OvmfPkg/SmmControl2Dxe: correct PCI_CONFIG_READ_WRITE in S3 boot script

EFI_BOOT_SCRIPT_PCI_CONFIG_READ_WRITE_OPCODE expects the PCI address to
access in UEFI encoding, not in edk2/PciLib encoding.

Introduce the POWER_MGMT_REGISTER_Q35_EFI_PCI_ADDRESS() macro, and with
it, store the ICH9_GEN_PMCON_1 register's address to the boot script in
UEFI representation.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

1 files changed, 4 insertions, 1 deletions

diff --git a/OvmfPkg/SmmControl2Dxe/SmmControl2Dxe.c b/OvmfPkg/SmmControl2Dxe/SmmControl2Dxe.c
index 82549b0a7e..6c03e17a3a 100644
--- a/OvmfPkg/SmmControl2Dxe/SmmControl2Dxe.c
+++ b/OvmfPkg/SmmControl2Dxe/SmmControl2Dxe.c
@@ -311,6 +311,7 @@ OnS3SaveStateInstalled (
   EFI_STATUS                 Status;

   EFI_S3_SAVE_STATE_PROTOCOL *S3SaveState;

   UINT32                     SmiEnOrMask, SmiEnAndMask;

+  UINT64                     GenPmCon1Address;

   UINT16                     GenPmCon1OrMask, GenPmCon1AndMask;

 

   ASSERT (Event == mS3SaveStateInstalled);

@@ -342,13 +343,15 @@ OnS3SaveStateInstalled (
     CpuDeadLoop ();

   }

 

+  GenPmCon1Address = POWER_MGMT_REGISTER_Q35_EFI_PCI_ADDRESS (

+                       ICH9_GEN_PMCON_1);

   GenPmCon1OrMask  = ICH9_GEN_PMCON_1_SMI_LOCK;

   GenPmCon1AndMask = MAX_UINT16;

   Status = S3SaveState->Write (

                           S3SaveState,

                           EFI_BOOT_SCRIPT_PCI_CONFIG_READ_WRITE_OPCODE,

                           EfiBootScriptWidthUint16,

-                          (UINT64)POWER_MGMT_REGISTER_Q35 (ICH9_GEN_PMCON_1),

+                          GenPmCon1Address,

                           &GenPmCon1OrMask,

                           &GenPmCon1AndMask

                           );