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| author | Gabriel Somlo <somlo@cmu.edu> | 2014-11-14 00:37:26 +0000 |
|---|---|---|
| committer | jljusten <jljusten@Edk2> | 2014-11-14 00:37:26 +0000 |
| commit | 97380beb15249f6abf4250ccccbae0f740649985 (patch) | |
| tree | 6eb7662a11e0d10d9622ad9de7f477862473e633 /OvmfPkg | |
| parent | 4e48c72c4cbbd24be3ec9835a7a428dce8064567 (diff) | |
| download | edk2-97380beb15249f6abf4250ccccbae0f740649985.tar.gz edk2-97380beb15249f6abf4250ccccbae0f740649985.tar.bz2 edk2-97380beb15249f6abf4250ccccbae0f740649985.zip | |
OvmfPkg: PlatformPei: Platform specific ACPI power management setup
Set up ACPI power management using registers determined based on
the underlying (PIIX4 or Q35/MCH) platform type.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gabriel Somlo <somlo@cmu.edu>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16373 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'OvmfPkg')
| -rw-r--r-- | OvmfPkg/PlatformPei/Platform.c | 43 |
1 files changed, 32 insertions, 11 deletions
diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c index 11b4cb7a14..d8a7c21ae0 100644 --- a/OvmfPkg/PlatformPei/Platform.c +++ b/OvmfPkg/PlatformPei/Platform.c @@ -35,6 +35,7 @@ #include <Guid/MemoryTypeInformation.h>
#include <Ppi/MasterBootMode.h>
#include <IndustryStandard/Pci22.h>
+#include <OvmfPlatforms.h>
#include "Platform.h"
#include "Cmos.h"
@@ -228,6 +229,11 @@ MiscInitialization ( VOID
)
{
+ UINT16 HostBridgeDevId;
+ UINTN PmCmd;
+ UINTN Pmba;
+ UINTN PmRegMisc;
+
//
// Disable A20 Mask
//
@@ -239,33 +245,48 @@ MiscInitialization ( BuildCpuHob (36, 16);
//
+ // Query Host Bridge DID to determine platform type
+ //
+ HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);
+ switch (HostBridgeDevId) {
+ case INTEL_82441_DEVICE_ID:
+ PmCmd = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);
+ Pmba = POWER_MGMT_REGISTER_PIIX4 (0x40);
+ PmRegMisc = POWER_MGMT_REGISTER_PIIX4 (0x80);
+ break;
+ case INTEL_Q35_MCH_DEVICE_ID:
+ PmCmd = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);
+ Pmba = POWER_MGMT_REGISTER_Q35 (0x40);
+ PmRegMisc = POWER_MGMT_REGISTER_Q35 (0x80);
+ break;
+ default:
+ DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",
+ __FUNCTION__, HostBridgeDevId));
+ ASSERT (FALSE);
+ return;
+ }
+
+ //
// If PMREGMISC/PMIOSE is set, assume the ACPI PMBA has been configured (for
// example by Xen) and skip the setup here. This matches the logic in
// AcpiTimerLibConstructor ().
//
- if ((PciRead8 (PCI_LIB_ADDRESS (0, 1, 3, 0x80)) & 0x01) == 0) {
+ if ((PciRead8 (PmRegMisc) & 0x01) == 0) {
//
// The PEI phase should be exited with fully accessibe PIIX4 IO space:
// 1. set PMBA
//
- PciAndThenOr32 (
- PCI_LIB_ADDRESS (0, 1, 3, 0x40),
- (UINT32) ~0xFFC0,
- PcdGet16 (PcdAcpiPmBaseAddress)
- );
+ PciAndThenOr32 (Pmba, (UINT32) ~0xFFC0, PcdGet16 (PcdAcpiPmBaseAddress));
//
// 2. set PCICMD/IOSE
//
- PciOr8 (
- PCI_LIB_ADDRESS (0, 1, 3, PCI_COMMAND_OFFSET),
- EFI_PCI_COMMAND_IO_SPACE
- );
+ PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);
//
// 3. set PMREGMISC/PMIOSE
//
- PciOr8 (PCI_LIB_ADDRESS (0, 1, 3, 0x80), 0x01);
+ PciOr8 (PmRegMisc, 0x01);
}
}
|