diff options
| author | mdkinney <mdkinney@6f19259b-4bc3-4df7-8a09-765794883524> | 2011-09-02 02:43:51 +0000 |
|---|---|---|
| committer | mdkinney <mdkinney@6f19259b-4bc3-4df7-8a09-765794883524> | 2011-09-02 02:43:51 +0000 |
| commit | 986d1dfb0813d6a7623531e85c2e2a7e1f956cf8 (patch) | |
| tree | 089ccd87cb8053f4836453c8fdfa30164d2c2496 /PcAtChipsetPkg/Include/Library | |
| parent | 5f867ad00d499debbf22dee044b22e01b63e1ade (diff) | |
| download | edk2-986d1dfb0813d6a7623531e85c2e2a7e1f956cf8.tar.gz edk2-986d1dfb0813d6a7623531e85c2e2a7e1f956cf8.tar.bz2 edk2-986d1dfb0813d6a7623531e85c2e2a7e1f956cf8.zip | |
Add generic HPET Timer DXE Driver and support libraries
Signed-off-by: mdkinney
Reviewed-by: li-elvin
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12260 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'PcAtChipsetPkg/Include/Library')
| -rw-r--r-- | PcAtChipsetPkg/Include/Library/IoApicLib.h | 102 |
1 files changed, 102 insertions, 0 deletions
diff --git a/PcAtChipsetPkg/Include/Library/IoApicLib.h b/PcAtChipsetPkg/Include/Library/IoApicLib.h new file mode 100644 index 0000000000..bd9054be53 --- /dev/null +++ b/PcAtChipsetPkg/Include/Library/IoApicLib.h @@ -0,0 +1,102 @@ +/** @file
+ Public include file for I/O APIC library.
+
+ I/O APIC library assumes I/O APIC is enabled. It does not
+ handles cases where I/O APIC is disabled.
+
+ Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+/**
+ Read a 32-bit I/O APIC register.
+
+ If Index is >= 0x100, then ASSERT().
+
+ @param Index Specifies the I/O APIC register to read.
+
+ @return The 32-bit value read from the I/O APIC register specified by Index.
+**/
+UINT32
+EFIAPI
+IoApicRead (
+ IN UINTN Index
+ );
+
+/**
+ Write a 32-bit I/O APIC register.
+
+ If Index is >= 0x100, then ASSERT().
+
+ @param Index Specifies the I/O APIC register to write.
+ @param Value Specifies the value to write to the I/O APIC register specified by Index.
+
+ @return The 32-bit value written to I/O APIC register specified by Index.
+**/
+UINT32
+EFIAPI
+IoApicWrite (
+ IN UINTN Index,
+ IN UINT32 Value
+ );
+
+/**
+ Set the interrupt mask of an I/O APIC interrupt.
+
+ If Irq is larger than the maximum number I/O APIC redirection entries, then ASSERT().
+
+ @param Irq Specifies the I/O APIC interrupt to enable or disable.
+ @param Enable If TRUE, then enable the I/O APIC interrupt specified by Irq.
+ If FALSE, then disable the I/O APIC interrupt specified by Irq.
+**/
+VOID
+EFIAPI
+IoApicEnableInterrupt (
+ IN UINTN Irq,
+ IN BOOLEAN Enable
+ );
+
+/**
+ Configures an I/O APIC interrupt.
+
+ Configure an I/O APIC Redirection Table Entry to deliver an interrupt in physical
+ mode to the Local APIC of the currntly executing CPU. The default state of the
+ entry is for the interrupt to be disabled (masked). IoApicEnableInterrupts() must
+ be used to enable(unmask) the I/O APIC Interrupt.
+
+ If Irq is larger than the maximum number I/O APIC redirection entries, then ASSERT().
+ If Vector >= 0x100, then ASSERT().
+ If DeliveryMode is not supported, then ASSERT().
+
+ @param Irq Specifies the I/O APIC interrupt to initialize.
+ @param Vector The 8-bit interrupt vector associated with the I/O APIC
+ Interrupt. Must be in the range 0x10..0xFE.
+ @param DeliveryMode A 3-bit value that specifies how the recept of the I/O APIC
+ interrupt is handled. The only supported values are:
+ 0: IO_APIC_DELIVERY_MODE_FIXED
+ 1: IO_APIC_DELIVERY_MODE_LOWEST_PRIORITY
+ 2: IO_APIC_DELIVERY_MODE_SMI
+ 4: IO_APIC_DELIVERY_MODE_NMI
+ 5: IO_APIC_DELIVERY_MODE_INIT
+ 7: IO_APIC_DELIVERY_MODE_EXTINT
+ @param LevelTriggered TRUE specifies a level triggered interrupt.
+ FALSE specifies an edge triggered interrupt.
+ @param AssertionLevel TRUE specified an active high interrupt.
+ FALSE specifies an active low interrupt.
+**/
+VOID
+EFIAPI
+IoApicConfigureInterrupt (
+ IN UINTN Irq,
+ IN UINTN Vector,
+ IN UINTN DeliveryMode,
+ IN BOOLEAN LevelTriggered,
+ IN BOOLEAN AssertionLevel
+ );
|