PcAtChipsetPkg: Fix spelling errors

https://bugzilla.tianocore.org/show_bug.cgi?id=2263

Cc: Ray Ni <ray.ni@intel.com>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>

2 files changed, 4 insertions, 4 deletions

diff --git a/PcAtChipsetPkg/Include/Library/IoApicLib.h b/PcAtChipsetPkg/Include/Library/IoApicLib.h
index 200ef731fb..4ee092c0f2 100644
--- a/PcAtChipsetPkg/Include/Library/IoApicLib.h
+++ b/PcAtChipsetPkg/Include/Library/IoApicLib.h
@@ -63,7 +63,7 @@ IoApicEnableInterrupt (
   Configures an I/O APIC interrupt.

 

   Configure an I/O APIC Redirection Table Entry to deliver an interrupt in physical

-  mode to the Local APIC of the currntly executing CPU.  The default state of the

+  mode to the Local APIC of the currently executing CPU.  The default state of the

   entry is for the interrupt to be disabled (masked).  IoApicEnableInterrupts() must

   be used to enable(unmask) the I/O APIC Interrupt.

 

diff --git a/PcAtChipsetPkg/Include/Register/Hpet.h b/PcAtChipsetPkg/Include/Register/Hpet.h
index f7c0174e14..8437ec1f2d 100644
--- a/PcAtChipsetPkg/Include/Register/Hpet.h
+++ b/PcAtChipsetPkg/Include/Register/Hpet.h
@@ -70,14 +70,14 @@ typedef union {
     UINT32  LevelTriggeredInterrupt:1;

     UINT32  InterruptEnable:1;

     UINT32  PeriodicInterruptEnable:1;

-    UINT32  PeriodicInterruptCapablity:1;

-    UINT32  CounterSizeCapablity:1;

+    UINT32  PeriodicInterruptCapability:1;

+    UINT32  CounterSizeCapability:1;

     UINT32  ValueSetEnable:1;

     UINT32  Reserved1:1;

     UINT32  CounterSizeEnable:1;

     UINT32  InterruptRoute:5;

     UINT32  MsiInterruptEnable:1;

-    UINT32  MsiInterruptCapablity:1;

+    UINT32  MsiInterruptCapability:1;

     UINT32  Reserved2:16;

     UINT32  InterruptRouteCapability;

   } Bits;