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| author | Michael Kubacki <michael.kubacki@microsoft.com> | 2021-12-05 14:54:12 -0800 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2021-12-07 17:24:28 +0000 |
| commit | c411b485b63a671a1e276700cff025c73997233c (patch) | |
| tree | e7a57ca51b659161ab4bc9da95e988760ec57e7a /SecurityPkg/Include/Library/TpmCommLib.h | |
| parent | 39de741e2dcb8f11e9b4438e37224797643d8451 (diff) | |
| download | edk2-c411b485b63a671a1e276700cff025c73997233c.tar.gz edk2-c411b485b63a671a1e276700cff025c73997233c.tar.bz2 edk2-c411b485b63a671a1e276700cff025c73997233c.zip | |
SecurityPkg: Apply uncrustify changes
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737
Apply uncrustify changes to .c/.h files in the SecurityPkg package
Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
Diffstat (limited to 'SecurityPkg/Include/Library/TpmCommLib.h')
| -rw-r--r-- | SecurityPkg/Include/Library/TpmCommLib.h | 86 |
1 files changed, 43 insertions, 43 deletions
diff --git a/SecurityPkg/Include/Library/TpmCommLib.h b/SecurityPkg/Include/Library/TpmCommLib.h index 1d18f8d837..4810ce4b2e 100644 --- a/SecurityPkg/Include/Library/TpmCommLib.h +++ b/SecurityPkg/Include/Library/TpmCommLib.h @@ -12,12 +12,12 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include <IndustryStandard/Tpm12.h>
-typedef EFI_HANDLE TIS_TPM_HANDLE;
+typedef EFI_HANDLE TIS_TPM_HANDLE;
///
/// TPM register base address.
///
-#define TPM_BASE_ADDRESS 0xfed40000
+#define TPM_BASE_ADDRESS 0xfed40000
//
// Set structure alignment to 1-byte
@@ -31,75 +31,75 @@ typedef struct { ///
/// Used to gain ownership for this particular port.
///
- UINT8 Access; // 0
- UINT8 Reserved1[7]; // 1
+ UINT8 Access; // 0
+ UINT8 Reserved1[7]; // 1
///
/// Controls interrupts.
///
- UINT32 IntEnable; // 8
+ UINT32 IntEnable; // 8
///
/// SIRQ vector to be used by the TPM.
///
- UINT8 IntVector; // 0ch
- UINT8 Reserved2[3]; // 0dh
+ UINT8 IntVector; // 0ch
+ UINT8 Reserved2[3]; // 0dh
///
/// What caused interrupt.
///
- UINT32 IntSts; // 10h
+ UINT32 IntSts; // 10h
///
/// Shows which interrupts are supported by that particular TPM.
///
- UINT32 IntfCapability; // 14h
+ UINT32 IntfCapability; // 14h
///
/// Status Register. Provides status of the TPM.
///
- UINT8 Status; // 18h
+ UINT8 Status; // 18h
///
/// Number of consecutive writes that can be done to the TPM.
///
- UINT16 BurstCount; // 19h
- UINT8 Reserved3[9];
+ UINT16 BurstCount; // 19h
+ UINT8 Reserved3[9];
///
/// Read or write FIFO, depending on transaction.
///
- UINT32 DataFifo; // 24
- UINT8 Reserved4[0xed8]; // 28h
+ UINT32 DataFifo; // 24
+ UINT8 Reserved4[0xed8]; // 28h
///
/// Vendor ID
///
- UINT16 Vid; // 0f00h
+ UINT16 Vid; // 0f00h
///
/// Device ID
///
- UINT16 Did; // 0f02h
+ UINT16 Did; // 0f02h
///
/// Revision ID
///
- UINT8 Rid; // 0f04h
+ UINT8 Rid; // 0f04h
///
/// TCG defined configuration registers.
///
- UINT8 TcgDefined[0x7b]; // 0f05h
+ UINT8 TcgDefined[0x7b]; // 0f05h
///
/// Alias to I/O legacy space.
///
- UINT32 LegacyAddress1; // 0f80h
+ UINT32 LegacyAddress1; // 0f80h
///
/// Additional 8 bits for I/O legacy space extension.
///
- UINT32 LegacyAddress1Ex; // 0f84h
+ UINT32 LegacyAddress1Ex; // 0f84h
///
/// Alias to second I/O legacy space.
///
- UINT32 LegacyAddress2; // 0f88h
+ UINT32 LegacyAddress2; // 0f88h
///
/// Additional 8 bits for second I/O legacy space extension.
///
- UINT32 LegacyAddress2Ex; // 0f8ch
+ UINT32 LegacyAddress2Ex; // 0f8ch
///
/// Vendor-defined configuration registers.
///
- UINT8 VendorDefined[0x70];// 0f90h
+ UINT8 VendorDefined[0x70]; // 0f90h
} TIS_PC_REGISTERS;
//
@@ -110,13 +110,13 @@ typedef struct { //
// Define pointer types used to access TIS registers on PC
//
-typedef TIS_PC_REGISTERS *TIS_PC_REGISTERS_PTR;
+typedef TIS_PC_REGISTERS *TIS_PC_REGISTERS_PTR;
//
// TCG Platform Type based on TCG ACPI Specification Version 1.00
//
-#define TCG_PLATFORM_TYPE_CLIENT 0
-#define TCG_PLATFORM_TYPE_SERVER 1
+#define TCG_PLATFORM_TYPE_CLIENT 0
+#define TCG_PLATFORM_TYPE_SERVER 1
//
// Define bits of ACCESS and STATUS registers
@@ -125,69 +125,69 @@ typedef TIS_PC_REGISTERS *TIS_PC_REGISTERS_PTR; ///
/// This bit is a 1 to indicate that the other bits in this register are valid.
///
-#define TIS_PC_VALID BIT7
+#define TIS_PC_VALID BIT7
///
/// Indicate that this locality is active.
///
-#define TIS_PC_ACC_ACTIVE BIT5
+#define TIS_PC_ACC_ACTIVE BIT5
///
/// Set to 1 to indicate that this locality had the TPM taken away while
/// this locality had the TIS_PC_ACC_ACTIVE bit set.
///
-#define TIS_PC_ACC_SEIZED BIT4
+#define TIS_PC_ACC_SEIZED BIT4
///
/// Set to 1 to indicate that TPM MUST reset the
/// TIS_PC_ACC_ACTIVE bit and remove ownership for localities less than the
/// locality that is writing this bit.
///
-#define TIS_PC_ACC_SEIZE BIT3
+#define TIS_PC_ACC_SEIZE BIT3
///
/// When this bit is 1, another locality is requesting usage of the TPM.
///
-#define TIS_PC_ACC_PENDIND BIT2
+#define TIS_PC_ACC_PENDIND BIT2
///
/// Set to 1 to indicate that this locality is requesting to use TPM.
///
-#define TIS_PC_ACC_RQUUSE BIT1
+#define TIS_PC_ACC_RQUUSE BIT1
///
/// A value of 1 indicates that a T/OS has not been established on the platform
///
-#define TIS_PC_ACC_ESTABLISH BIT0
+#define TIS_PC_ACC_ESTABLISH BIT0
///
/// When this bit is 1, TPM is in the Ready state,
/// indicating it is ready to receive a new command.
///
-#define TIS_PC_STS_READY BIT6
+#define TIS_PC_STS_READY BIT6
///
/// Write a 1 to this bit to cause the TPM to execute that command.
///
-#define TIS_PC_STS_GO BIT5
+#define TIS_PC_STS_GO BIT5
///
/// This bit indicates that the TPM has data available as a response.
///
-#define TIS_PC_STS_DATA BIT4
+#define TIS_PC_STS_DATA BIT4
///
/// The TPM sets this bit to a value of 1 when it expects another byte of data for a command.
///
-#define TIS_PC_STS_EXPECT BIT3
+#define TIS_PC_STS_EXPECT BIT3
///
/// Writes a 1 to this bit to force the TPM to re-send the response.
///
-#define TIS_PC_STS_RETRY BIT1
+#define TIS_PC_STS_RETRY BIT1
//
// Default TimeOut value
//
-#define TIS_TIMEOUT_A 750 * 1000 // 750ms
-#define TIS_TIMEOUT_B 2000 * 1000 // 2s
-#define TIS_TIMEOUT_C 750 * 1000 // 750ms
-#define TIS_TIMEOUT_D 750 * 1000 // 750ms
+#define TIS_TIMEOUT_A 750 * 1000 // 750ms
+#define TIS_TIMEOUT_B 2000 * 1000 // 2s
+#define TIS_TIMEOUT_C 750 * 1000 // 750ms
+#define TIS_TIMEOUT_D 750 * 1000 // 750ms
//
// Max TPM command/response length
//
-#define TPMCMDBUFLENGTH 1024
+#define TPMCMDBUFLENGTH 1024
/**
Check whether the value of a TPM chip register satisfies the input BIT setting.
|