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authorNi, Ray <ray.ni@intel.com>2019-08-01 17:58:26 +0800
committerEric Dong <eric.dong@intel.com>2019-08-09 08:52:08 +0800
commite58aa474329ef63a64150b7625c56b48a00e31da (patch)
treee906bf28b38d841d0bb8484f2c253930d2c71957 /UefiCpuPkg/CpuDxe/CpuPageTable.h
parent29355b4e1aed751addce6ffd85fbb65a2f409a33 (diff)
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UefiCpuPkg/CpuDxe: Support parsing 5-level page table
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2008 Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Eric Dong <eric.dong@intel.com>
Diffstat (limited to 'UefiCpuPkg/CpuDxe/CpuPageTable.h')
-rw-r--r--UefiCpuPkg/CpuDxe/CpuPageTable.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/UefiCpuPkg/CpuDxe/CpuPageTable.h b/UefiCpuPkg/CpuDxe/CpuPageTable.h
index 02d62f2b14..f845956f73 100644
--- a/UefiCpuPkg/CpuDxe/CpuPageTable.h
+++ b/UefiCpuPkg/CpuDxe/CpuPageTable.h
@@ -1,7 +1,7 @@
/** @file
Page table management header file.
- Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -14,6 +14,7 @@
#define PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PSE BIT0
#define PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PAE BIT1
#define PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PAGE_1G_SUPPORT BIT2
+#define PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_5_LEVEL BIT3
#define PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_WP_ENABLE BIT30
#define PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_XD_ACTIVATED BIT31
// Other bits are reserved for future use