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| author | Jeff Fan <jeff.fan@intel.com> | 2017-03-15 09:47:52 +0800 |
|---|---|---|
| committer | Jeff Fan <jeff.fan@intel.com> | 2017-03-17 13:55:12 +0800 |
| commit | 01eb3f39bbcc5b6474d69cff3922be8eb1856636 (patch) | |
| tree | f30eb739a013a3e45389b12916a8a66d8c6a346e /UefiCpuPkg/CpuDxe | |
| parent | 78807f605082ecec60c3b465a6e6f3e01741bf2c (diff) | |
| download | edk2-01eb3f39bbcc5b6474d69cff3922be8eb1856636.tar.gz edk2-01eb3f39bbcc5b6474d69cff3922be8eb1856636.tar.bz2 edk2-01eb3f39bbcc5b6474d69cff3922be8eb1856636.zip | |
UefiCpuPkg/CpuDxe: Remove MSR_IA32_MISC_ENABLE check
The architectural MSR MSR_IA32_MISC_ENABLE is not supported by AMD processors.
Because reading CPUID.80000001H:EDK[20] is enough to check if XD feature is
supported or not, we just remove checking MSR_IA32_MISC_ENABLE(0x1A0).
Cc: Anthony PERARD <anthony.perard@citrix.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Tested-by: Anthony PERARD <anthony.perard@citrix.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
Diffstat (limited to 'UefiCpuPkg/CpuDxe')
| -rw-r--r-- | UefiCpuPkg/CpuDxe/CpuPageTable.c | 9 |
1 files changed, 3 insertions, 6 deletions
diff --git a/UefiCpuPkg/CpuDxe/CpuPageTable.c b/UefiCpuPkg/CpuDxe/CpuPageTable.c index 65f607a90c..ab664b47d6 100644 --- a/UefiCpuPkg/CpuDxe/CpuPageTable.c +++ b/UefiCpuPkg/CpuDxe/CpuPageTable.c @@ -193,12 +193,9 @@ GetCurrentPagingContext ( AsmCpuid (0x80000001, NULL, NULL, NULL, &RegEdx);
if ((RegEdx & BIT20) != 0) {
// XD supported
- if ((AsmReadMsr64 (0x000001A0) & BIT34) == 0) {
- // XD enabled
- if ((AsmReadMsr64 (0xC0000080) & BIT11) != 0) {
- // XD activated
- PagingContext->ContextData.Ia32.Attributes |= PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_XD_ACTIVATED;
- }
+ if ((AsmReadMsr64 (0xC0000080) & BIT11) != 0) {
+ // XD activated
+ PagingContext->ContextData.Ia32.Attributes |= PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_XD_ACTIVATED;
}
}
if ((RegEdx & BIT26) != 0) {
|