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| author | Eric Dong <eric.dong@intel.com> | 2017-08-02 18:29:09 +0800 |
|---|---|---|
| committer | Eric Dong <eric.dong@intel.com> | 2017-08-07 15:28:12 +0800 |
| commit | c894f83fe35948f02b38fcc57c35998d1b88c14d (patch) | |
| tree | 3cb6825c955776c27fa09bef9ecef98c937d1520 /UefiCpuPkg/CpuDxe | |
| parent | 055fa1c6661dfb421568ab73ca6a7e4f723f60de (diff) | |
| download | edk2-c894f83fe35948f02b38fcc57c35998d1b88c14d.tar.gz edk2-c894f83fe35948f02b38fcc57c35998d1b88c14d.tar.bz2 edk2-c894f83fe35948f02b38fcc57c35998d1b88c14d.zip | |
UefiCpuPkg CpuDxe: Enhance get mtrr mask logic.
In order to not use the deprecated macro, refine
get mtrr mask value logic.
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
Diffstat (limited to 'UefiCpuPkg/CpuDxe')
| -rw-r--r-- | UefiCpuPkg/CpuDxe/CpuDxe.c | 13 |
1 files changed, 6 insertions, 7 deletions
diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.c b/UefiCpuPkg/CpuDxe/CpuDxe.c index 86806568a9..621867090f 100644 --- a/UefiCpuPkg/CpuDxe/CpuDxe.c +++ b/UefiCpuPkg/CpuDxe/CpuDxe.c @@ -25,8 +25,8 @@ BOOLEAN InterruptState = FALSE;
EFI_HANDLE mCpuHandle = NULL;
BOOLEAN mIsFlushingGCD;
-UINT64 mValidMtrrAddressMask = MTRR_LIB_CACHE_VALID_ADDRESS;
-UINT64 mValidMtrrBitsMask = MTRR_LIB_MSR_VALID_MASK;
+UINT64 mValidMtrrAddressMask;
+UINT64 mValidMtrrBitsMask;
UINT64 mTimerPeriod = 0;
FIXED_MTRR mFixedMtrrTable[] = {
@@ -510,13 +510,12 @@ InitializeMtrrMask ( AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);
PhysicalAddressBits = (UINT8) RegEax;
-
- mValidMtrrBitsMask = LShiftU64 (1, PhysicalAddressBits) - 1;
- mValidMtrrAddressMask = mValidMtrrBitsMask & 0xfffffffffffff000ULL;
} else {
- mValidMtrrBitsMask = MTRR_LIB_MSR_VALID_MASK;
- mValidMtrrAddressMask = MTRR_LIB_CACHE_VALID_ADDRESS;
+ PhysicalAddressBits = 36;
}
+
+ mValidMtrrBitsMask = LShiftU64 (1, PhysicalAddressBits) - 1;
+ mValidMtrrAddressMask = mValidMtrrBitsMask & 0xfffffffffffff000ULL;
}
/**
|