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| author | Jeff Fan <jeff.fan@intel.com> | 2017-03-07 11:14:35 +0800 |
|---|---|---|
| committer | Jeff Fan <jeff.fan@intel.com> | 2017-03-22 10:11:34 +0800 |
| commit | f4c982bf095307fc598cf07f7b157831030b77f1 (patch) | |
| tree | c22da88b87636f8b8be8b67fbafaa4b689da0f12 /UefiCpuPkg/Include/Register/Msr/XeonDMsr.h | |
| parent | 30d995ee083653a408df8ee1a3e37198f5b1454e (diff) | |
| download | edk2-f4c982bf095307fc598cf07f7b157831030b77f1.tar.gz edk2-f4c982bf095307fc598cf07f7b157831030b77f1.tar.bz2 edk2-f4c982bf095307fc598cf07f7b157831030b77f1.zip | |
UefiCpuPkg/Msr: Add CPUID signature check MACROs
All model-specific MSRs are related to processor signatures that are defined in
each section in Chapter 35 Model-Specific-Registers (MSR), Intel(R) 64 and
IA-32 Architectures Software Developer's Manual, Volume 3, September 2016.
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
Diffstat (limited to 'UefiCpuPkg/Include/Register/Msr/XeonDMsr.h')
| -rw-r--r-- | UefiCpuPkg/Include/Register/Msr/XeonDMsr.h | 19 |
1 files changed, 18 insertions, 1 deletions
diff --git a/UefiCpuPkg/Include/Register/Msr/XeonDMsr.h b/UefiCpuPkg/Include/Register/Msr/XeonDMsr.h index 5e7e13aa8e..7b31288a35 100644 --- a/UefiCpuPkg/Include/Register/Msr/XeonDMsr.h +++ b/UefiCpuPkg/Include/Register/Msr/XeonDMsr.h @@ -6,7 +6,7 @@ returned is a single 32-bit or 64-bit value, then a data structure is not
provided for that MSR.
- Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -27,6 +27,23 @@ #include <Register/ArchitecturalMsr.h>
/**
+ Is Intel(R) Xeon(R) Processor D product Family?
+
+ @param DisplayFamily Display Family ID
+ @param DisplayModel Display Model ID
+
+ @retval TRUE Yes, it is.
+ @retval FALSE No, it isn't.
+**/
+#define IS_XEON_D_PROCESSOR(DisplayFamily, DisplayModel) \
+ (DisplayFamily == 0x06 && \
+ ( \
+ DisplayModel == 0x4F || \
+ DisplayModel == 0x56 \
+ ) \
+ )
+
+/**
Package. Protected Processor Inventory Number Enable Control (R/W).
@param ECX MSR_XEON_D_PPIN_CTL (0x0000004E)
|