diff options
| author | Liming Gao <liming.gao@intel.com> | 2016-06-14 15:58:31 +0800 |
|---|---|---|
| committer | Liming Gao <liming.gao@intel.com> | 2016-06-28 09:52:07 +0800 |
| commit | f893042d05c9ec7a889ee5b74b4ca5090c553daf (patch) | |
| tree | 7c433ed1c70c0b7c2382a0e83a5f2fb4eacf55d5 /UefiCpuPkg/Library/BaseUefiCpuLib | |
| parent | b85a6ffb441129889c301459207a729d562ab8e8 (diff) | |
| download | edk2-f893042d05c9ec7a889ee5b74b4ca5090c553daf.tar.gz edk2-f893042d05c9ec7a889ee5b74b4ca5090c553daf.tar.bz2 edk2-f893042d05c9ec7a889ee5b74b4ca5090c553daf.zip | |
UefiCpuPkg BaseUefiCpuLib: Convert Ia32/InitializeFpu.asm to NASM
The BaseTools/Scripts/ConvertMasmToNasm.py script was used to convert
Ia32/InitializeFpu.asm to Ia32/InitializeFpu.nasm.
And, manually add .rdata section.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
Diffstat (limited to 'UefiCpuPkg/Library/BaseUefiCpuLib')
| -rw-r--r-- | UefiCpuPkg/Library/BaseUefiCpuLib/Ia32/InitializeFpu.nasm | 74 |
1 files changed, 74 insertions, 0 deletions
diff --git a/UefiCpuPkg/Library/BaseUefiCpuLib/Ia32/InitializeFpu.nasm b/UefiCpuPkg/Library/BaseUefiCpuLib/Ia32/InitializeFpu.nasm new file mode 100644 index 0000000000..55085e019f --- /dev/null +++ b/UefiCpuPkg/Library/BaseUefiCpuLib/Ia32/InitializeFpu.nasm @@ -0,0 +1,74 @@ +;------------------------------------------------------------------------------
+;*
+;* Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+;* This program and the accompanying materials
+;* are licensed and made available under the terms and conditions of the BSD License
+;* which accompanies this distribution. The full text of the license may be found at
+;* http://opensource.org/licenses/bsd-license.php
+;*
+;* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;*
+;*
+;------------------------------------------------------------------------------
+
+ SECTION .rdata
+
+;
+; Float control word initial value:
+; all exceptions masked, double-precision, round-to-nearest
+;
+mFpuControlWord: DW 0x27F
+;
+; Multimedia-extensions control word:
+; all exceptions masked, round-to-nearest, flush to zero for masked underflow
+;
+mMmxControlWord: DD 0x1F80
+
+ SECTION .text
+
+;
+; Initializes floating point units for requirement of UEFI specification.
+;
+; This function initializes floating-point control word to 0x027F (all exceptions
+; masked,double-precision, round-to-nearest) and multimedia-extensions control word
+; (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero
+; for masked underflow).
+;
+global ASM_PFX(InitializeFloatingPointUnits)
+ASM_PFX(InitializeFloatingPointUnits):
+
+ push ebx
+
+ ;
+ ; Initialize floating point units
+ ;
+ finit
+ fldcw [mFpuControlWord]
+
+ ;
+ ; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test
+ ; whether the processor supports SSE instruction.
+ ;
+ mov eax, 1
+ cpuid
+ bt edx, 25
+ jnc Done
+
+ ;
+ ; Set OSFXSR bit 9 in CR4
+ ;
+ mov eax, cr4
+ or eax, BIT9
+ mov cr4, eax
+
+ ;
+ ; The processor should support SSE instruction and we can use
+ ; ldmxcsr instruction
+ ;
+ ldmxcsr [mMmxControlWord]
+Done:
+ pop ebx
+
+ ret
+
|