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| author | Liming Gao <liming.gao@intel.com> | 2018-01-11 17:05:13 +0800 |
|---|---|---|
| committer | Liming Gao <liming.gao@intel.com> | 2018-01-16 23:42:48 +0800 |
| commit | 2db0ccc2d7fef249487f95db41042943c0617f54 (patch) | |
| tree | fb4ceba6d6d731338f4035e21961be21a042a5e4 /UefiCpuPkg/Library/CpuExceptionHandlerLib | |
| parent | 62382925c90eb54de6413208f561b24a0b97e337 (diff) | |
| download | edk2-2db0ccc2d7fef249487f95db41042943c0617f54.tar.gz edk2-2db0ccc2d7fef249487f95db41042943c0617f54.tar.bz2 edk2-2db0ccc2d7fef249487f95db41042943c0617f54.zip | |
UefiCpuPkg: Update CpuExceptionHandlerLib pass XCODE5 tool chain
https://bugzilla.tianocore.org/show_bug.cgi?id=849
In V2, use mov rax, strict qword 0 to replace the hard code db.
Use the dummy address as jmp destination, and add the logic to fix up
the address to the absolute address at boot time.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Liming Gao <liming.gao@intel.com>
Cc: Andrew Fish <afish@apple.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Diffstat (limited to 'UefiCpuPkg/Library/CpuExceptionHandlerLib')
| -rw-r--r-- | UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm | 27 |
1 files changed, 20 insertions, 7 deletions
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm index ba8993d84b..7b97810d10 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm @@ -1,5 +1,5 @@ ;------------------------------------------------------------------------------ ;
-; Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.<BR>
; This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
@@ -40,7 +40,7 @@ AsmIdtVectorBegin: db 0x6a ; push #VectorNum
db ($ - AsmIdtVectorBegin) / ((AsmIdtVectorEnd - AsmIdtVectorBegin) / 32) ; VectorNum
push rax
- mov rax, ASM_PFX(CommonInterruptEntry)
+ mov rax, strict qword 0 ; mov rax, ASM_PFX(CommonInterruptEntry)
jmp rax
%endrep
AsmIdtVectorEnd:
@@ -50,7 +50,8 @@ HookAfterStubHeaderBegin: @VectorNum:
db 0 ; 0 will be fixed
push rax
- mov rax, HookAfterStubHeaderEnd
+ mov rax, strict qword 0 ; mov rax, HookAfterStubHeaderEnd
+JmpAbsoluteAddress:
jmp rax
HookAfterStubHeaderEnd:
mov rax, rsp
@@ -260,8 +261,7 @@ HasErrorCode: ; and make sure RSP is 16-byte aligned
;
sub rsp, 4 * 8 + 8
- mov rax, ASM_PFX(CommonExceptionHandler)
- call rax
+ call ASM_PFX(CommonExceptionHandler)
add rsp, 4 * 8 + 8
cli
@@ -369,11 +369,24 @@ DoIret: ; comments here for definition of address map
global ASM_PFX(AsmGetTemplateAddressMap)
ASM_PFX(AsmGetTemplateAddressMap):
- mov rax, AsmIdtVectorBegin
+ lea rax, [AsmIdtVectorBegin]
mov qword [rcx], rax
mov qword [rcx + 0x8], (AsmIdtVectorEnd - AsmIdtVectorBegin) / 32
- mov rax, HookAfterStubHeaderBegin
+ lea rax, [HookAfterStubHeaderBegin]
mov qword [rcx + 0x10], rax
+
+; Fix up CommonInterruptEntry address
+ lea rax, [ASM_PFX(CommonInterruptEntry)]
+ lea rcx, [AsmIdtVectorBegin]
+%rep 32
+ mov qword [rcx + (JmpAbsoluteAddress - 8 - HookAfterStubHeaderBegin)], rax
+ add rcx, (AsmIdtVectorEnd - AsmIdtVectorBegin) / 32
+%endrep
+; Fix up HookAfterStubHeaderEnd
+ lea rax, [HookAfterStubHeaderEnd]
+ lea rcx, [JmpAbsoluteAddress]
+ mov qword [rcx - 8], rax
+
ret
;-------------------------------------------------------------------------------------
|