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| author | Ni, Ray <ray.ni@intel.com> | 2019-08-01 17:58:24 +0800 |
|---|---|---|
| committer | Eric Dong <eric.dong@intel.com> | 2019-08-09 08:52:08 +0800 |
| commit | 09f69a877b1b499ff4b6bd6450dc531a19d7ed72 (patch) | |
| tree | 402b3452df4065df3b765412c9fdabd07a6079a8 /UefiCpuPkg/Library/MpInitLib/MpLib.c | |
| parent | 1ab7d72651bb254fa9bcb20fd3da2685fc142ea1 (diff) | |
| download | edk2-09f69a877b1b499ff4b6bd6450dc531a19d7ed72.tar.gz edk2-09f69a877b1b499ff4b6bd6450dc531a19d7ed72.tar.bz2 edk2-09f69a877b1b499ff4b6bd6450dc531a19d7ed72.zip | |
UefiCpuPkg/MpInitLib: Enable 5-level paging for AP when BSP's enabled
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2008
MpInitLib is the library that's responsible to wake up APs to provide
MP PPI and Protocol services.
The patch synchronizes BSP's CR4.LA57 to each AP's CR4.LA57.
Without this change, AP may enter to GP fault when BSP's 5-level page
table is set to AP during AP wakes up.
Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Eric Dong <eric.dong@intel.com>
Diffstat (limited to 'UefiCpuPkg/Library/MpInitLib/MpLib.c')
| -rw-r--r-- | UefiCpuPkg/Library/MpInitLib/MpLib.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpInitLib/MpLib.c index a1ad665564..d6f84c6f45 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c @@ -790,6 +790,7 @@ FillExchangeInfoData ( volatile MP_CPU_EXCHANGE_INFO *ExchangeInfo;
UINTN Size;
IA32_SEGMENT_DESCRIPTOR *Selector;
+ IA32_CR4 Cr4;
ExchangeInfo = CpuMpData->MpCpuExchangeInfo;
ExchangeInfo->Lock = 0;
@@ -815,6 +816,18 @@ FillExchangeInfoData ( ExchangeInfo->InitializeFloatingPointUnitsAddress = (UINTN)InitializeFloatingPointUnits;
//
+ // We can check either CPUID(7).ECX[bit16] or check CR4.LA57[bit12]
+ // to determin whether 5-Level Paging is enabled.
+ // CPUID(7).ECX[bit16] shows CPU's capability, CR4.LA57[bit12] shows
+ // current system setting.
+ // Using latter way is simpler because it also eliminates the needs to
+ // check whether platform wants to enable it.
+ //
+ Cr4.UintN = AsmReadCr4 ();
+ ExchangeInfo->Enable5LevelPaging = (BOOLEAN) (Cr4.Bits.LA57 == 1);
+ DEBUG ((DEBUG_INFO, "%a: 5-Level Paging = %d\n", gEfiCallerBaseName, ExchangeInfo->Enable5LevelPaging));
+
+ //
// Get the BSP's data of GDT and IDT
//
AsmReadGdtr ((IA32_DESCRIPTOR *) &ExchangeInfo->GdtrProfile);
|