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| author | Brijesh Singh <brijesh.singh@amd.com> | 2021-12-09 11:27:54 +0800 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2021-12-09 06:28:10 +0000 |
| commit | 9c703bc0f1d6972ef44d55d9a5243f8558c564e4 (patch) | |
| tree | c92dc900755f777de0899cebbd26cfdbe5de18e8 /UefiCpuPkg/Library/MpInitLib/MpLib.c | |
| parent | 2c354252be0ef156a80540555d7293800a200ecd (diff) | |
| download | edk2-9c703bc0f1d6972ef44d55d9a5243f8558c564e4.tar.gz edk2-9c703bc0f1d6972ef44d55d9a5243f8558c564e4.tar.bz2 edk2-9c703bc0f1d6972ef44d55d9a5243f8558c564e4.zip | |
UefiCpuPkg/MpLib: add support to register GHCB GPA when SEV-SNP is enabled
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275
An SEV-SNP guest requires that the physical address of the GHCB must
be registered with the hypervisor before using it. See the GHCB
specification section 2.3.2 for more details.
Cc: Michael Roth <michael.roth@amd.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Min Xu <min.m.xu@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Erdem Aktas <erdemaktas@google.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Acked-by: Ray Ni <ray.ni@Intel.com>
Signed-off-by: Brijesh Singh <brijesh.singh@amd.com>
Diffstat (limited to 'UefiCpuPkg/Library/MpInitLib/MpLib.c')
| -rw-r--r-- | UefiCpuPkg/Library/MpInitLib/MpLib.c | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpInitLib/MpLib.c index 64fddb497e..44a011ba75 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c @@ -896,8 +896,9 @@ FillExchangeInfoData ( ExchangeInfo->Enable5LevelPaging = (BOOLEAN)(Cr4.Bits.LA57 == 1);
DEBUG ((DEBUG_INFO, "%a: 5-Level Paging = %d\n", gEfiCallerBaseName, ExchangeInfo->Enable5LevelPaging));
- ExchangeInfo->SevEsIsEnabled = CpuMpData->SevEsIsEnabled;
- ExchangeInfo->GhcbBase = (UINTN)CpuMpData->GhcbBase;
+ ExchangeInfo->SevEsIsEnabled = CpuMpData->SevEsIsEnabled;
+ ExchangeInfo->SevSnpIsEnabled = CpuMpData->SevSnpIsEnabled;
+ ExchangeInfo->GhcbBase = (UINTN)CpuMpData->GhcbBase;
//
// Get the BSP's data of GDT and IDT
@@ -1847,9 +1848,10 @@ MpInitLibInitialize ( CpuMpData->CpuData = (CPU_AP_DATA *)(CpuMpData + 1);
CpuMpData->CpuInfoInHob = (UINT64)(UINTN)(CpuMpData->CpuData + MaxLogicalProcessorNumber);
InitializeSpinLock (&CpuMpData->MpLock);
- CpuMpData->SevEsIsEnabled = ConfidentialComputingGuestHas (CCAttrAmdSevEs);
- CpuMpData->SevEsAPBuffer = (UINTN)-1;
- CpuMpData->GhcbBase = PcdGet64 (PcdGhcbBase);
+ CpuMpData->SevEsIsEnabled = ConfidentialComputingGuestHas (CCAttrAmdSevEs);
+ CpuMpData->SevSnpIsEnabled = ConfidentialComputingGuestHas (CCAttrAmdSevSnp);
+ CpuMpData->SevEsAPBuffer = (UINTN)-1;
+ CpuMpData->GhcbBase = PcdGet64 (PcdGhcbBase);
//
// Make sure no memory usage outside of the allocated buffer.
|