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authorNi, Ray <ray.ni@intel.com>2019-08-01 17:58:24 +0800
committerEric Dong <eric.dong@intel.com>2019-08-09 08:52:08 +0800
commit09f69a877b1b499ff4b6bd6450dc531a19d7ed72 (patch)
tree402b3452df4065df3b765412c9fdabd07a6079a8 /UefiCpuPkg/Library/MpInitLib/MpLib.h
parent1ab7d72651bb254fa9bcb20fd3da2685fc142ea1 (diff)
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UefiCpuPkg/MpInitLib: Enable 5-level paging for AP when BSP's enabled
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2008 MpInitLib is the library that's responsible to wake up APs to provide MP PPI and Protocol services. The patch synchronizes BSP's CR4.LA57 to each AP's CR4.LA57. Without this change, AP may enter to GP fault when BSP's 5-level page table is set to AP during AP wakes up. Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Eric Dong <eric.dong@intel.com>
Diffstat (limited to 'UefiCpuPkg/Library/MpInitLib/MpLib.h')
-rw-r--r--UefiCpuPkg/Library/MpInitLib/MpLib.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.h b/UefiCpuPkg/Library/MpInitLib/MpLib.h
index effa235778..4b12f91d47 100644
--- a/UefiCpuPkg/Library/MpInitLib/MpLib.h
+++ b/UefiCpuPkg/Library/MpInitLib/MpLib.h
@@ -185,6 +185,10 @@ typedef struct {
UINT16 ModeTransitionSegment;
UINT32 ModeHighMemory;
UINT16 ModeHighSegment;
+ //
+ // Enable5LevelPaging indicates whether 5-level paging is enabled in long mode.
+ //
+ BOOLEAN Enable5LevelPaging;
} MP_CPU_EXCHANGE_INFO;
#pragma pack()