UefiCpuPkg: Remove X86 ASM and S files

NASM has replaced ASM and S files.
1. Remove ASM from all modules expect for the ones in ResetVector directory.
The ones in ResetVector directory are included by Vtf0.nasmb. They are
also nasm style.
2. Remove S files from the drivers only.
3. https://bugzilla.tianocore.org/show_bug.cgi?id=881
After NASM is updated, S files can be removed from Library.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>

5 files changed, 1 insertions, 924 deletions

diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm
deleted file mode 100644
index 91dc1eb3d3..0000000000
--- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm
+++ /dev/null
@@ -1,285 +0,0 @@
-;------------------------------------------------------------------------------ ;

-; Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>

-; This program and the accompanying materials

-; are licensed and made available under the terms and conditions of the BSD License

-; which accompanies this distribution.  The full text of the license may be found at

-; http://opensource.org/licenses/bsd-license.php.

-;

-; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

-; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

-;

-; Module Name:

-;

-;   SmiEntry.asm

-;

-; Abstract:

-;

-;   Code template of the SMI handler for a particular processor

-;

-;-------------------------------------------------------------------------------

-

-    .686p

-    .model  flat,C

-    .xmm

-

-MSR_IA32_MISC_ENABLE  EQU     1A0h

-MSR_EFER      EQU     0c0000080h

-MSR_EFER_XD   EQU     0800h

-

-;

-; Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR

-;

-DSC_OFFSET    EQU     0fb00h

-DSC_GDTPTR    EQU     48h

-DSC_GDTSIZ    EQU     50h

-DSC_CS        EQU     14h

-DSC_DS        EQU     16h

-DSC_SS        EQU     18h

-DSC_OTHERSEG  EQU     1Ah

-

-PROTECT_MODE_CS EQU   08h

-PROTECT_MODE_DS EQU   20h

-TSS_SEGMENT     EQU   40h

-

-SmiRendezvous      PROTO   C

-CpuSmmDebugEntry   PROTO   C

-CpuSmmDebugExit    PROTO   C

-

-EXTERNDEF   gcStmSmiHandlerTemplate:BYTE

-EXTERNDEF   gcStmSmiHandlerSize:WORD

-EXTERNDEF   gcStmSmiHandlerOffset:WORD

-EXTERNDEF   gStmSmiCr3:DWORD

-EXTERNDEF   gStmSmiStack:DWORD

-EXTERNDEF   gStmSmbase:DWORD

-EXTERNDEF   gStmXdSupported:BYTE

-EXTERNDEF   FeaturePcdGet (PcdCpuSmmStackGuard):BYTE

-EXTERNDEF   gStmSmiHandlerIdtr:FWORD

-

-    .code

-

-gcStmSmiHandlerTemplate    LABEL   BYTE

-

-_StmSmiEntryPoint:

-    DB      0bbh                        ; mov bx, imm16

-    DW      offset _StmGdtDesc - _StmSmiEntryPoint + 8000h

-    DB      2eh, 0a1h                   ; mov ax, cs:[offset16]

-    DW      DSC_OFFSET + DSC_GDTSIZ

-    dec     eax

-    mov     cs:[edi], eax               ; mov cs:[bx], ax

-    DB      66h, 2eh, 0a1h              ; mov eax, cs:[offset16]

-    DW      DSC_OFFSET + DSC_GDTPTR

-    mov     cs:[edi + 2], ax            ; mov cs:[bx + 2], eax

-    mov     bp, ax                      ; ebp = GDT base

-    DB      66h

-    lgdt    fword ptr cs:[edi]          ; lgdt fword ptr cs:[bx]

-; Patch ProtectedMode Segment

-    DB      0b8h                        ; mov ax, imm16

-    DW      PROTECT_MODE_CS             ; set AX for segment directly

-    mov     cs:[edi - 2], eax           ; mov cs:[bx - 2], ax

-; Patch ProtectedMode entry

-    DB      66h, 0bfh                   ; mov edi, SMBASE

-gStmSmbase    DD    ?

-    DB      67h

-    lea     ax, [edi + (@32bit - _StmSmiEntryPoint) + 8000h]

-    mov     cs:[edi - 6], ax            ; mov cs:[bx - 6], eax

-    mov     ebx, cr0

-    DB      66h

-    and     ebx, 9ffafff3h

-    DB      66h

-    or      ebx, 23h

-    mov     cr0, ebx

-    DB      66h, 0eah

-    DD      ?

-    DW      ?

-_StmGdtDesc    FWORD   ?

-

-@32bit:

-    mov     ax, PROTECT_MODE_DS

-    mov     ds, ax

-    mov     es, ax

-    mov     fs, ax

-    mov     gs, ax

-    mov     ss, ax

-    DB      0bch                   ; mov esp, imm32

-gStmSmiStack   DD      ?

-    mov     eax, offset gStmSmiHandlerIdtr

-    lidt    fword ptr [eax]

-    jmp     ProtFlatMode

-

-ProtFlatMode:

-    DB      0b8h                        ; mov eax, imm32

-gStmSmiCr3     DD      ?

-    mov     cr3, eax

-;

-; Need to test for CR4 specific bit support

-;

-    mov     eax, 1

-    cpuid                               ; use CPUID to determine if specific CR4 bits are supported

-    xor     eax, eax                    ; Clear EAX

-    test    edx, BIT2                   ; Check for DE capabilities

-    jz      @f

-    or      eax, BIT3

-@@:

-    test    edx, BIT6                   ; Check for PAE capabilities

-    jz      @f

-    or      eax, BIT5

-@@:

-    test    edx, BIT7                   ; Check for MCE capabilities

-    jz      @f

-    or      eax, BIT6

-@@:

-    test    edx, BIT24                  ; Check for FXSR capabilities

-    jz      @f

-    or      eax, BIT9

-@@:

-    test    edx, BIT25                  ; Check for SSE capabilities

-    jz      @f

-    or      eax, BIT10

-@@:                                     ; as cr4.PGE is not set here, refresh cr3

-    mov     cr4, eax                    ; in PreModifyMtrrs() to flush TLB.

-

-    cmp     FeaturePcdGet (PcdCpuSmmStackGuard), 0

-    jz      @F

-; Load TSS

-    mov     byte ptr [ebp + TSS_SEGMENT + 5], 89h ; clear busy flag

-    mov     eax, TSS_SEGMENT

-    ltr     ax

-@@:

-

-; enable NXE if supported

-    DB      0b0h                        ; mov al, imm8

-gStmXdSupported     DB      1

-    cmp     al, 0

-    jz      @SkipXd

-;

-; Check XD disable bit

-;

-    mov     ecx, MSR_IA32_MISC_ENABLE

-    rdmsr

-    push    edx                        ; save MSR_IA32_MISC_ENABLE[63-32]

-    test    edx, BIT2                  ; MSR_IA32_MISC_ENABLE[34]

-    jz      @f

-    and     dx, 0FFFBh                 ; clear XD Disable bit if it is set

-    wrmsr

-@@:

-    mov     ecx, MSR_EFER

-    rdmsr

-    or      ax, MSR_EFER_XD             ; enable NXE

-    wrmsr

-    jmp     @XdDone

-@SkipXd:

-    sub     esp, 4

-@XdDone:

-

-    mov     ebx, cr0

-    or      ebx, 080010023h             ; enable paging + WP + NE + MP + PE

-    mov     cr0, ebx

-    lea     ebx, [edi + DSC_OFFSET]

-    mov     ax, [ebx + DSC_DS]

-    mov     ds, eax

-    mov     ax, [ebx + DSC_OTHERSEG]

-    mov     es, eax

-    mov     fs, eax

-    mov     gs, eax

-    mov     ax, [ebx + DSC_SS]

-    mov     ss, eax

-

-CommonHandler:

-    mov     ebx, [esp + 4]                  ; CPU Index

-    push    ebx

-    mov     eax, CpuSmmDebugEntry

-    call    eax

-    add     esp, 4

-

-    push    ebx

-    mov     eax, SmiRendezvous

-    call    eax

-    add     esp, 4

-

-    push    ebx

-    mov     eax, CpuSmmDebugExit

-    call    eax

-    add     esp, 4

-

-    mov     eax, offset gStmXdSupported

-    mov     al, [eax]

-    cmp     al, 0

-    jz      @f

-    pop     edx                       ; get saved MSR_IA32_MISC_ENABLE[63-32]

-    test    edx, BIT2

-    jz      @f

-    mov     ecx, MSR_IA32_MISC_ENABLE

-    rdmsr

-    or      dx, BIT2                  ; set XD Disable bit if it was set before entering into SMM

-    wrmsr

-

-@@:

-    rsm

-

-_StmSmiHandler:

-;

-; Check XD disable bit

-;

-    xor     esi, esi

-    mov     eax, offset gStmXdSupported

-    mov     al, [eax]

-    cmp     al, 0

-    jz      @StmXdDone

-    mov     ecx, MSR_IA32_MISC_ENABLE

-    rdmsr

-    mov     esi, edx                   ; save MSR_IA32_MISC_ENABLE[63-32]

-    test    edx, BIT2                  ; MSR_IA32_MISC_ENABLE[34]

-    jz      @f

-    and     dx, 0FFFBh                 ; clear XD Disable bit if it is set

-    wrmsr

-@@:

-    mov     ecx, MSR_EFER

-    rdmsr

-    or      ax, MSR_EFER_XD             ; enable NXE

-    wrmsr

-@StmXdDone:

-    push    esi

-

-    ; below step is needed, because STM does not run above code.

-    ; we have to run below code to set IDT/CR0/CR4

-    mov     eax, offset gStmSmiHandlerIdtr

-    lidt    fword ptr [eax]

-

-

-    mov     eax, cr0

-    or      eax, 80010023h              ; enable paging + WP + NE + MP + PE

-    mov     cr0, eax

-;

-; Need to test for CR4 specific bit support

-;

-    mov     eax, 1

-    cpuid                               ; use CPUID to determine if specific CR4 bits are supported

-    mov     eax, cr4                    ; init EAX

-    test    edx, BIT2                   ; Check for DE capabilities

-    jz      @f

-    or      eax, BIT3

-@@:

-    test    edx, BIT6                   ; Check for PAE capabilities

-    jz      @f

-    or      eax, BIT5

-@@:

-    test    edx, BIT7                   ; Check for MCE capabilities

-    jz      @f

-    or      eax, BIT6

-@@:

-    test    edx, BIT24                  ; Check for FXSR capabilities

-    jz      @f

-    or      eax, BIT9

-@@:

-    test    edx, BIT25                  ; Check for SSE capabilities

-    jz      @f

-    or      eax, BIT10

-@@:                                     ; as cr4.PGE is not set here, refresh cr3

-    mov     cr4, eax                    ; in PreModifyMtrrs() to flush TLB.

-    ; STM init finish

-    jmp     CommonHandler

-

-gcStmSmiHandlerSize    DW      $ - _StmSmiEntryPoint

-gcStmSmiHandlerOffset  DW      _StmSmiHandler - _StmSmiEntryPoint

-

-    END

diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiException.asm b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiException.asm
deleted file mode 100644
index d0ae14713c..0000000000
--- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiException.asm
+++ /dev/null
@@ -1,175 +0,0 @@
-;------------------------------------------------------------------------------ ;

-; Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>

-; This program and the accompanying materials

-; are licensed and made available under the terms and conditions of the BSD License

-; which accompanies this distribution.  The full text of the license may be found at

-; http://opensource.org/licenses/bsd-license.php.

-;

-; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

-; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

-;

-; Module Name:

-;

-;   SmiException.asm

-;

-; Abstract:

-;

-;   Exception handlers used in SM mode

-;

-;-------------------------------------------------------------------------------

-

-    .686p

-    .model  flat,C

-

-EXTERNDEF   gcStmPsd:BYTE

-

-EXTERNDEF   SmmStmExceptionHandler:PROC

-EXTERNDEF   SmmStmSetup:PROC

-EXTERNDEF   SmmStmTeardown:PROC

-EXTERNDEF   gStmXdSupported:BYTE

-

-CODE_SEL    = 08h

-DATA_SEL    = 20h

-TSS_SEL     = 40h

-

-MSR_IA32_MISC_ENABLE  EQU     1A0h

-MSR_EFER              EQU     0c0000080h

-MSR_EFER_XD           EQU     0800h

-

-    .data

-

-gcStmPsd     LABEL   BYTE

-            DB      'TXTPSSIG'

-            DW      PSD_SIZE

-            DW      1              ; Version

-            DD      0              ; LocalApicId

-            DB      05h            ; Cr4Pse;Cr4Pae;Intel64Mode;ExecutionDisableOutsideSmrr

-            DB      0              ; BIOS to STM

-            DB      0              ; STM to BIOS

-            DB      0

-            DW      CODE_SEL

-            DW      DATA_SEL

-            DW      DATA_SEL

-            DW      DATA_SEL

-            DW      TSS_SEL

-            DW      0

-            DQ      0              ; SmmCr3

-            DQ      _OnStmSetup

-            DQ      _OnStmTeardown

-            DQ      0              ; SmmSmiHandlerRip - SMM guest entrypoint

-            DQ      0              ; SmmSmiHandlerRsp

-            DQ      0

-            DD      0

-            DD      80010100h      ; RequiredStmSmmRevId

-            DQ      _OnException

-            DQ      0              ; ExceptionStack

-            DW      DATA_SEL

-            DW      01Fh           ; ExceptionFilter

-            DD      0

-            DQ      0

-            DQ      0              ; BiosHwResourceRequirementsPtr

-            DQ      0              ; AcpiRsdp

-            DB      0              ; PhysicalAddressBits

-PSD_SIZE  = $ - offset gcStmPsd

-

-    .code

-;------------------------------------------------------------------------------

-; SMM Exception handlers

-;------------------------------------------------------------------------------

-_OnException       PROC

-    mov  ecx, esp

-    push ecx

-    call SmmStmExceptionHandler

-    add  esp, 4

-

-    mov  ebx, eax

-    mov  eax, 4

-    DB  0fh, 01h, 0c1h ; VMCALL

-    jmp $

-_OnException       ENDP

-

-_OnStmSetup PROC

-;

-; Check XD disable bit

-;

-    xor     esi, esi

-    mov     eax, offset gStmXdSupported

-    mov     al, [eax]

-    cmp     al, 0

-    jz      @StmXdDone1

-    mov     ecx, MSR_IA32_MISC_ENABLE

-    rdmsr

-    mov     esi, edx                   ; save MSR_IA32_MISC_ENABLE[63-32]

-    test    edx, BIT2                  ; MSR_IA32_MISC_ENABLE[34]

-    jz      @f

-    and     dx, 0FFFBh                 ; clear XD Disable bit if it is set

-    wrmsr

-@@:

-    mov     ecx, MSR_EFER

-    rdmsr

-    or      ax, MSR_EFER_XD             ; enable NXE

-    wrmsr

-@StmXdDone1:

-    push    esi

-

-  call SmmStmSetup

-

-    mov     eax, offset gStmXdSupported

-    mov     al, [eax]

-    cmp     al, 0

-    jz      @f

-    pop     edx                       ; get saved MSR_IA32_MISC_ENABLE[63-32]

-    test    edx, BIT2

-    jz      @f

-    mov     ecx, MSR_IA32_MISC_ENABLE

-    rdmsr

-    or      dx, BIT2                  ; set XD Disable bit if it was set before entering into SMM

-    wrmsr

-@@:

-

-  rsm

-_OnStmSetup ENDP

-

-_OnStmTeardown PROC

-;

-; Check XD disable bit

-;

-    xor     esi, esi

-    mov     eax, offset gStmXdSupported

-    mov     al, [eax]

-    cmp     al, 0

-    jz      @StmXdDone2

-    mov     ecx, MSR_IA32_MISC_ENABLE

-    rdmsr

-    mov     esi, edx                   ; save MSR_IA32_MISC_ENABLE[63-32]

-    test    edx, BIT2                  ; MSR_IA32_MISC_ENABLE[34]

-    jz      @f

-    and     dx, 0FFFBh                 ; clear XD Disable bit if it is set

-    wrmsr

-@@:

-    mov     ecx, MSR_EFER

-    rdmsr

-    or      ax, MSR_EFER_XD             ; enable NXE

-    wrmsr

-@StmXdDone2:

-    push    esi

-

-  call SmmStmTeardown

-

-    mov     eax, offset gStmXdSupported

-    mov     al, [eax]

-    cmp     al, 0

-    jz      @f

-    pop     edx                       ; get saved MSR_IA32_MISC_ENABLE[63-32]

-    test    edx, BIT2

-    jz      @f

-    mov     ecx, MSR_IA32_MISC_ENABLE

-    rdmsr

-    or      dx, BIT2                  ; set XD Disable bit if it was set before entering into SMM

-    wrmsr

-@@:

-

-  rsm

-_OnStmTeardown ENDP

-

-    END

diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf
index db8dcdcff4..c700644427 100644
--- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf
@@ -2,7 +2,7 @@
 #  The CPU specific programming for PiSmmCpuDxeSmm module when STM support

 #  is included.

 #

-#  Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>

+#  Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>

 #  This program and the accompanying materials

 #  are licensed and made available under the terms and conditions of the BSD License

 #  which accompanies this distribution.  The full text of the license may be found at

@@ -31,8 +31,6 @@
 [Sources.Ia32]

   Ia32/SmmStmSupport.c

 

-  Ia32/SmiEntry.asm

-  Ia32/SmiException.asm

 

   Ia32/SmiEntry.nasm

   Ia32/SmiException.nasm

@@ -43,8 +41,6 @@
 [Sources.X64]

   X64/SmmStmSupport.c

 

-  X64/SmiEntry.asm

-  X64/SmiException.asm

 

   X64/SmiEntry.nasm

   X64/SmiException.nasm

diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.asm b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.asm
deleted file mode 100644
index ad51e07079..0000000000
--- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.asm
+++ /dev/null
@@ -1,281 +0,0 @@
-;------------------------------------------------------------------------------ ;

-; Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>

-; This program and the accompanying materials

-; are licensed and made available under the terms and conditions of the BSD License

-; which accompanies this distribution.  The full text of the license may be found at

-; http://opensource.org/licenses/bsd-license.php.

-;

-; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

-; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

-;

-; Module Name:

-;

-;   SmiEntry.asm

-;

-; Abstract:

-;

-;   Code template of the SMI handler for a particular processor

-;

-;-------------------------------------------------------------------------------

-

-;

-; Variables referenced by C code

-;

-EXTERNDEF   SmiRendezvous:PROC

-EXTERNDEF   CpuSmmDebugEntry:PROC

-EXTERNDEF   CpuSmmDebugExit:PROC

-EXTERNDEF   gcStmSmiHandlerTemplate:BYTE

-EXTERNDEF   gcStmSmiHandlerSize:WORD

-EXTERNDEF   gcStmSmiHandlerOffset:WORD

-EXTERNDEF   gStmSmiCr3:DWORD

-EXTERNDEF   gStmSmiStack:DWORD

-EXTERNDEF   gStmSmbase:DWORD

-EXTERNDEF   gStmXdSupported:BYTE

-EXTERNDEF   gStmSmiHandlerIdtr:FWORD

-

-MSR_IA32_MISC_ENABLE  EQU     1A0h

-MSR_EFER      EQU     0c0000080h

-MSR_EFER_XD   EQU     0800h

-

-;

-; Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR

-;

-DSC_OFFSET    EQU     0fb00h

-DSC_GDTPTR    EQU     48h

-DSC_GDTSIZ    EQU     50h

-DSC_CS        EQU     14h

-DSC_DS        EQU     16h

-DSC_SS        EQU     18h

-DSC_OTHERSEG  EQU     1ah

-;

-; Constants relating to CPU State Save Area

-;

-SSM_DR6         EQU     0ffd0h

-SSM_DR7         EQU     0ffc8h

-

-PROTECT_MODE_CS EQU     08h

-PROTECT_MODE_DS EQU     20h

-LONG_MODE_CS    EQU     38h

-TSS_SEGMENT     EQU     40h

-GDT_SIZE        EQU     50h

-

-    .code

-

-gcStmSmiHandlerTemplate    LABEL   BYTE

-

-_StmSmiEntryPoint:

-    ;

-    ; The encoding of BX in 16-bit addressing mode is the same as of RDI in 64-

-    ; bit addressing mode. And that coincidence has been used in the following

-    ; "64-bit like" 16-bit code. Be aware that once RDI is referenced as a

-    ; base address register, it is actually BX that is referenced.

-    ;

-    DB      0bbh                        ; mov bx, imm16

-    DW      offset _StmGdtDesc - _StmSmiEntryPoint + 8000h  ; bx = GdtDesc offset

-; fix GDT descriptor

-    DB      2eh, 0a1h                   ; mov ax, cs:[offset16]

-    DW      DSC_OFFSET + DSC_GDTSIZ

-    DB      48h                         ; dec ax

-    DB      2eh

-    mov     [rdi], eax                  ; mov cs:[bx], ax

-    DB      66h, 2eh, 0a1h              ; mov eax, cs:[offset16]

-    DW      DSC_OFFSET + DSC_GDTPTR

-    DB      2eh

-    mov     [rdi + 2], ax               ; mov cs:[bx + 2], eax

-    DB      66h, 2eh

-    lgdt    fword ptr [rdi]             ; lgdt fword ptr cs:[bx]

-; Patch ProtectedMode Segment

-    DB      0b8h                        ; mov ax, imm16

-    DW      PROTECT_MODE_CS             ; set AX for segment directly

-    DB      2eh

-    mov     [rdi - 2], eax              ; mov cs:[bx - 2], ax

-; Patch ProtectedMode entry

-    DB      66h, 0bfh                   ; mov edi, SMBASE

-gStmSmbase    DD    ?

-    lea     ax, [edi + (@ProtectedMode - _StmSmiEntryPoint) + 8000h]

-    DB      2eh

-    mov     [rdi - 6], ax               ; mov cs:[bx - 6], eax

-; Switch into @ProtectedMode

-    mov     rbx, cr0

-    DB      66h

-    and     ebx, 9ffafff3h

-    DB      66h

-    or      ebx, 00000023h

-

-    mov     cr0, rbx

-    DB      66h, 0eah

-    DD      ?

-    DW      ?

-

-_StmGdtDesc    FWORD   ?

-@ProtectedMode:

-    mov     ax, PROTECT_MODE_DS

-    mov     ds, ax

-    mov     es, ax

-    mov     fs, ax

-    mov     gs, ax

-    mov     ss, ax

-    DB      0bch                   ; mov esp, imm32

-gStmSmiStack   DD      ?

-    jmp     ProtFlatMode

-

-ProtFlatMode:

-    DB      0b8h                        ; mov eax, offset gStmSmiCr3

-gStmSmiCr3     DD      ?

-    mov     cr3, rax

-    mov     eax, 668h                   ; as cr4.PGE is not set here, refresh cr3

-    mov     cr4, rax                    ; in PreModifyMtrrs() to flush TLB.

-; Load TSS

-    sub     esp, 8                      ; reserve room in stack

-    sgdt    fword ptr [rsp]

-    mov     eax, [rsp + 2]              ; eax = GDT base

-    add     esp, 8

-    mov     dl, 89h

-    mov     [rax + TSS_SEGMENT + 5], dl ; clear busy flag

-    mov     eax, TSS_SEGMENT

-    ltr     ax

-

-; enable NXE if supported

-    DB      0b0h                        ; mov al, imm8

-gStmXdSupported     DB      1

-    cmp     al, 0

-    jz      @SkipXd

-;

-; Check XD disable bit

-;

-    mov     ecx, MSR_IA32_MISC_ENABLE

-    rdmsr

-    sub     esp, 4

-    push    rdx                        ; save MSR_IA32_MISC_ENABLE[63-32]

-    test    edx, BIT2                  ; MSR_IA32_MISC_ENABLE[34]

-    jz      @f

-    and     dx, 0FFFBh                 ; clear XD Disable bit if it is set

-    wrmsr

-@@:

-    mov     ecx, MSR_EFER

-    rdmsr

-    or      ax, MSR_EFER_XD            ; enable NXE

-    wrmsr

-    jmp     @XdDone

-@SkipXd:

-    sub     esp, 8

-@XdDone:

-

-; Switch into @LongMode

-    push    LONG_MODE_CS                ; push cs hardcore here

-    call    Base                       ; push return address for retf later

-Base:

-    add     dword ptr [rsp], @LongMode - Base; offset for far retf, seg is the 1st arg

-

-    mov     ecx, MSR_EFER

-    rdmsr

-    or      ah, 1                      ; enable LME

-    wrmsr

-    mov     rbx, cr0

-    or      ebx, 080010023h            ; enable paging + WP + NE + MP + PE

-    mov     cr0, rbx

-    retf

-@LongMode:                              ; long mode (64-bit code) starts here

-    mov     rax, offset gStmSmiHandlerIdtr

-    lidt    fword ptr [rax]

-    lea     ebx, [rdi + DSC_OFFSET]

-    mov     ax, [rbx + DSC_DS]

-    mov     ds, eax

-    mov     ax, [rbx + DSC_OTHERSEG]

-    mov     es, eax

-    mov     fs, eax

-    mov     gs, eax

-    mov     ax, [rbx + DSC_SS]

-    mov     ss, eax

-

-CommonHandler:

-    mov     rbx, [rsp + 0x08]           ; rbx <- CpuIndex

-

-    ;

-    ; Save FP registers

-    ;

-    sub     rsp, 200h

-    DB      48h                         ; FXSAVE64

-    fxsave  [rsp]

-

-    add     rsp, -20h

-

-    mov     rcx, rbx

-    mov     rax, CpuSmmDebugEntry

-    call    rax

-

-    mov     rcx, rbx

-    mov     rax, SmiRendezvous          ; rax <- absolute addr of SmiRedezvous

-    call    rax

-

-    mov     rcx, rbx

-    mov     rax, CpuSmmDebugExit

-    call    rax

-

-    add     rsp, 20h

-

-    ;

-    ; Restore FP registers

-    ;

-    DB      48h                         ; FXRSTOR64

-    fxrstor [rsp]

-

-    add     rsp, 200h

-

-    mov     rax, offset ASM_PFX(gStmXdSupported)

-    mov     al, [rax]

-    cmp     al, 0

-    jz      @f

-    pop     rdx                       ; get saved MSR_IA32_MISC_ENABLE[63-32]

-    test    edx, BIT2

-    jz      @f

-    mov     ecx, MSR_IA32_MISC_ENABLE

-    rdmsr

-    or      dx, BIT2                  ; set XD Disable bit if it was set before entering into SMM

-    wrmsr

-

-@@:

-    rsm

-

-_StmSmiHandler:

-;

-; Check XD disable bit

-;

-    xor     r8, r8

-    mov     rax, offset ASM_PFX(gStmXdSupported)

-    mov     al, [rax]

-    cmp     al, 0

-    jz      @StmXdDone

-    mov     ecx, MSR_IA32_MISC_ENABLE

-    rdmsr

-    mov     r8, rdx                   ; save MSR_IA32_MISC_ENABLE[63-32]

-    test    edx, BIT2                  ; MSR_IA32_MISC_ENABLE[34]

-    jz      @f

-    and     dx, 0FFFBh                 ; clear XD Disable bit if it is set

-    wrmsr

-@@:

-    mov     ecx, MSR_EFER

-    rdmsr

-    or      ax, MSR_EFER_XD            ; enable NXE

-    wrmsr

-@StmXdDone:

-    push    r8

-

-    ; below step is needed, because STM does not run above code.

-    ; we have to run below code to set IDT/CR0/CR4

-    mov     rax, offset gStmSmiHandlerIdtr

-    lidt    fword ptr [rax]

-

-    mov     rax, cr0

-    or      eax, 80010023h              ; enable paging + WP + NE + MP + PE

-    mov     cr0, rax

-    mov     rax, cr4

-    mov     eax, 668h                   ; as cr4.PGE is not set here, refresh cr3

-    mov     cr4, rax                    ; in PreModifyMtrrs() to flush TLB.

-    ; STM init finish

-    jmp     CommonHandler

-

-gcStmSmiHandlerSize    DW      $ - _StmSmiEntryPoint

-gcStmSmiHandlerOffset  DW      _StmSmiHandler - _StmSmiEntryPoint

-

-    END

diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiException.asm b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiException.asm
deleted file mode 100644
index 33e9860160..0000000000
--- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiException.asm
+++ /dev/null
@@ -1,178 +0,0 @@
-;------------------------------------------------------------------------------ ;

-; Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>

-; This program and the accompanying materials

-; are licensed and made available under the terms and conditions of the BSD License

-; which accompanies this distribution.  The full text of the license may be found at

-; http://opensource.org/licenses/bsd-license.php.

-;

-; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

-; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

-;

-; Module Name:

-;

-;   SmiException.asm

-;

-; Abstract:

-;

-;   Exception handlers used in SM mode

-;

-;-------------------------------------------------------------------------------

-

-EXTERNDEF   gcStmPsd:BYTE

-

-EXTERNDEF   SmmStmExceptionHandler:PROC

-EXTERNDEF   SmmStmSetup:PROC

-EXTERNDEF   SmmStmTeardown:PROC

-EXTERNDEF   gStmXdSupported:BYTE

-

-CODE_SEL    EQU 38h

-DATA_SEL    EQU 20h

-TR_SEL      EQU 40h

-

-MSR_IA32_MISC_ENABLE  EQU     1A0h

-MSR_EFER              EQU     0c0000080h

-MSR_EFER_XD           EQU     0800h

-

-    .data

-

-;

-; This structure serves as a template for all processors.

-;

-gcStmPsd     LABEL   BYTE

-            DB      'TXTPSSIG'

-            DW      PSD_SIZE

-            DW      1              ; Version

-            DD      0              ; LocalApicId

-            DB      0Fh            ; Cr4Pse;Cr4Pae;Intel64Mode;ExecutionDisableOutsideSmrr

-            DB      0              ; BIOS to STM

-            DB      0              ; STM to BIOS

-            DB      0

-            DW      CODE_SEL

-            DW      DATA_SEL

-            DW      DATA_SEL

-            DW      DATA_SEL

-            DW      TR_SEL

-            DW      0

-            DQ      0              ; SmmCr3

-            DQ      _OnStmSetup

-            DQ      _OnStmTeardown

-            DQ      0              ; SmmSmiHandlerRip - SMM guest entrypoint

-            DQ      0              ; SmmSmiHandlerRsp

-            DQ      0

-            DD      0

-            DD      80010100h      ; RequiredStmSmmRevId

-            DQ      _OnException

-            DQ      0              ; ExceptionStack

-            DW      DATA_SEL

-            DW      01Fh           ; ExceptionFilter

-            DD      0

-            DQ      0

-            DQ      0              ; BiosHwResourceRequirementsPtr

-            DQ      0              ; AcpiRsdp

-            DB      0              ; PhysicalAddressBits

-PSD_SIZE  = $ - offset gcStmPsd

-

-    .code

-;------------------------------------------------------------------------------

-; SMM Exception handlers

-;------------------------------------------------------------------------------

-_OnException       PROC

-    mov  rcx, rsp

-    add  rsp, -28h

-    call SmmStmExceptionHandler

-    add  rsp, 28h

-    mov  ebx, eax

-    mov  eax, 4

-    DB  0fh, 01h, 0c1h ; VMCALL

-    jmp $

-_OnException       ENDP

-

-_OnStmSetup PROC

-;

-; Check XD disable bit

-;

-    xor     r8, r8

-    mov     rax, offset ASM_PFX(gStmXdSupported)

-    mov     al, [rax]

-    cmp     al, 0

-    jz      @StmXdDone1

-    mov     ecx, MSR_IA32_MISC_ENABLE

-    rdmsr

-    mov     r8, rdx                   ; save MSR_IA32_MISC_ENABLE[63-32]

-    test    edx, BIT2                  ; MSR_IA32_MISC_ENABLE[34]

-    jz      @f

-    and     dx, 0FFFBh                 ; clear XD Disable bit if it is set

-    wrmsr

-@@:

-    mov     ecx, MSR_EFER

-    rdmsr

-    or      ax, MSR_EFER_XD            ; enable NXE

-    wrmsr

-@StmXdDone1:

-    push    r8

-

-  add  rsp, -20h

-  call SmmStmSetup

-  add  rsp, 20h

-

-    mov     rax, offset ASM_PFX(gStmXdSupported)

-    mov     al, [rax]

-    cmp     al, 0

-    jz      @f

-    pop     rdx                       ; get saved MSR_IA32_MISC_ENABLE[63-32]

-    test    edx, BIT2

-    jz      @f

-    mov     ecx, MSR_IA32_MISC_ENABLE

-    rdmsr

-    or      dx, BIT2                  ; set XD Disable bit if it was set before entering into SMM

-    wrmsr

-@@:

-

-  rsm

-_OnStmSetup ENDP

-

-_OnStmTeardown PROC

-;

-; Check XD disable bit

-;

-    xor     r8, r8

-    mov     rax, offset ASM_PFX(gStmXdSupported)

-    mov     al, [rax]

-    cmp     al, 0

-    jz      @StmXdDone2

-    mov     ecx, MSR_IA32_MISC_ENABLE

-    rdmsr

-    mov     r8, rdx                   ; save MSR_IA32_MISC_ENABLE[63-32]

-    test    edx, BIT2                  ; MSR_IA32_MISC_ENABLE[34]

-    jz      @f

-    and     dx, 0FFFBh                 ; clear XD Disable bit if it is set

-    wrmsr

-@@:

-    mov     ecx, MSR_EFER

-    rdmsr

-    or      ax, MSR_EFER_XD            ; enable NXE

-    wrmsr

-@StmXdDone2:

-    push    r8

-

-  add  rsp, -20h

-  call SmmStmTeardown

-  add  rsp, 20h

-

-    mov     rax, offset ASM_PFX(gStmXdSupported)

-    mov     al, [rax]

-    cmp     al, 0

-    jz      @f

-    pop     rdx                       ; get saved MSR_IA32_MISC_ENABLE[63-32]

-    test    edx, BIT2

-    jz      @f

-    mov     ecx, MSR_IA32_MISC_ENABLE

-    rdmsr

-    or      dx, BIT2                  ; set XD Disable bit if it was set before entering into SMM

-    wrmsr

-@@:

-

-  rsm

-_OnStmTeardown ENDP

-

-    END