diff options
| author | Jian J Wang <jian.j.wang@intel.com> | 2017-12-26 08:43:59 +0800 |
|---|---|---|
| committer | Star Zeng <star.zeng@intel.com> | 2017-12-26 09:44:14 +0800 |
| commit | 56649f43013703e95f54c293d708152b765cc49b (patch) | |
| tree | 9042472f664a940c368b68921de45b169f6f47f3 /UefiCpuPkg/Library | |
| parent | 5e2ee2f5f4def0482ce2f8687d6840ac38b4383f (diff) | |
| download | edk2-56649f43013703e95f54c293d708152b765cc49b.tar.gz edk2-56649f43013703e95f54c293d708152b765cc49b.tar.bz2 edk2-56649f43013703e95f54c293d708152b765cc49b.zip | |
UefiCpuPkg: Update code to use new structure field names
Due to coding style fix of the structure definition in BaseLib.h, all
code referencing those structure must be updated accordingly.
Cc: Dandan Bi <dandan.bi@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jian J Wang <jian.j.wang@intel.com>
Reviewed-by: Dandan Bi <dandan.bi@intel.com>
Diffstat (limited to 'UefiCpuPkg/Library')
3 files changed, 16 insertions, 16 deletions
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c index 6ac8549839..4e89b0470f 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c @@ -216,7 +216,7 @@ ArchSetupExcpetionStack ( TssDesc->Bits.BaseLow = (UINT16)TssBase;
TssDesc->Bits.BaseMid = (UINT8)(TssBase >> 16);
TssDesc->Bits.Type = IA32_GDT_TYPE_TSS;
- TssDesc->Bits.P = 1;
+ TssDesc->Bits.Present = 1;
TssDesc->Bits.LimitHigh = 0;
TssDesc->Bits.BaseHigh = (UINT8)(TssBase >> 24);
@@ -240,7 +240,7 @@ ArchSetupExcpetionStack ( TssDesc->Bits.BaseLow = (UINT16)TssBase;
TssDesc->Bits.BaseMid = (UINT8)(TssBase >> 16);
TssDesc->Bits.Type = IA32_GDT_TYPE_TSS;
- TssDesc->Bits.P = 1;
+ TssDesc->Bits.Present = 1;
TssDesc->Bits.LimitHigh = 0;
TssDesc->Bits.BaseHigh = (UINT8)(TssBase >> 24);
@@ -253,17 +253,17 @@ ArchSetupExcpetionStack ( continue;
}
- Tss->EIP = (UINT32)(TemplateMap.ExceptionStart
+ Tss->Eip = (UINT32)(TemplateMap.ExceptionStart
+ Vector * TemplateMap.ExceptionStubHeaderSize);
- Tss->EFLAGS = 0x2;
- Tss->ESP = StackTop;
- Tss->CR3 = AsmReadCr3 ();
- Tss->ES = AsmReadEs ();
- Tss->CS = AsmReadCs ();
- Tss->SS = AsmReadSs ();
- Tss->DS = AsmReadDs ();
- Tss->FS = AsmReadFs ();
- Tss->GS = AsmReadGs ();
+ Tss->Eflags = 0x2;
+ Tss->Esp = StackTop;
+ Tss->Cr3 = AsmReadCr3 ();
+ Tss->Es = AsmReadEs ();
+ Tss->Cs = AsmReadCs ();
+ Tss->Ss = AsmReadSs ();
+ Tss->Ds = AsmReadDs ();
+ Tss->Fs = AsmReadFs ();
+ Tss->Gs = AsmReadGs ();
StackTop -= StackSwitchData->Ia32.KnownGoodStackSize;
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c index 1dcf4277de..4d52b4eb0e 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c @@ -186,7 +186,7 @@ ArchSetupExcpetionStack ( //
TssDesc = StackSwitchData->X64.ExceptionTssDesc;
Tss = StackSwitchData->X64.ExceptionTss;
- if (StackSwitchData->X64.StackSwitchExceptionNumber > ARRAY_SIZE (Tss->IST)) {
+ if (StackSwitchData->X64.StackSwitchExceptionNumber > ARRAY_SIZE (Tss->Ist)) {
return EFI_INVALID_PARAMETER;
}
@@ -221,7 +221,7 @@ ArchSetupExcpetionStack ( TssDesc->Bits.BaseLow = (UINT16)TssBase;
TssDesc->Bits.BaseMidl = (UINT8)(TssBase >> 16);
TssDesc->Bits.Type = IA32_GDT_TYPE_TSS;
- TssDesc->Bits.P = 1;
+ TssDesc->Bits.Present = 1;
TssDesc->Bits.LimitHigh = 0;
TssDesc->Bits.BaseMidh = (UINT8)(TssBase >> 24);
TssDesc->Bits.BaseHigh = (UINT32)(TssBase >> 32);
@@ -236,7 +236,7 @@ ArchSetupExcpetionStack ( //
// Fixup IST
//
- Tss->IST[Index] = StackTop;
+ Tss->Ist[Index] = StackTop;
StackTop -= StackSwitchData->X64.KnownGoodStackSize;
//
diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpInitLib/MpLib.c index 0c2058a7b0..da1a43c430 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c @@ -243,7 +243,7 @@ RestoreVolatileRegisters ( VolatileRegisters->Tr < VolatileRegisters->Gdtr.Limit) {
Tss = (IA32_TSS_DESCRIPTOR *)(VolatileRegisters->Gdtr.Base +
VolatileRegisters->Tr);
- if (Tss->Bits.P == 1) {
+ if (Tss->Bits.Present == 1) {
Tss->Bits.Type &= 0xD; // 1101 - Clear busy bit just in case
AsmWriteTr (VolatileRegisters->Tr);
}
|