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| author | Michael Kinney <michael.d.kinney@intel.com> | 2015-11-17 05:10:45 +0000 |
|---|---|---|
| committer | vanjeff <vanjeff@Edk2> | 2015-11-17 05:10:45 +0000 |
| commit | a8f7592e4e1ae1f80f6ee847a91c7012ea3073cc (patch) | |
| tree | d45a67ff6cc2a767319315549f9e23d22165c8c4 /UefiCpuPkg/Library | |
| parent | e5240a6e42757b8637c8c56589f3978c6d4a7e41 (diff) | |
| download | edk2-a8f7592e4e1ae1f80f6ee847a91c7012ea3073cc.tar.gz edk2-a8f7592e4e1ae1f80f6ee847a91c7012ea3073cc.tar.bz2 edk2-a8f7592e4e1ae1f80f6ee847a91c7012ea3073cc.zip | |
UefiCpuPkg: SmmCpuFeaturesLib: Add MSR_SMM_FEATURE_CONTROL support
Add support for the reading and writing MSR_SMM_FEATURE_CONTROL
through the SmmCpuFeaturesIsSmmRegisterSupported(),
SmmCpuFeaturesGetSmmRegister(), and SmmCpuFeaturesSetSmmRegister()
functions. This MSR is supported if the Family/Model is 06_3C,
06_45, or 06_46.
(Sync patch r18690 from main trunk.)
Cc: "Yao, Jiewen" <jiewen.yao@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: "Yao, Jiewen" <jiewen.yao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/branches/UDK2015@18846 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'UefiCpuPkg/Library')
| -rw-r--r-- | UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c index 4f2f9b65fa..0c1610d977 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c @@ -33,6 +33,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. #define SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSMASK 0x0A1
#define EFI_MSR_SMRR_MASK 0xFFFFF000
#define EFI_MSR_SMRR_PHYS_MASK_VALID BIT11
+#define SMM_FEATURES_LIB_SMM_FEATURE_CONTROL 0x4E0
//
// Set default value to assume SMRR is not supported
@@ -40,6 +41,11 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. BOOLEAN mSmrrSupported = FALSE;
//
+// Set default value to assume MSR_SMM_FEATURE_CONTROL is not supported
+//
+BOOLEAN mSmmFeatureControlSupported = FALSE;
+
+//
// Set default value to assume IA-32 Architectural MSRs are used
//
UINT32 mSmrrPhysBaseMsr = SMM_FEATURES_LIB_IA32_SMRR_PHYSBASE;
@@ -127,6 +133,20 @@ SmmCpuFeaturesLibConstructor ( //
// Intel(R) 64 and IA-32 Architectures Software Developer's Manual
+ // Volume 3C, Section 35.10.1 MSRs in 4th Generation Intel(R) Core(TM)
+ // Processor Family
+ //
+ // If CPU Family/Model is 06_3C, 06_45, or 06_46 then use 4th Generation
+ // Intel(R) Core(TM) Processor Family MSRs
+ //
+ if (FamilyId == 0x06) {
+ if (ModelId == 0x3C || ModelId == 0x45 || ModelId == 0x46) {
+ mSmmFeatureControlSupported = TRUE;
+ }
+ }
+
+ //
+ // Intel(R) 64 and IA-32 Architectures Software Developer's Manual
// Volume 3C, Section 34.4.2 SMRAM Caching
// An IA-32 processor does not automatically write back and invalidate its
// caches before entering SMM or before exiting SMM. Because of this behavior,
@@ -457,6 +477,9 @@ SmmCpuFeaturesIsSmmRegisterSupported ( IN SMM_REG_NAME RegName
)
{
+ if (mSmmFeatureControlSupported && RegName == SmmRegFeatureControl) {
+ return TRUE;
+ }
return FALSE;
}
@@ -479,6 +502,9 @@ SmmCpuFeaturesGetSmmRegister ( IN SMM_REG_NAME RegName
)
{
+ if (mSmmFeatureControlSupported && RegName == SmmRegFeatureControl) {
+ return AsmReadMsr64 (SMM_FEATURES_LIB_SMM_FEATURE_CONTROL);
+ }
return 0;
}
@@ -501,6 +527,9 @@ SmmCpuFeaturesSetSmmRegister ( IN UINT64 Value
)
{
+ if (mSmmFeatureControlSupported && RegName == SmmRegFeatureControl) {
+ AsmWriteMsr64 (SMM_FEATURES_LIB_SMM_FEATURE_CONTROL, Value);
+ }
}
/**
|