UefiCpuPkg/PiSmmCpuDxeSmm: Using global semaphores in aligned buffer

Update all global semaphores to the ones in allocated aligned
semaphores buffer.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>

1 files changed, 4 insertions, 6 deletions

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c
index 5d299044c4..a871bef4e2 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c
@@ -1,7 +1,7 @@
 /** @file

 Page table manipulation functions for IA-32 processors

 

-Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>

+Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>

 This program and the accompanying materials

 are licensed and made available under the terms and conditions of the BSD License

 which accompanies this distribution.  The full text of the license may be found at

@@ -14,8 +14,6 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 

 #include "PiSmmCpuDxeSmm.h"

 

-SPIN_LOCK                           mPFLock;

-

 /**

   Create PageTable for SMM use.

 

@@ -33,7 +31,7 @@ SmmInitPageTable (
   //

   // Initialize spin lock

   //

-  InitializeSpinLock (&mPFLock);

+  InitializeSpinLock (mPFLock);

 

   if (FeaturePcdGet (PcdCpuSmmProfileEnable)) {

     //

@@ -94,7 +92,7 @@ SmiPFHandler (
 

   ASSERT (InterruptType == EXCEPT_IA32_PAGE_FAULT);

 

-  AcquireSpinLock (&mPFLock);

+  AcquireSpinLock (mPFLock);

 

   PFAddress = AsmReadCr2 ();

 

@@ -128,5 +126,5 @@ SmiPFHandler (
     SmiDefaultPFHandler ();

   }

 

-  ReleaseSpinLock (&mPFLock);

+  ReleaseSpinLock (mPFLock);

 }