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| author | Leo Duran <leo.duran@amd.com> | 2017-02-27 01:43:06 +0800 |
|---|---|---|
| committer | Star Zeng <star.zeng@intel.com> | 2017-03-01 12:52:58 +0800 |
| commit | ab1a5a58c95937998f3ecf384a8940130511e234 (patch) | |
| tree | 2b1ed8154d0aedb8a230d68292c06c3646c2222b /UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | |
| parent | 787a085b0fb7553c8e530b74b350c32b0f81c779 (diff) | |
| download | edk2-ab1a5a58c95937998f3ecf384a8940130511e234.tar.gz edk2-ab1a5a58c95937998f3ecf384a8940130511e234.tar.bz2 edk2-ab1a5a58c95937998f3ecf384a8940130511e234.zip | |
MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe: Add support for PCD PcdPteMemoryEncryptionAddressOrMask
This PCD holds the address mask for page table entries when memory
encryption is enabled on AMD processors supporting the Secure Encrypted
Virtualization (SEV) feature.
This module updates the under-4GB page tables configured by the S3-Resume
code in UefiCpuPkg/Universal/Acpi/S3Resume2Pei. The mask is saved at module
start (ScriptExecute.c), and applied when tables are expanded on-demand by
page-faults above 4GB's (SetIdtEntry.c).
CC: Jeff Fan <jeff.fan@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Brijesh Singh <brijesh.singh@amd.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Leo Duran <leo.duran@amd.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
Diffstat (limited to 'UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c')
0 files changed, 0 insertions, 0 deletions