summaryrefslogtreecommitdiffstats
path: root/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
diff options
context:
space:
mode:
authorJeff Fan <jeff.fan@intel.com>2016-03-22 10:15:53 +0800
committerMichael Kinney <michael.d.kinney@intel.com>2016-05-24 15:20:01 -0700
commitfe3a75bc41545125f76c28238016658f48833ba2 (patch)
tree36d6c549bf2bb30b9fa9cb3cba443fcb531b62a1 /UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
parentd67b73cc381219f16f5d120e733efb7ffaa814f0 (diff)
downloadedk2-fe3a75bc41545125f76c28238016658f48833ba2.tar.gz
edk2-fe3a75bc41545125f76c28238016658f48833ba2.tar.bz2
edk2-fe3a75bc41545125f76c28238016658f48833ba2.zip
UefiCpuPkg/PiSmmCpuDxeSmm: Using global semaphores in aligned buffer
Update all global semaphores to the ones in allocated aligned semaphores buffer. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
Diffstat (limited to 'UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c')
-rw-r--r--UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c16
1 files changed, 8 insertions, 8 deletions
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
index 36a0650b2f..4ef535fb4e 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
@@ -1,7 +1,7 @@
/** @file
Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU.
-Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -104,7 +104,7 @@ BOOLEAN mSmmCodeAccessCheckEnable = FALSE;
//
// Spin lock used to serialize setting of SMM Code Access Check feature
//
-SPIN_LOCK mConfigSmmCodeAccessCheckLock;
+SPIN_LOCK *mConfigSmmCodeAccessCheckLock = NULL;
/**
Initialize IDT to setup exception handlers for SMM.
@@ -1338,7 +1338,7 @@ ConfigSmmCodeAccessCheckOnCurrentProcessor (
//
// Release the spin lock user to serialize the updates to the SMM Feature Control MSR
//
- ReleaseSpinLock (&mConfigSmmCodeAccessCheckLock);
+ ReleaseSpinLock (mConfigSmmCodeAccessCheckLock);
}
/**
@@ -1374,13 +1374,13 @@ ConfigSmmCodeAccessCheck (
//
// Initialize the lock used to serialize the MSR programming in BSP and all APs
//
- InitializeSpinLock (&mConfigSmmCodeAccessCheckLock);
+ InitializeSpinLock (mConfigSmmCodeAccessCheckLock);
//
// Acquire Config SMM Code Access Check spin lock. The BSP will release the
// spin lock when it is done executing ConfigSmmCodeAccessCheckOnCurrentProcessor().
//
- AcquireSpinLock (&mConfigSmmCodeAccessCheckLock);
+ AcquireSpinLock (mConfigSmmCodeAccessCheckLock);
//
// Enable SMM Code Access Check feature on the BSP.
@@ -1397,7 +1397,7 @@ ConfigSmmCodeAccessCheck (
// Acquire Config SMM Code Access Check spin lock. The AP will release the
// spin lock when it is done executing ConfigSmmCodeAccessCheckOnCurrentProcessor().
//
- AcquireSpinLock (&mConfigSmmCodeAccessCheckLock);
+ AcquireSpinLock (mConfigSmmCodeAccessCheckLock);
//
// Call SmmStartupThisAp() to enable SMM Code Access Check on an AP.
@@ -1408,14 +1408,14 @@ ConfigSmmCodeAccessCheck (
//
// Wait for the AP to release the Config SMM Code Access Check spin lock.
//
- while (!AcquireSpinLockOrFail (&mConfigSmmCodeAccessCheckLock)) {
+ while (!AcquireSpinLockOrFail (mConfigSmmCodeAccessCheckLock)) {
CpuPause ();
}
//
// Release the Config SMM Code Access Check spin lock.
//
- ReleaseSpinLock (&mConfigSmmCodeAccessCheckLock);
+ ReleaseSpinLock (mConfigSmmCodeAccessCheckLock);
}
}
}