UefiCpuPkg/PiSmmCpuDxeSmm: patch "gSmmCr4" with PatchInstructionX86()

Unlike "gSmmCr3" in the previous patch, "gSmmCr4" is not only used for
machine code patching, but also as a means to communicate the initial CR4
value from SmmRelocateBases() to InitSmmS3ResumeState(). In other words,
the last four bytes of the "mov eax, Cr4Value" instruction's binary
representation are utilized as normal data too.

In order to get rid of the DB for "mov eax, Cr4Value", we have to split
both roles, patching and data flow. Introduce the "mSmmCr4" global (SMRAM)
variable for the data flow purpose. Rename the "gSmmCr4" variable to
"gPatchSmmCr4" so that its association with PatchInstructionX86() is clear
from the declaration, change its type to X86_ASSEMBLY_PATCH_LABEL, and
patch it with PatchInstructionX86(), to the value now contained in
"mSmmCr4".

This lets us remove the binary (DB) encoding of "mov eax, Cr4Value" in
"SmmInit.nasm".

Cc: Eric Dong <eric.dong@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=866
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>

1 files changed, 7 insertions, 1 deletions

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
index c5b67e3dc0..a3fd796dba 100755
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
@@ -125,6 +125,11 @@ UINTN                    mSmmCpuSmramRangeCount;
 

 UINT8                    mPhysicalAddressBits;

 

+//

+// Control register contents saved for SMM S3 resume state initialization.

+//

+UINT32                   mSmmCr4;

+

 /**

   Initialize IDT to setup exception handlers for SMM.

 

@@ -407,7 +412,8 @@ SmmRelocateBases (
   //

   gSmmCr0 = (UINT32)AsmReadCr0 ();

   PatchInstructionX86 (gPatchSmmCr3, AsmReadCr3 (), 4);

-  gSmmCr4 = (UINT32)AsmReadCr4 ();

+  mSmmCr4 = (UINT32)AsmReadCr4 ();

+  PatchInstructionX86 (gPatchSmmCr4, mSmmCr4, 4);

 

   //

   // Patch GDTR for SMM base relocation