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| author | Dun Tan <dun.tan@intel.com> | 2022-08-09 15:58:28 +0800 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2022-08-15 05:15:43 +0000 |
| commit | 7b4754904efd5503d191f034ef17e982ceb65962 (patch) | |
| tree | 932b4689dd34fe0631447d189e0aa299950ec89c /UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | |
| parent | 83d5871184d1e09332565bfc939e5fc8354b5b79 (diff) | |
| download | edk2-7b4754904efd5503d191f034ef17e982ceb65962.tar.gz edk2-7b4754904efd5503d191f034ef17e982ceb65962.tar.bz2 edk2-7b4754904efd5503d191f034ef17e982ceb65962.zip | |
UefiCpuPkg/PiSmmCpuDxeSmm: Remove mInternalCr3 in PiSmmCpuDxeSmm
This patch is code refactoring and doesn't change any functionality.
Remove mInternalCr3 in PiSmmCpuDxe pagetable related code. In previous
code, mInternalCr3 is used to pass address of page table which is
different from Cr3 register in different level of SetMemoryAttributes
function. Now remove it and pass the page table base address from the
root function parameter to simplify the code logic.
Signed-off-by: Dun Tan <dun.tan@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Diffstat (limited to 'UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h')
| -rw-r--r-- | UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 26 |
1 files changed, 9 insertions, 17 deletions
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h index dfeceec2aa..ef8bf5947d 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h @@ -264,7 +264,7 @@ extern UINTN mMaxNumberOfCpus; extern UINTN mNumberOfCpus;
extern EFI_SMM_CPU_PROTOCOL mSmmCpu;
extern EFI_MM_MP_PROTOCOL mSmmMp;
-extern UINTN mInternalCr3;
+extern BOOLEAN m5LevelPagingNeeded;
///
/// The mode of the CPU at the time an SMI occurs
@@ -682,7 +682,6 @@ SmmBlockingStartupThisAp ( **/
EFI_STATUS
-EFIAPI
SmmSetMemoryAttributes (
IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length,
@@ -712,7 +711,6 @@ SmmSetMemoryAttributes ( **/
EFI_STATUS
-EFIAPI
SmmClearMemoryAttributes (
IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length,
@@ -958,21 +956,11 @@ SetPageTableAttributes ( );
/**
- Get page table base address and the depth of the page table.
-
- @param[out] Base Page table base address.
- @param[out] FiveLevels TRUE means 5 level paging. FALSE means 4 level paging.
-**/
-VOID
-GetPageTable (
- OUT UINTN *Base,
- OUT BOOLEAN *FiveLevels OPTIONAL
- );
-
-/**
This function sets the attributes for the memory region specified by BaseAddress and
Length from their current attributes to the attributes specified by Attributes.
+ @param[in] PageTableBase The page table base.
+ @param[in] EnablePML5Paging If PML5 paging is enabled.
@param[in] BaseAddress The physical address that is the start address of a memory region.
@param[in] Length The size in bytes of the memory region.
@param[in] Attributes The bit mask of attributes to set for the memory region.
@@ -993,8 +981,9 @@ GetPageTable ( **/
EFI_STATUS
-EFIAPI
SmmSetMemoryAttributesEx (
+ IN UINTN PageTableBase,
+ IN BOOLEAN EnablePML5Paging,
IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length,
IN UINT64 Attributes,
@@ -1005,6 +994,8 @@ SmmSetMemoryAttributesEx ( This function clears the attributes for the memory region specified by BaseAddress and
Length from their current attributes to the attributes specified by Attributes.
+ @param[in] PageTableBase The page table base.
+ @param[in] EnablePML5Paging If PML5 paging is enabled.
@param[in] BaseAddress The physical address that is the start address of a memory region.
@param[in] Length The size in bytes of the memory region.
@param[in] Attributes The bit mask of attributes to clear for the memory region.
@@ -1025,8 +1016,9 @@ SmmSetMemoryAttributesEx ( **/
EFI_STATUS
-EFIAPI
SmmClearMemoryAttributesEx (
+ IN UINTN PageTableBase,
+ IN BOOLEAN EnablePML5Paging,
IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length,
IN UINT64 Attributes,
|