summaryrefslogtreecommitdiffstats
path: root/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
diff options
context:
space:
mode:
authorDun Tan <dun.tan@intel.com>2023-05-15 15:47:54 +0800
committerRay Ni <ray.ni@intel.com>2023-06-30 11:07:40 +0530
commit701b5797b260cbc9477380beb7fb071f3c5c88d1 (patch)
treeb1c0fe99e3fd819136fb50c48fd0c4a35760ee4e /UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
parentd706d9c64ac6074f3066f0531b66f59f4991973b (diff)
downloadedk2-701b5797b260cbc9477380beb7fb071f3c5c88d1.tar.gz
edk2-701b5797b260cbc9477380beb7fb071f3c5c88d1.tar.bz2
edk2-701b5797b260cbc9477380beb7fb071f3c5c88d1.zip
UefiCpuPkg: Add GenSmmPageTable() to create smm page table
This commit is code refinement to current smm pagetable generation code. Add a new GenSmmPageTable() API to create smm page table based on the PageTableMap() API in CpuPageTableLib. Caller only needs to specify the paging mode and the PhysicalAddressBits to map. This function can be used to create both IA32 pae paging and X64 5level, 4level paging. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com>
Diffstat (limited to 'UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h')
-rw-r--r--UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h15
1 files changed, 15 insertions, 0 deletions
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
index 7326c13d01..1989babc67 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
@@ -556,6 +556,21 @@ Gen4GPageTable (
);
/**
+ Create page table based on input PagingMode and PhysicalAddressBits in smm.
+
+ @param[in] PagingMode The paging mode.
+ @param[in] PhysicalAddressBits The bits of physical address to map.
+
+ @retval PageTable Address
+
+**/
+UINTN
+GenSmmPageTable (
+ IN PAGING_MODE PagingMode,
+ IN UINT8 PhysicalAddressBits
+ );
+
+/**
Initialize global data for MP synchronization.
@param Stacks Base address of SMI stack buffer for all processors.