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| author | Michael Kinney <michael.d.kinney@intel.com> | 2016-11-17 20:50:27 -0800 |
|---|---|---|
| committer | Michael Kinney <michael.d.kinney@intel.com> | 2016-12-01 11:07:03 -0800 |
| commit | 26ab5ac3621bdefe96987f8c1512ca79e1bb7ac0 (patch) | |
| tree | 421bd611b4859325583c78e5948e295d43dcf332 /UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | |
| parent | 018c3c0b3e0c04f7f422a0b41b228482870d11f0 (diff) | |
| download | edk2-26ab5ac3621bdefe96987f8c1512ca79e1bb7ac0.tar.gz edk2-26ab5ac3621bdefe96987f8c1512ca79e1bb7ac0.tar.bz2 edk2-26ab5ac3621bdefe96987f8c1512ca79e1bb7ac0.zip | |
UefiCpuPkg/PiSmmCpuDxeSmm: Remove MTRRs from PSD structure
https://bugzilla.tianocore.org/show_bug.cgi?id=277
All CPUs use the same MTRR settings. Move MTRR settings
from a field in the PROCESSOR_SMM_DESCRIPTOR structure into
a module global variable.
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
Diffstat (limited to 'UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h')
| -rw-r--r-- | UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h index abe5cc612b..bd6abf28b5 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h @@ -380,7 +380,7 @@ typedef struct { UINT16 Reserved11; // Offset 0x50
UINT16 Reserved12; // Offset 0x52
UINT32 Reserved13; // Offset 0x54
- UINT64 MtrrBaseMaskPtr; // Offset 0x58
+ UINT64 Reserved14; // Offset 0x58
} PROCESSOR_SMM_DESCRIPTOR;
|