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| author | Ray Ni <ray.ni@intel.com> | 2019-06-12 17:26:45 +0800 |
|---|---|---|
| committer | Ray Ni <ray.ni@intel.com> | 2019-07-12 15:13:51 +0800 |
| commit | 4eee0cc7cc0db74489b99c19eba056b53eda6358 (patch) | |
| tree | c360139d639118a99fe6c86c0ff58b335b189656 /UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | |
| parent | 6e5a33d1fba7c170dc8680eeb81a9c7f4fe14fe6 (diff) | |
| download | edk2-4eee0cc7cc0db74489b99c19eba056b53eda6358.tar.gz edk2-4eee0cc7cc0db74489b99c19eba056b53eda6358.tar.bz2 edk2-4eee0cc7cc0db74489b99c19eba056b53eda6358.zip | |
UefiCpuPkg/PiSmmCpu: Enable 5 level paging when CPU supports
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=1946
The patch changes SMM environment to use 5 level paging when CPU
supports it.
Signed-off-by: Ray Ni <ray.ni@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
(cherry picked from commit 7365eb2c8cf1d7112330d09918c0c67e8d0b827a)
Diffstat (limited to 'UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c')
| -rw-r--r-- | UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 20 |
1 files changed, 19 insertions, 1 deletions
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c index 069be3aaa5..55090e9c3e 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c @@ -125,18 +125,36 @@ GetPageTableEntry ( UINTN Index2;
UINTN Index3;
UINTN Index4;
+ UINTN Index5;
UINT64 *L1PageTable;
UINT64 *L2PageTable;
UINT64 *L3PageTable;
UINT64 *L4PageTable;
+ UINT64 *L5PageTable;
+ IA32_CR4 Cr4;
+ BOOLEAN Enable5LevelPaging;
+ Index5 = ((UINTN)RShiftU64 (Address, 48)) & PAGING_PAE_INDEX_MASK;
Index4 = ((UINTN)RShiftU64 (Address, 39)) & PAGING_PAE_INDEX_MASK;
Index3 = ((UINTN)Address >> 30) & PAGING_PAE_INDEX_MASK;
Index2 = ((UINTN)Address >> 21) & PAGING_PAE_INDEX_MASK;
Index1 = ((UINTN)Address >> 12) & PAGING_PAE_INDEX_MASK;
+ Cr4.UintN = AsmReadCr4 ();
+ Enable5LevelPaging = (BOOLEAN) (Cr4.Bits.LA57 == 1);
+
if (sizeof(UINTN) == sizeof(UINT64)) {
- L4PageTable = (UINT64 *)GetPageTableBase ();
+ if (Enable5LevelPaging) {
+ L5PageTable = (UINT64 *)GetPageTableBase ();
+ if (L5PageTable[Index5] == 0) {
+ *PageAttribute = PageNone;
+ return NULL;
+ }
+
+ L4PageTable = (UINT64 *)(UINTN)(L5PageTable[Index5] & ~mAddressEncMask & PAGING_4K_ADDRESS_MASK_64);
+ } else {
+ L4PageTable = (UINT64 *)GetPageTableBase ();
+ }
if (L4PageTable[Index4] == 0) {
*PageAttribute = PageNone;
return NULL;
|