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| author | Ray Ni <ray.ni@intel.com> | 2019-06-12 17:26:45 +0800 |
|---|---|---|
| committer | Ray Ni <ray.ni@intel.com> | 2019-07-12 15:13:51 +0800 |
| commit | 4eee0cc7cc0db74489b99c19eba056b53eda6358 (patch) | |
| tree | c360139d639118a99fe6c86c0ff58b335b189656 /UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm | |
| parent | 6e5a33d1fba7c170dc8680eeb81a9c7f4fe14fe6 (diff) | |
| download | edk2-4eee0cc7cc0db74489b99c19eba056b53eda6358.tar.gz edk2-4eee0cc7cc0db74489b99c19eba056b53eda6358.tar.bz2 edk2-4eee0cc7cc0db74489b99c19eba056b53eda6358.zip | |
UefiCpuPkg/PiSmmCpu: Enable 5 level paging when CPU supports
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=1946
The patch changes SMM environment to use 5 level paging when CPU
supports it.
Signed-off-by: Ray Ni <ray.ni@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
(cherry picked from commit 7365eb2c8cf1d7112330d09918c0c67e8d0b827a)
Diffstat (limited to 'UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm')
| -rw-r--r-- | UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm index 741e4b7da2..271492a9d7 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm @@ -69,6 +69,7 @@ extern ASM_PFX(mXdSupported) global ASM_PFX(gPatchXdSupported)
global ASM_PFX(gPatchSmiStack)
global ASM_PFX(gPatchSmiCr3)
+global ASM_PFX(gPatch5LevelPagingSupport)
global ASM_PFX(gcSmiHandlerTemplate)
global ASM_PFX(gcSmiHandlerSize)
@@ -124,6 +125,17 @@ ProtFlatMode: ASM_PFX(gPatchSmiCr3):
mov cr3, rax
mov eax, 0x668 ; as cr4.PGE is not set here, refresh cr3
+
+ mov cl, strict byte 0 ; source operand will be patched
+ASM_PFX(gPatch5LevelPagingSupport):
+ cmp cl, 0
+ je SkipEnable5LevelPaging
+ ;
+ ; Enable 5-Level Paging bit
+ ;
+ bts eax, 12 ; Set LA57 bit (bit #12)
+SkipEnable5LevelPaging:
+
mov cr4, rax ; in PreModifyMtrrs() to flush TLB.
; Load TSS
sub esp, 8 ; reserve room in stack
|