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authorLaszlo Ersek <lersek@redhat.com>2018-02-02 04:46:26 +0100
committerLaszlo Ersek <lersek@redhat.com>2018-04-04 16:44:23 +0200
commit5830d2c399f82f09853fac81956495f06c3a4064 (patch)
tree8737a186edf6069004cfcd52566755a06a12e00d /UefiCpuPkg/PiSmmCpuDxeSmm
parent456c4ccab27b79f1b9c8d13ddcb5ed5453c09c53 (diff)
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UefiCpuPkg/PiSmmCpuDxeSmm: patch "gSmmInitStack" with PatchInstructionX86()
Rename the variable to "gPatchSmmInitStack" so that its association with PatchInstructionX86() is clear from the declaration, change its type to X86_ASSEMBLY_PATCH_LABEL, and patch it with PatchInstructionX86(). This lets us remove the binary (DB) encoding of some instructions in "SmmInit.nasm". The size of the patched source operand is (sizeof (UINTN)). Cc: Eric Dong <eric.dong@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=866 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
Diffstat (limited to 'UefiCpuPkg/PiSmmCpuDxeSmm')
-rw-r--r--UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm6
-rwxr-xr-xUefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c6
-rw-r--r--UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h2
-rw-r--r--UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm6
4 files changed, 12 insertions, 8 deletions
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm
index f59413d9d4..5ff3cd2e73 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm
@@ -25,7 +25,7 @@ extern ASM_PFX(mSmmRelocationOriginalAddress)
global ASM_PFX(gPatchSmmCr3)
global ASM_PFX(gPatchSmmCr4)
global ASM_PFX(gPatchSmmCr0)
-global ASM_PFX(gSmmInitStack)
+global ASM_PFX(gPatchSmmInitStack)
global ASM_PFX(gcSmiInitGdtr)
global ASM_PFX(gcSmmInitSize)
global ASM_PFX(gcSmmInitTemplate)
@@ -72,8 +72,8 @@ BITS 32
mov fs, edi
mov gs, edi
mov ss, edi
- DB 0xbc ; mov esp, imm32
-ASM_PFX(gSmmInitStack): DD 0
+ mov esp, strict dword 0 ; source operand will be patched
+ASM_PFX(gPatchSmmInitStack):
call ASM_PFX(SmmInitHandler)
rsm
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
index 0c8a4543d8..fbf74e8d90 100755
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
@@ -848,7 +848,11 @@ PiCpuSmmEntry (
//
// Set SMI stack for SMM base relocation
//
- gSmmInitStack = (UINTN) (Stacks + mSmmStackSize - sizeof (UINTN));
+ PatchInstructionX86 (
+ gPatchSmmInitStack,
+ (UINTN) (Stacks + mSmmStackSize - sizeof (UINTN)),
+ sizeof (UINTN)
+ );
//
// Initialize IDT
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
index d897d4353e..1d016594e0 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
@@ -302,7 +302,7 @@ extern UINT32 mSmmCr0;
X86_ASSEMBLY_PATCH_LABEL gPatchSmmCr3;
extern UINT32 mSmmCr4;
X86_ASSEMBLY_PATCH_LABEL gPatchSmmCr4;
-extern UINTN gSmmInitStack;
+X86_ASSEMBLY_PATCH_LABEL gPatchSmmInitStack;
/**
Semaphore operation for all processor relocate SMMBase.
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
index 2460e1eb2d..eae14c0549 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
@@ -25,7 +25,7 @@ extern ASM_PFX(mSmmRelocationOriginalAddress)
global ASM_PFX(gPatchSmmCr3)
global ASM_PFX(gPatchSmmCr4)
global ASM_PFX(gPatchSmmCr0)
-global ASM_PFX(gSmmInitStack)
+global ASM_PFX(gPatchSmmInitStack)
global ASM_PFX(gcSmiInitGdtr)
global ASM_PFX(gcSmmInitSize)
global ASM_PFX(gcSmmInitTemplate)
@@ -72,8 +72,8 @@ ASM_PFX(gPatchSmmCr0):
BITS 64
@LongMode: ; long-mode starts here
- DB 0x48, 0xbc ; mov rsp, imm64
-ASM_PFX(gSmmInitStack): DQ 0
+ mov rsp, strict qword 0 ; source operand will be patched
+ASM_PFX(gPatchSmmInitStack):
and sp, 0xfff0 ; make sure RSP is 16-byte aligned
;
; Accoring to X64 calling convention, XMM0~5 are volatile, we need to save