diff options
| author | Michael Kubacki <michael.kubacki@microsoft.com> | 2021-12-05 14:54:17 -0800 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2021-12-07 17:24:28 +0000 |
| commit | 053e878bfb5c9d5eca779789b62891add30b14ba (patch) | |
| tree | 1cdf5bacb37306e373b8d14bd67c5b3e4f3b269f /UefiCpuPkg/PiSmmCpuDxeSmm | |
| parent | 91415a36ae7aaeabb2bbab3762f39544f9aed683 (diff) | |
| download | edk2-053e878bfb5c9d5eca779789b62891add30b14ba.tar.gz edk2-053e878bfb5c9d5eca779789b62891add30b14ba.tar.bz2 edk2-053e878bfb5c9d5eca779789b62891add30b14ba.zip | |
UefiCpuPkg: Apply uncrustify changes
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737
Apply uncrustify changes to .c/.h files in the UefiCpuPkg package
Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Diffstat (limited to 'UefiCpuPkg/PiSmmCpuDxeSmm')
24 files changed, 2415 insertions, 2175 deletions
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c index 0d723336e4..9b45c442c9 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c @@ -10,42 +10,42 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #pragma pack(1)
typedef struct {
- UINTN Lock;
- VOID *StackStart;
- UINTN StackSize;
- VOID *ApFunction;
- IA32_DESCRIPTOR GdtrProfile;
- IA32_DESCRIPTOR IdtrProfile;
- UINT32 BufferStart;
- UINT32 Cr3;
- UINTN InitializeFloatingPointUnitsAddress;
+ UINTN Lock;
+ VOID *StackStart;
+ UINTN StackSize;
+ VOID *ApFunction;
+ IA32_DESCRIPTOR GdtrProfile;
+ IA32_DESCRIPTOR IdtrProfile;
+ UINT32 BufferStart;
+ UINT32 Cr3;
+ UINTN InitializeFloatingPointUnitsAddress;
} MP_CPU_EXCHANGE_INFO;
#pragma pack()
typedef struct {
- UINT8 *RendezvousFunnelAddress;
- UINTN PModeEntryOffset;
- UINTN FlatJumpOffset;
- UINTN Size;
- UINTN LModeEntryOffset;
- UINTN LongJumpOffset;
+ UINT8 *RendezvousFunnelAddress;
+ UINTN PModeEntryOffset;
+ UINTN FlatJumpOffset;
+ UINTN Size;
+ UINTN LModeEntryOffset;
+ UINTN LongJumpOffset;
} MP_ASSEMBLY_ADDRESS_MAP;
//
// Flags used when program the register.
//
typedef struct {
- volatile UINTN MemoryMappedLock; // Spinlock used to program mmio
- volatile UINT32 *CoreSemaphoreCount; // Semaphore container used to program
+ volatile UINTN MemoryMappedLock; // Spinlock used to program mmio
+ volatile UINT32 *CoreSemaphoreCount; // Semaphore container used to program
// core level semaphore.
- volatile UINT32 *PackageSemaphoreCount; // Semaphore container used to program
+ volatile UINT32 *PackageSemaphoreCount; // Semaphore container used to program
// package level semaphore.
} PROGRAM_CPU_REGISTER_FLAGS;
//
// Signal that SMM BASE relocation is complete.
//
-volatile BOOLEAN mInitApsAfterSmmBaseReloc;
+volatile BOOLEAN mInitApsAfterSmmBaseReloc;
/**
Get starting address and size of the rendezvous entry for APs.
@@ -56,38 +56,38 @@ volatile BOOLEAN mInitApsAfterSmmBaseReloc; VOID *
EFIAPI
AsmGetAddressMap (
- MP_ASSEMBLY_ADDRESS_MAP *AddressMap
+ MP_ASSEMBLY_ADDRESS_MAP *AddressMap
);
-#define LEGACY_REGION_SIZE (2 * 0x1000)
-#define LEGACY_REGION_BASE (0xA0000 - LEGACY_REGION_SIZE)
+#define LEGACY_REGION_SIZE (2 * 0x1000)
+#define LEGACY_REGION_BASE (0xA0000 - LEGACY_REGION_SIZE)
-PROGRAM_CPU_REGISTER_FLAGS mCpuFlags;
-ACPI_CPU_DATA mAcpiCpuData;
-volatile UINT32 mNumberToFinish;
-MP_CPU_EXCHANGE_INFO *mExchangeInfo;
-BOOLEAN mRestoreSmmConfigurationInS3 = FALSE;
+PROGRAM_CPU_REGISTER_FLAGS mCpuFlags;
+ACPI_CPU_DATA mAcpiCpuData;
+volatile UINT32 mNumberToFinish;
+MP_CPU_EXCHANGE_INFO *mExchangeInfo;
+BOOLEAN mRestoreSmmConfigurationInS3 = FALSE;
//
// S3 boot flag
//
-BOOLEAN mSmmS3Flag = FALSE;
+BOOLEAN mSmmS3Flag = FALSE;
//
// Pointer to structure used during S3 Resume
//
-SMM_S3_RESUME_STATE *mSmmS3ResumeState = NULL;
+SMM_S3_RESUME_STATE *mSmmS3ResumeState = NULL;
-BOOLEAN mAcpiS3Enable = TRUE;
+BOOLEAN mAcpiS3Enable = TRUE;
-UINT8 *mApHltLoopCode = NULL;
-UINT8 mApHltLoopCodeTemplate[] = {
- 0x8B, 0x44, 0x24, 0x04, // mov eax, dword ptr [esp+4]
- 0xF0, 0xFF, 0x08, // lock dec dword ptr [eax]
- 0xFA, // cli
- 0xF4, // hlt
- 0xEB, 0xFC // jmp $-2
- };
+UINT8 *mApHltLoopCode = NULL;
+UINT8 mApHltLoopCodeTemplate[] = {
+ 0x8B, 0x44, 0x24, 0x04, // mov eax, dword ptr [esp+4]
+ 0xF0, 0xFF, 0x08, // lock dec dword ptr [eax]
+ 0xFA, // cli
+ 0xF4, // hlt
+ 0xEB, 0xFC // jmp $-2
+};
/**
Sync up the MTRR values for all processors.
@@ -97,8 +97,9 @@ UINT8 mApHltLoopCodeTemplate[] = { VOID
EFIAPI
LoadMtrrData (
- EFI_PHYSICAL_ADDRESS MtrrTable
+ EFI_PHYSICAL_ADDRESS MtrrTable
)
+
/*++
Routine Description:
@@ -112,9 +113,9 @@ Returns: --*/
{
- MTRR_SETTINGS *MtrrSettings;
+ MTRR_SETTINGS *MtrrSettings;
- MtrrSettings = (MTRR_SETTINGS *) (UINTN) MtrrTable;
+ MtrrSettings = (MTRR_SETTINGS *)(UINTN)MtrrTable;
MtrrSetAllMtrrs (MtrrSettings);
}
@@ -126,7 +127,7 @@ Returns: **/
VOID
S3ReleaseSemaphore (
- IN OUT volatile UINT32 *Sem
+ IN OUT volatile UINT32 *Sem
)
{
InterlockedIncrement (Sem);
@@ -144,7 +145,7 @@ S3ReleaseSemaphore ( **/
VOID
S3WaitForSemaphore (
- IN OUT volatile UINT32 *Sem
+ IN OUT volatile UINT32 *Sem
)
{
UINT32 Value;
@@ -170,42 +171,46 @@ S3WaitForSemaphore ( **/
UINTN
ReadWriteCr (
- IN UINT32 CrIndex,
- IN BOOLEAN Read,
- IN OUT UINTN *CrValue
+ IN UINT32 CrIndex,
+ IN BOOLEAN Read,
+ IN OUT UINTN *CrValue
)
{
switch (CrIndex) {
- case 0:
- if (Read) {
- *CrValue = AsmReadCr0 ();
- } else {
- AsmWriteCr0 (*CrValue);
- }
- break;
- case 2:
- if (Read) {
- *CrValue = AsmReadCr2 ();
- } else {
- AsmWriteCr2 (*CrValue);
- }
- break;
- case 3:
- if (Read) {
- *CrValue = AsmReadCr3 ();
- } else {
- AsmWriteCr3 (*CrValue);
- }
- break;
- case 4:
- if (Read) {
- *CrValue = AsmReadCr4 ();
- } else {
- AsmWriteCr4 (*CrValue);
- }
- break;
- default:
- return EFI_UNSUPPORTED;;
+ case 0:
+ if (Read) {
+ *CrValue = AsmReadCr0 ();
+ } else {
+ AsmWriteCr0 (*CrValue);
+ }
+
+ break;
+ case 2:
+ if (Read) {
+ *CrValue = AsmReadCr2 ();
+ } else {
+ AsmWriteCr2 (*CrValue);
+ }
+
+ break;
+ case 3:
+ if (Read) {
+ *CrValue = AsmReadCr3 ();
+ } else {
+ AsmWriteCr3 (*CrValue);
+ }
+
+ break;
+ case 4:
+ if (Read) {
+ *CrValue = AsmReadCr4 ();
+ } else {
+ AsmWriteCr4 (*CrValue);
+ }
+
+ break;
+ default:
+ return EFI_UNSUPPORTED;
}
return EFI_SUCCESS;
@@ -223,10 +228,10 @@ ReadWriteCr ( **/
VOID
ProgramProcessorRegister (
- IN CPU_REGISTER_TABLE *RegisterTable,
- IN EFI_CPU_PHYSICAL_LOCATION *ApLocation,
- IN CPU_STATUS_INFORMATION *CpuStatus,
- IN PROGRAM_CPU_REGISTER_FLAGS *CpuFlags
+ IN CPU_REGISTER_TABLE *RegisterTable,
+ IN EFI_CPU_PHYSICAL_LOCATION *ApLocation,
+ IN CPU_STATUS_INFORMATION *CpuStatus,
+ IN PROGRAM_CPU_REGISTER_FLAGS *CpuFlags
)
{
CPU_REGISTER_TABLE_ENTRY *RegisterTableEntry;
@@ -246,53 +251,25 @@ ProgramProcessorRegister ( //
// Traverse Register Table of this logical processor
//
- RegisterTableEntryHead = (CPU_REGISTER_TABLE_ENTRY *) (UINTN) RegisterTable->RegisterTableEntry;
+ RegisterTableEntryHead = (CPU_REGISTER_TABLE_ENTRY *)(UINTN)RegisterTable->RegisterTableEntry;
for (Index = 0; Index < RegisterTable->TableLength; Index++) {
-
RegisterTableEntry = &RegisterTableEntryHead[Index];
//
// Check the type of specified register
//
switch (RegisterTableEntry->RegisterType) {
- //
- // The specified register is Control Register
- //
- case ControlRegister:
- Status = ReadWriteCr (RegisterTableEntry->Index, TRUE, &Value);
- if (EFI_ERROR (Status)) {
- break;
- }
- if (RegisterTableEntry->TestThenWrite) {
- CurrentValue = BitFieldRead64 (
- Value,
- RegisterTableEntry->ValidBitStart,
- RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1
- );
- if (CurrentValue == RegisterTableEntry->Value) {
+ //
+ // The specified register is Control Register
+ //
+ case ControlRegister:
+ Status = ReadWriteCr (RegisterTableEntry->Index, TRUE, &Value);
+ if (EFI_ERROR (Status)) {
break;
}
- }
- Value = (UINTN) BitFieldWrite64 (
- Value,
- RegisterTableEntry->ValidBitStart,
- RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,
- RegisterTableEntry->Value
- );
- ReadWriteCr (RegisterTableEntry->Index, FALSE, &Value);
- break;
- //
- // The specified register is Model Specific Register
- //
- case Msr:
- if (RegisterTableEntry->TestThenWrite) {
- Value = (UINTN)AsmReadMsr64 (RegisterTableEntry->Index);
- if (RegisterTableEntry->ValidBitLength >= 64) {
- if (Value == RegisterTableEntry->Value) {
- break;
- }
- } else {
+
+ if (RegisterTableEntry->TestThenWrite) {
CurrentValue = BitFieldRead64 (
Value,
RegisterTableEntry->ValidBitStart,
@@ -302,164 +279,200 @@ ProgramProcessorRegister ( break;
}
}
- }
+ Value = (UINTN)BitFieldWrite64 (
+ Value,
+ RegisterTableEntry->ValidBitStart,
+ RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,
+ RegisterTableEntry->Value
+ );
+ ReadWriteCr (RegisterTableEntry->Index, FALSE, &Value);
+ break;
//
- // If this function is called to restore register setting after INIT signal,
- // there is no need to restore MSRs in register table.
+ // The specified register is Model Specific Register
//
- if (RegisterTableEntry->ValidBitLength >= 64) {
- //
- // If length is not less than 64 bits, then directly write without reading
- //
- AsmWriteMsr64 (
- RegisterTableEntry->Index,
- RegisterTableEntry->Value
- );
- } else {
+ case Msr:
+ if (RegisterTableEntry->TestThenWrite) {
+ Value = (UINTN)AsmReadMsr64 (RegisterTableEntry->Index);
+ if (RegisterTableEntry->ValidBitLength >= 64) {
+ if (Value == RegisterTableEntry->Value) {
+ break;
+ }
+ } else {
+ CurrentValue = BitFieldRead64 (
+ Value,
+ RegisterTableEntry->ValidBitStart,
+ RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1
+ );
+ if (CurrentValue == RegisterTableEntry->Value) {
+ break;
+ }
+ }
+ }
+
//
- // Set the bit section according to bit start and length
+ // If this function is called to restore register setting after INIT signal,
+ // there is no need to restore MSRs in register table.
//
- AsmMsrBitFieldWrite64 (
- RegisterTableEntry->Index,
- RegisterTableEntry->ValidBitStart,
- RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,
- RegisterTableEntry->Value
- );
- }
- break;
- //
- // MemoryMapped operations
- //
- case MemoryMapped:
- AcquireSpinLock (&CpuFlags->MemoryMappedLock);
- MmioBitFieldWrite32 (
- (UINTN)(RegisterTableEntry->Index | LShiftU64 (RegisterTableEntry->HighIndex, 32)),
- RegisterTableEntry->ValidBitStart,
- RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,
- (UINT32)RegisterTableEntry->Value
- );
- ReleaseSpinLock (&CpuFlags->MemoryMappedLock);
- break;
- //
- // Enable or disable cache
- //
- case CacheControl:
- //
- // If value of the entry is 0, then disable cache. Otherwise, enable cache.
- //
- if (RegisterTableEntry->Value == 0) {
- AsmDisableCache ();
- } else {
- AsmEnableCache ();
- }
- break;
+ if (RegisterTableEntry->ValidBitLength >= 64) {
+ //
+ // If length is not less than 64 bits, then directly write without reading
+ //
+ AsmWriteMsr64 (
+ RegisterTableEntry->Index,
+ RegisterTableEntry->Value
+ );
+ } else {
+ //
+ // Set the bit section according to bit start and length
+ //
+ AsmMsrBitFieldWrite64 (
+ RegisterTableEntry->Index,
+ RegisterTableEntry->ValidBitStart,
+ RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,
+ RegisterTableEntry->Value
+ );
+ }
- case Semaphore:
- // Semaphore works logic like below:
- //
- // V(x) = LibReleaseSemaphore (Semaphore[FirstThread + x]);
- // P(x) = LibWaitForSemaphore (Semaphore[FirstThread + x]);
- //
- // All threads (T0...Tn) waits in P() line and continues running
- // together.
+ break;
//
+ // MemoryMapped operations
//
- // T0 T1 ... Tn
+ case MemoryMapped:
+ AcquireSpinLock (&CpuFlags->MemoryMappedLock);
+ MmioBitFieldWrite32 (
+ (UINTN)(RegisterTableEntry->Index | LShiftU64 (RegisterTableEntry->HighIndex, 32)),
+ RegisterTableEntry->ValidBitStart,
+ RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,
+ (UINT32)RegisterTableEntry->Value
+ );
+ ReleaseSpinLock (&CpuFlags->MemoryMappedLock);
+ break;
//
- // V(0...n) V(0...n) ... V(0...n)
- // n * P(0) n * P(1) ... n * P(n)
+ // Enable or disable cache
//
- ASSERT (
- (ApLocation != NULL) &&
- (CpuStatus->ThreadCountPerPackage != 0) &&
- (CpuStatus->ThreadCountPerCore != 0) &&
- (CpuFlags->CoreSemaphoreCount != NULL) &&
- (CpuFlags->PackageSemaphoreCount != NULL)
- );
- switch (RegisterTableEntry->Value) {
- case CoreDepType:
- SemaphorePtr = CpuFlags->CoreSemaphoreCount;
- ThreadCountPerCore = (UINT8 *)(UINTN)CpuStatus->ThreadCountPerCore;
-
- CurrentCore = ApLocation->Package * CpuStatus->MaxCoreCount + ApLocation->Core;
- //
- // Get Offset info for the first thread in the core which current thread belongs to.
+ case CacheControl:
//
- FirstThread = CurrentCore * CpuStatus->MaxThreadCount;
- CurrentThread = FirstThread + ApLocation->Thread;
-
- //
- // Different cores may have different valid threads in them. If driver maintail clearly
- // thread index in different cores, the logic will be much complicated.
- // Here driver just simply records the max thread number in all cores and use it as expect
- // thread number for all cores.
- // In below two steps logic, first current thread will Release semaphore for each thread
- // in current core. Maybe some threads are not valid in this core, but driver don't
- // care. Second, driver will let current thread wait semaphore for all valid threads in
- // current core. Because only the valid threads will do release semaphore for this
- // thread, driver here only need to wait the valid thread count.
- //
-
+ // If value of the entry is 0, then disable cache. Otherwise, enable cache.
//
- // First Notify ALL THREADs in current Core that this thread is ready.
- //
- for (ProcessorIndex = 0; ProcessorIndex < CpuStatus->MaxThreadCount; ProcessorIndex ++) {
- S3ReleaseSemaphore (&SemaphorePtr[FirstThread + ProcessorIndex]);
- }
- //
- // Second, check whether all VALID THREADs (not all threads) in current core are ready.
- //
- for (ProcessorIndex = 0; ProcessorIndex < ThreadCountPerCore[CurrentCore]; ProcessorIndex ++) {
- S3WaitForSemaphore (&SemaphorePtr[CurrentThread]);
+ if (RegisterTableEntry->Value == 0) {
+ AsmDisableCache ();
+ } else {
+ AsmEnableCache ();
}
+
break;
- case PackageDepType:
- SemaphorePtr = CpuFlags->PackageSemaphoreCount;
- ThreadCountPerPackage = (UINT32 *)(UINTN)CpuStatus->ThreadCountPerPackage;
+ case Semaphore:
+ // Semaphore works logic like below:
//
- // Get Offset info for the first thread in the package which current thread belongs to.
+ // V(x) = LibReleaseSemaphore (Semaphore[FirstThread + x]);
+ // P(x) = LibWaitForSemaphore (Semaphore[FirstThread + x]);
//
- FirstThread = ApLocation->Package * CpuStatus->MaxCoreCount * CpuStatus->MaxThreadCount;
+ // All threads (T0...Tn) waits in P() line and continues running
+ // together.
//
- // Get the possible threads count for current package.
//
- CurrentThread = FirstThread + CpuStatus->MaxThreadCount * ApLocation->Core + ApLocation->Thread;
-
+ // T0 T1 ... Tn
//
- // Different packages may have different valid threads in them. If driver maintail clearly
- // thread index in different packages, the logic will be much complicated.
- // Here driver just simply records the max thread number in all packages and use it as expect
- // thread number for all packages.
- // In below two steps logic, first current thread will Release semaphore for each thread
- // in current package. Maybe some threads are not valid in this package, but driver don't
- // care. Second, driver will let current thread wait semaphore for all valid threads in
- // current package. Because only the valid threads will do release semaphore for this
- // thread, driver here only need to wait the valid thread count.
+ // V(0...n) V(0...n) ... V(0...n)
+ // n * P(0) n * P(1) ... n * P(n)
//
+ ASSERT (
+ (ApLocation != NULL) &&
+ (CpuStatus->ThreadCountPerPackage != 0) &&
+ (CpuStatus->ThreadCountPerCore != 0) &&
+ (CpuFlags->CoreSemaphoreCount != NULL) &&
+ (CpuFlags->PackageSemaphoreCount != NULL)
+ );
+ switch (RegisterTableEntry->Value) {
+ case CoreDepType:
+ SemaphorePtr = CpuFlags->CoreSemaphoreCount;
+ ThreadCountPerCore = (UINT8 *)(UINTN)CpuStatus->ThreadCountPerCore;
+
+ CurrentCore = ApLocation->Package * CpuStatus->MaxCoreCount + ApLocation->Core;
+ //
+ // Get Offset info for the first thread in the core which current thread belongs to.
+ //
+ FirstThread = CurrentCore * CpuStatus->MaxThreadCount;
+ CurrentThread = FirstThread + ApLocation->Thread;
+
+ //
+ // Different cores may have different valid threads in them. If driver maintail clearly
+ // thread index in different cores, the logic will be much complicated.
+ // Here driver just simply records the max thread number in all cores and use it as expect
+ // thread number for all cores.
+ // In below two steps logic, first current thread will Release semaphore for each thread
+ // in current core. Maybe some threads are not valid in this core, but driver don't
+ // care. Second, driver will let current thread wait semaphore for all valid threads in
+ // current core. Because only the valid threads will do release semaphore for this
+ // thread, driver here only need to wait the valid thread count.
+ //
+
+ //
+ // First Notify ALL THREADs in current Core that this thread is ready.
+ //
+ for (ProcessorIndex = 0; ProcessorIndex < CpuStatus->MaxThreadCount; ProcessorIndex++) {
+ S3ReleaseSemaphore (&SemaphorePtr[FirstThread + ProcessorIndex]);
+ }
+
+ //
+ // Second, check whether all VALID THREADs (not all threads) in current core are ready.
+ //
+ for (ProcessorIndex = 0; ProcessorIndex < ThreadCountPerCore[CurrentCore]; ProcessorIndex++) {
+ S3WaitForSemaphore (&SemaphorePtr[CurrentThread]);
+ }
- //
- // First Notify ALL THREADS in current package that this thread is ready.
- //
- for (ProcessorIndex = 0; ProcessorIndex < CpuStatus->MaxThreadCount * CpuStatus->MaxCoreCount; ProcessorIndex ++) {
- S3ReleaseSemaphore (&SemaphorePtr[FirstThread + ProcessorIndex]);
- }
- //
- // Second, check whether VALID THREADS (not all threads) in current package are ready.
- //
- for (ProcessorIndex = 0; ProcessorIndex < ThreadCountPerPackage[ApLocation->Package]; ProcessorIndex ++) {
- S3WaitForSemaphore (&SemaphorePtr[CurrentThread]);
+ break;
+
+ case PackageDepType:
+ SemaphorePtr = CpuFlags->PackageSemaphoreCount;
+ ThreadCountPerPackage = (UINT32 *)(UINTN)CpuStatus->ThreadCountPerPackage;
+ //
+ // Get Offset info for the first thread in the package which current thread belongs to.
+ //
+ FirstThread = ApLocation->Package * CpuStatus->MaxCoreCount * CpuStatus->MaxThreadCount;
+ //
+ // Get the possible threads count for current package.
+ //
+ CurrentThread = FirstThread + CpuStatus->MaxThreadCount * ApLocation->Core + ApLocation->Thread;
+
+ //
+ // Different packages may have different valid threads in them. If driver maintail clearly
+ // thread index in different packages, the logic will be much complicated.
+ // Here driver just simply records the max thread number in all packages and use it as expect
+ // thread number for all packages.
+ // In below two steps logic, first current thread will Release semaphore for each thread
+ // in current package. Maybe some threads are not valid in this package, but driver don't
+ // care. Second, driver will let current thread wait semaphore for all valid threads in
+ // current package. Because only the valid threads will do release semaphore for this
+ // thread, driver here only need to wait the valid thread count.
+ //
+
+ //
+ // First Notify ALL THREADS in current package that this thread is ready.
+ //
+ for (ProcessorIndex = 0; ProcessorIndex < CpuStatus->MaxThreadCount * CpuStatus->MaxCoreCount; ProcessorIndex++) {
+ S3ReleaseSemaphore (&SemaphorePtr[FirstThread + ProcessorIndex]);
+ }
+
+ //
+ // Second, check whether VALID THREADS (not all threads) in current package are ready.
+ //
+ for (ProcessorIndex = 0; ProcessorIndex < ThreadCountPerPackage[ApLocation->Package]; ProcessorIndex++) {
+ S3WaitForSemaphore (&SemaphorePtr[CurrentThread]);
+ }
+
+ break;
+
+ default:
+ break;
}
+
break;
default:
break;
- }
- break;
-
- default:
- break;
}
}
}
@@ -473,15 +486,15 @@ ProgramProcessorRegister ( **/
VOID
SetRegister (
- IN BOOLEAN PreSmmRegisterTable
+ IN BOOLEAN PreSmmRegisterTable
)
{
- CPU_FEATURE_INIT_DATA *FeatureInitData;
- CPU_REGISTER_TABLE *RegisterTable;
- CPU_REGISTER_TABLE *RegisterTables;
- UINT32 InitApicId;
- UINTN ProcIndex;
- UINTN Index;
+ CPU_FEATURE_INIT_DATA *FeatureInitData;
+ CPU_REGISTER_TABLE *RegisterTable;
+ CPU_REGISTER_TABLE *RegisterTables;
+ UINT32 InitApicId;
+ UINTN ProcIndex;
+ UINTN Index;
FeatureInitData = &mAcpiCpuData.CpuFeatureInitData;
@@ -490,20 +503,22 @@ SetRegister ( } else {
RegisterTables = (CPU_REGISTER_TABLE *)(UINTN)FeatureInitData->RegisterTable;
}
+
if (RegisterTables == NULL) {
return;
}
- InitApicId = GetInitialApicId ();
+ InitApicId = GetInitialApicId ();
RegisterTable = NULL;
- ProcIndex = (UINTN)-1;
+ ProcIndex = (UINTN)-1;
for (Index = 0; Index < mAcpiCpuData.NumberOfCpus; Index++) {
if (RegisterTables[Index].InitialApicId == InitApicId) {
RegisterTable = &RegisterTables[Index];
- ProcIndex = Index;
+ ProcIndex = Index;
break;
}
}
+
ASSERT (RegisterTable != NULL);
if (FeatureInitData->ApLocation != 0) {
@@ -531,8 +546,8 @@ InitializeAp ( VOID
)
{
- UINTN TopOfStack;
- UINT8 Stack[128];
+ UINTN TopOfStack;
+ UINT8 Stack[128];
LoadMtrrData (mAcpiCpuData.MtrrTable);
@@ -558,9 +573,9 @@ InitializeAp ( //
// Place AP into the safe code, count down the number with lock mechanism in the safe code.
//
- TopOfStack = (UINTN) Stack + sizeof (Stack);
- TopOfStack &= ~(UINTN) (CPU_STACK_ALIGNMENT - 1);
- CopyMem ((VOID *) (UINTN) mApHltLoopCode, mApHltLoopCodeTemplate, sizeof (mApHltLoopCodeTemplate));
+ TopOfStack = (UINTN)Stack + sizeof (Stack);
+ TopOfStack &= ~(UINTN)(CPU_STACK_ALIGNMENT - 1);
+ CopyMem ((VOID *)(UINTN)mApHltLoopCode, mApHltLoopCodeTemplate, sizeof (mApHltLoopCodeTemplate));
TransferApToSafeState ((UINTN)mApHltLoopCode, TopOfStack, (UINTN)&mNumberToFinish);
}
@@ -576,8 +591,8 @@ PrepareApStartupVector ( EFI_PHYSICAL_ADDRESS WorkingBuffer
)
{
- EFI_PHYSICAL_ADDRESS StartupVector;
- MP_ASSEMBLY_ADDRESS_MAP AddressMap;
+ EFI_PHYSICAL_ADDRESS StartupVector;
+ MP_ASSEMBLY_ADDRESS_MAP AddressMap;
//
// Get the address map of startup code for AP,
@@ -592,25 +607,25 @@ PrepareApStartupVector ( // Copy AP startup code to startup vector, and then redirect the long jump
// instructions for mode switching.
//
- CopyMem ((VOID *) (UINTN) StartupVector, AddressMap.RendezvousFunnelAddress, AddressMap.Size);
- *(UINT32 *) (UINTN) (StartupVector + AddressMap.FlatJumpOffset + 3) = (UINT32) (StartupVector + AddressMap.PModeEntryOffset);
+ CopyMem ((VOID *)(UINTN)StartupVector, AddressMap.RendezvousFunnelAddress, AddressMap.Size);
+ *(UINT32 *)(UINTN)(StartupVector + AddressMap.FlatJumpOffset + 3) = (UINT32)(StartupVector + AddressMap.PModeEntryOffset);
if (AddressMap.LongJumpOffset != 0) {
- *(UINT32 *) (UINTN) (StartupVector + AddressMap.LongJumpOffset + 2) = (UINT32) (StartupVector + AddressMap.LModeEntryOffset);
+ *(UINT32 *)(UINTN)(StartupVector + AddressMap.LongJumpOffset + 2) = (UINT32)(StartupVector + AddressMap.LModeEntryOffset);
}
//
// Get the start address of exchange data between BSP and AP.
//
- mExchangeInfo = (MP_CPU_EXCHANGE_INFO *) (UINTN) (StartupVector + AddressMap.Size);
- ZeroMem ((VOID *) mExchangeInfo, sizeof (MP_CPU_EXCHANGE_INFO));
+ mExchangeInfo = (MP_CPU_EXCHANGE_INFO *)(UINTN)(StartupVector + AddressMap.Size);
+ ZeroMem ((VOID *)mExchangeInfo, sizeof (MP_CPU_EXCHANGE_INFO));
- CopyMem ((VOID *) (UINTN) &mExchangeInfo->GdtrProfile, (VOID *) (UINTN) mAcpiCpuData.GdtrProfile, sizeof (IA32_DESCRIPTOR));
- CopyMem ((VOID *) (UINTN) &mExchangeInfo->IdtrProfile, (VOID *) (UINTN) mAcpiCpuData.IdtrProfile, sizeof (IA32_DESCRIPTOR));
+ CopyMem ((VOID *)(UINTN)&mExchangeInfo->GdtrProfile, (VOID *)(UINTN)mAcpiCpuData.GdtrProfile, sizeof (IA32_DESCRIPTOR));
+ CopyMem ((VOID *)(UINTN)&mExchangeInfo->IdtrProfile, (VOID *)(UINTN)mAcpiCpuData.IdtrProfile, sizeof (IA32_DESCRIPTOR));
- mExchangeInfo->StackStart = (VOID *) (UINTN) mAcpiCpuData.StackAddress;
- mExchangeInfo->StackSize = mAcpiCpuData.StackSize;
- mExchangeInfo->BufferStart = (UINT32) StartupVector;
- mExchangeInfo->Cr3 = (UINT32) (AsmReadCr3 ());
+ mExchangeInfo->StackStart = (VOID *)(UINTN)mAcpiCpuData.StackAddress;
+ mExchangeInfo->StackSize = mAcpiCpuData.StackSize;
+ mExchangeInfo->BufferStart = (UINT32)StartupVector;
+ mExchangeInfo->Cr3 = (UINT32)(AsmReadCr3 ());
mExchangeInfo->InitializeFloatingPointUnitsAddress = (UINTN)InitializeFloatingPointUnits;
}
@@ -639,8 +654,9 @@ InitializeCpuBeforeRebase ( } else {
ASSERT (mNumberOfCpus == mAcpiCpuData.NumberOfCpus);
}
- mNumberToFinish = (UINT32)(mNumberOfCpus - 1);
- mExchangeInfo->ApFunction = (VOID *) (UINTN) InitializeAp;
+
+ mNumberToFinish = (UINT32)(mNumberOfCpus - 1);
+ mExchangeInfo->ApFunction = (VOID *)(UINTN)InitializeAp;
//
// Execute code for before SmmBaseReloc. Note: This flag is maintained across S3 boots.
@@ -674,6 +690,7 @@ InitializeCpuAfterRebase ( } else {
ASSERT (mNumberOfCpus == mAcpiCpuData.NumberOfCpus);
}
+
mNumberToFinish = (UINT32)(mNumberOfCpus - 1);
//
@@ -745,11 +762,11 @@ SmmRestoreCpu ( VOID
)
{
- SMM_S3_RESUME_STATE *SmmS3ResumeState;
- IA32_DESCRIPTOR Ia32Idtr;
- IA32_DESCRIPTOR X64Idtr;
- IA32_IDT_GATE_DESCRIPTOR IdtEntryTable[EXCEPTION_VECTOR_NUMBER];
- EFI_STATUS Status;
+ SMM_S3_RESUME_STATE *SmmS3ResumeState;
+ IA32_DESCRIPTOR Ia32Idtr;
+ IA32_DESCRIPTOR X64Idtr;
+ IA32_IDT_GATE_DESCRIPTOR IdtEntryTable[EXCEPTION_VECTOR_NUMBER];
+ EFI_STATUS Status;
DEBUG ((DEBUG_INFO, "SmmRestoreCpu()\n"));
@@ -770,15 +787,15 @@ SmmRestoreCpu ( //
// Save the IA32 IDT Descriptor
//
- AsmReadIdtr ((IA32_DESCRIPTOR *) &Ia32Idtr);
+ AsmReadIdtr ((IA32_DESCRIPTOR *)&Ia32Idtr);
//
// Setup X64 IDT table
//
ZeroMem (IdtEntryTable, sizeof (IA32_IDT_GATE_DESCRIPTOR) * 32);
- X64Idtr.Base = (UINTN) IdtEntryTable;
- X64Idtr.Limit = (UINT16) (sizeof (IA32_IDT_GATE_DESCRIPTOR) * 32 - 1);
- AsmWriteIdtr ((IA32_DESCRIPTOR *) &X64Idtr);
+ X64Idtr.Base = (UINTN)IdtEntryTable;
+ X64Idtr.Limit = (UINT16)(sizeof (IA32_IDT_GATE_DESCRIPTOR) * 32 - 1);
+ AsmWriteIdtr ((IA32_DESCRIPTOR *)&X64Idtr);
//
// Setup the default exception handler
@@ -822,11 +839,11 @@ SmmRestoreCpu ( //
mRestoreSmmConfigurationInS3 = TRUE;
- DEBUG (( DEBUG_INFO, "SMM S3 Return CS = %x\n", SmmS3ResumeState->ReturnCs));
- DEBUG (( DEBUG_INFO, "SMM S3 Return Entry Point = %x\n", SmmS3ResumeState->ReturnEntryPoint));
- DEBUG (( DEBUG_INFO, "SMM S3 Return Context1 = %x\n", SmmS3ResumeState->ReturnContext1));
- DEBUG (( DEBUG_INFO, "SMM S3 Return Context2 = %x\n", SmmS3ResumeState->ReturnContext2));
- DEBUG (( DEBUG_INFO, "SMM S3 Return Stack Pointer = %x\n", SmmS3ResumeState->ReturnStackPointer));
+ DEBUG ((DEBUG_INFO, "SMM S3 Return CS = %x\n", SmmS3ResumeState->ReturnCs));
+ DEBUG ((DEBUG_INFO, "SMM S3 Return Entry Point = %x\n", SmmS3ResumeState->ReturnEntryPoint));
+ DEBUG ((DEBUG_INFO, "SMM S3 Return Context1 = %x\n", SmmS3ResumeState->ReturnContext1));
+ DEBUG ((DEBUG_INFO, "SMM S3 Return Context2 = %x\n", SmmS3ResumeState->ReturnContext2));
+ DEBUG ((DEBUG_INFO, "SMM S3 Return Stack Pointer = %x\n", SmmS3ResumeState->ReturnStackPointer));
//
// If SMM is in 32-bit mode, then use SwitchStack() to resume PEI Phase
@@ -854,7 +871,7 @@ SmmRestoreCpu ( //
// Restore IA32 IDT table
//
- AsmWriteIdtr ((IA32_DESCRIPTOR *) &Ia32Idtr);
+ AsmWriteIdtr ((IA32_DESCRIPTOR *)&Ia32Idtr);
AsmDisablePaging64 (
SmmS3ResumeState->ReturnCs,
(UINT32)SmmS3ResumeState->ReturnEntryPoint,
@@ -882,11 +899,11 @@ InitSmmS3ResumeState ( IN UINT32 Cr3
)
{
- VOID *GuidHob;
- EFI_SMRAM_DESCRIPTOR *SmramDescriptor;
- SMM_S3_RESUME_STATE *SmmS3ResumeState;
- EFI_PHYSICAL_ADDRESS Address;
- EFI_STATUS Status;
+ VOID *GuidHob;
+ EFI_SMRAM_DESCRIPTOR *SmramDescriptor;
+ SMM_S3_RESUME_STATE *SmmS3ResumeState;
+ EFI_PHYSICAL_ADDRESS Address;
+ EFI_STATUS Status;
if (!mAcpiS3Enable) {
return;
@@ -899,10 +916,10 @@ InitSmmS3ResumeState ( "ERROR:%a(): HOB(gEfiAcpiVariableGuid=%g) needed by S3 resume doesn't exist!\n",
__FUNCTION__,
&gEfiAcpiVariableGuid
- ));
+ ));
CpuDeadLoop ();
} else {
- SmramDescriptor = (EFI_SMRAM_DESCRIPTOR *) GET_GUID_HOB_DATA (GuidHob);
+ SmramDescriptor = (EFI_SMRAM_DESCRIPTOR *)GET_GUID_HOB_DATA (GuidHob);
DEBUG ((DEBUG_INFO, "SMM S3 SMRAM Structure = %x\n", SmramDescriptor));
DEBUG ((DEBUG_INFO, "SMM S3 Structure = %x\n", SmramDescriptor->CpuStart));
@@ -910,7 +927,7 @@ InitSmmS3ResumeState ( SmmS3ResumeState = (SMM_S3_RESUME_STATE *)(UINTN)SmramDescriptor->CpuStart;
ZeroMem (SmmS3ResumeState, sizeof (SMM_S3_RESUME_STATE));
- mSmmS3ResumeState = SmmS3ResumeState;
+ mSmmS3ResumeState = SmmS3ResumeState;
SmmS3ResumeState->Smst = (EFI_PHYSICAL_ADDRESS)(UINTN)gSmst;
SmmS3ResumeState->SmmS3ResumeEntryPoint = (EFI_PHYSICAL_ADDRESS)(UINTN)SmmRestoreCpu;
@@ -928,6 +945,7 @@ InitSmmS3ResumeState ( if (sizeof (UINTN) == sizeof (UINT64)) {
SmmS3ResumeState->Signature = SMM_S3_RESUME_SMM_64;
}
+
if (sizeof (UINTN) == sizeof (UINT32)) {
SmmS3ResumeState->Signature = SMM_S3_RESUME_SMM_32;
}
@@ -950,7 +968,7 @@ InitSmmS3ResumeState ( &Address
);
ASSERT_EFI_ERROR (Status);
- mApHltLoopCode = (UINT8 *) (UINTN) Address;
+ mApHltLoopCode = (UINT8 *)(UINTN)Address;
}
/**
@@ -963,22 +981,22 @@ InitSmmS3ResumeState ( **/
VOID
CopyRegisterTable (
- IN CPU_REGISTER_TABLE *DestinationRegisterTableList,
- IN CPU_REGISTER_TABLE *SourceRegisterTableList,
- IN UINT32 NumberOfCpus
+ IN CPU_REGISTER_TABLE *DestinationRegisterTableList,
+ IN CPU_REGISTER_TABLE *SourceRegisterTableList,
+ IN UINT32 NumberOfCpus
)
{
- UINTN Index;
- CPU_REGISTER_TABLE_ENTRY *RegisterTableEntry;
+ UINTN Index;
+ CPU_REGISTER_TABLE_ENTRY *RegisterTableEntry;
CopyMem (DestinationRegisterTableList, SourceRegisterTableList, NumberOfCpus * sizeof (CPU_REGISTER_TABLE));
for (Index = 0; Index < NumberOfCpus; Index++) {
if (DestinationRegisterTableList[Index].TableLength != 0) {
DestinationRegisterTableList[Index].AllocatedSize = DestinationRegisterTableList[Index].TableLength * sizeof (CPU_REGISTER_TABLE_ENTRY);
- RegisterTableEntry = AllocateCopyPool (
- DestinationRegisterTableList[Index].AllocatedSize,
- (VOID *)(UINTN)SourceRegisterTableList[Index].RegisterTableEntry
- );
+ RegisterTableEntry = AllocateCopyPool (
+ DestinationRegisterTableList[Index].AllocatedSize,
+ (VOID *)(UINTN)SourceRegisterTableList[Index].RegisterTableEntry
+ );
ASSERT (RegisterTableEntry != NULL);
DestinationRegisterTableList[Index].RegisterTableEntry = (EFI_PHYSICAL_ADDRESS)(UINTN)RegisterTableEntry;
}
@@ -996,11 +1014,11 @@ CopyRegisterTable ( **/
BOOLEAN
IsRegisterTableEmpty (
- IN CPU_REGISTER_TABLE *RegisterTable,
- IN UINT32 NumberOfCpus
+ IN CPU_REGISTER_TABLE *RegisterTable,
+ IN UINT32 NumberOfCpus
)
{
- UINTN Index;
+ UINTN Index;
if (RegisterTable != NULL) {
for (Index = 0; Index < NumberOfCpus; Index++) {
@@ -1022,11 +1040,11 @@ IsRegisterTableEmpty ( **/
VOID
CopyCpuFeatureInitDatatoSmram (
- IN OUT CPU_FEATURE_INIT_DATA *CpuFeatureInitDataDst,
- IN CPU_FEATURE_INIT_DATA *CpuFeatureInitDataSrc
+ IN OUT CPU_FEATURE_INIT_DATA *CpuFeatureInitDataDst,
+ IN CPU_FEATURE_INIT_DATA *CpuFeatureInitDataSrc
)
{
- CPU_STATUS_INFORMATION *CpuStatus;
+ CPU_STATUS_INFORMATION *CpuStatus;
if (!IsRegisterTableEmpty ((CPU_REGISTER_TABLE *)(UINTN)CpuFeatureInitDataSrc->PreSmmInitRegisterTable, mAcpiCpuData.NumberOfCpus)) {
CpuFeatureInitDataDst->PreSmmInitRegisterTable = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocatePool (mAcpiCpuData.NumberOfCpus * sizeof (CPU_REGISTER_TABLE));
@@ -1055,25 +1073,25 @@ CopyCpuFeatureInitDatatoSmram ( if (CpuFeatureInitDataSrc->CpuStatus.ThreadCountPerPackage != 0) {
CpuStatus->ThreadCountPerPackage = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocateCopyPool (
- sizeof (UINT32) * CpuStatus->PackageCount,
- (UINT32 *)(UINTN)CpuFeatureInitDataSrc->CpuStatus.ThreadCountPerPackage
- );
+ sizeof (UINT32) * CpuStatus->PackageCount,
+ (UINT32 *)(UINTN)CpuFeatureInitDataSrc->CpuStatus.ThreadCountPerPackage
+ );
ASSERT (CpuStatus->ThreadCountPerPackage != 0);
}
if (CpuFeatureInitDataSrc->CpuStatus.ThreadCountPerCore != 0) {
CpuStatus->ThreadCountPerCore = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocateCopyPool (
- sizeof (UINT8) * (CpuStatus->PackageCount * CpuStatus->MaxCoreCount),
- (UINT32 *)(UINTN)CpuFeatureInitDataSrc->CpuStatus.ThreadCountPerCore
- );
+ sizeof (UINT8) * (CpuStatus->PackageCount * CpuStatus->MaxCoreCount),
+ (UINT32 *)(UINTN)CpuFeatureInitDataSrc->CpuStatus.ThreadCountPerCore
+ );
ASSERT (CpuStatus->ThreadCountPerCore != 0);
}
if (CpuFeatureInitDataSrc->ApLocation != 0) {
CpuFeatureInitDataDst->ApLocation = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocateCopyPool (
- mAcpiCpuData.NumberOfCpus * sizeof (EFI_CPU_PHYSICAL_LOCATION),
- (EFI_CPU_PHYSICAL_LOCATION *)(UINTN)CpuFeatureInitDataSrc->ApLocation
- );
+ mAcpiCpuData.NumberOfCpus * sizeof (EFI_CPU_PHYSICAL_LOCATION),
+ (EFI_CPU_PHYSICAL_LOCATION *)(UINTN)CpuFeatureInitDataSrc->ApLocation
+ );
ASSERT (CpuFeatureInitDataDst->ApLocation != 0);
}
}
@@ -1087,13 +1105,13 @@ GetAcpiCpuData ( VOID
)
{
- ACPI_CPU_DATA *AcpiCpuData;
- IA32_DESCRIPTOR *Gdtr;
- IA32_DESCRIPTOR *Idtr;
- VOID *GdtForAp;
- VOID *IdtForAp;
- VOID *MachineCheckHandlerForAp;
- CPU_STATUS_INFORMATION *CpuStatus;
+ ACPI_CPU_DATA *AcpiCpuData;
+ IA32_DESCRIPTOR *Gdtr;
+ IA32_DESCRIPTOR *Idtr;
+ VOID *GdtForAp;
+ VOID *IdtForAp;
+ VOID *MachineCheckHandlerForAp;
+ CPU_STATUS_INFORMATION *CpuStatus;
if (!mAcpiS3Enable) {
return;
@@ -1140,15 +1158,15 @@ GetAcpiCpuData ( GdtForAp = AllocatePool ((Gdtr->Limit + 1) + (Idtr->Limit + 1) + mAcpiCpuData.ApMachineCheckHandlerSize);
ASSERT (GdtForAp != NULL);
- IdtForAp = (VOID *) ((UINTN)GdtForAp + (Gdtr->Limit + 1));
- MachineCheckHandlerForAp = (VOID *) ((UINTN)IdtForAp + (Idtr->Limit + 1));
+ IdtForAp = (VOID *)((UINTN)GdtForAp + (Gdtr->Limit + 1));
+ MachineCheckHandlerForAp = (VOID *)((UINTN)IdtForAp + (Idtr->Limit + 1));
CopyMem (GdtForAp, (VOID *)Gdtr->Base, Gdtr->Limit + 1);
CopyMem (IdtForAp, (VOID *)Idtr->Base, Idtr->Limit + 1);
CopyMem (MachineCheckHandlerForAp, (VOID *)(UINTN)mAcpiCpuData.ApMachineCheckHandlerBase, mAcpiCpuData.ApMachineCheckHandlerSize);
- Gdtr->Base = (UINTN)GdtForAp;
- Idtr->Base = (UINTN)IdtForAp;
+ Gdtr->Base = (UINTN)GdtForAp;
+ Idtr->Base = (UINTN)IdtForAp;
mAcpiCpuData.ApMachineCheckHandlerBase = (EFI_PHYSICAL_ADDRESS)(UINTN)MachineCheckHandlerForAp;
ZeroMem (&mAcpiCpuData.CpuFeatureInitData, sizeof (CPU_FEATURE_INIT_DATA));
@@ -1175,7 +1193,7 @@ GetAcpiCpuData ( );
ASSERT (mCpuFlags.PackageSemaphoreCount != NULL);
- InitializeSpinLock((SPIN_LOCK*) &mCpuFlags.MemoryMappedLock);
+ InitializeSpinLock ((SPIN_LOCK *)&mCpuFlags.MemoryMappedLock);
}
}
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c index c9138a531a..5d624f8e9e 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c @@ -38,15 +38,15 @@ EFI_SMM_CPU_SERVICE_PROTOCOL mSmmCpuService = { EFI_STATUS
EFIAPI
SmmGetProcessorInfo (
- IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This,
- IN UINTN ProcessorNumber,
- OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer
+ IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This,
+ IN UINTN ProcessorNumber,
+ OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer
)
{
//
// Check parameter
//
- if (ProcessorNumber >= mMaxNumberOfCpus || ProcessorInfoBuffer == NULL) {
+ if ((ProcessorNumber >= mMaxNumberOfCpus) || (ProcessorInfoBuffer == NULL)) {
return EFI_INVALID_PARAMETER;
}
@@ -75,8 +75,8 @@ SmmGetProcessorInfo ( EFI_STATUS
EFIAPI
SmmSwitchBsp (
- IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This,
- IN UINTN ProcessorNumber
+ IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This,
+ IN UINTN ProcessorNumber
)
{
//
@@ -90,8 +90,9 @@ SmmSwitchBsp ( return EFI_NOT_FOUND;
}
- if (gSmmCpuPrivate->Operation[ProcessorNumber] != SmmCpuNone ||
- gSmst->CurrentlyExecutingCpu == ProcessorNumber) {
+ if ((gSmmCpuPrivate->Operation[ProcessorNumber] != SmmCpuNone) ||
+ (gSmst->CurrentlyExecutingCpu == ProcessorNumber))
+ {
return EFI_UNSUPPORTED;
}
@@ -132,7 +133,7 @@ SmmAddProcessor ( //
// Check parameter
//
- if (ProcessorNumber == NULL || ProcessorId == INVALID_APIC_ID) {
+ if ((ProcessorNumber == NULL) || (ProcessorId == INVALID_APIC_ID)) {
return EFI_INVALID_PARAMETER;
}
@@ -151,10 +152,11 @@ SmmAddProcessor ( // of the APIC ID to SMBASE.
//
for (Index = 0; Index < mMaxNumberOfCpus; Index++) {
- if (mCpuHotPlugData.ApicId[Index] == ProcessorId &&
- gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId == INVALID_APIC_ID) {
+ if ((mCpuHotPlugData.ApicId[Index] == ProcessorId) &&
+ (gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId == INVALID_APIC_ID))
+ {
gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId = ProcessorId;
- gSmmCpuPrivate->ProcessorInfo[Index].StatusFlag = 0;
+ gSmmCpuPrivate->ProcessorInfo[Index].StatusFlag = 0;
GetProcessorLocationByApicId (
(UINT32)ProcessorId,
&gSmmCpuPrivate->ProcessorInfo[Index].Location.Package,
@@ -162,7 +164,7 @@ SmmAddProcessor ( &gSmmCpuPrivate->ProcessorInfo[Index].Location.Thread
);
- *ProcessorNumber = Index;
+ *ProcessorNumber = Index;
gSmmCpuPrivate->Operation[Index] = SmmCpuAdd;
return EFI_SUCCESS;
}
@@ -197,8 +199,9 @@ SmmRemoveProcessor ( //
// Check parameter
//
- if (ProcessorNumber >= mMaxNumberOfCpus ||
- gSmmCpuPrivate->ProcessorInfo[ProcessorNumber].ProcessorId == INVALID_APIC_ID) {
+ if ((ProcessorNumber >= mMaxNumberOfCpus) ||
+ (gSmmCpuPrivate->ProcessorInfo[ProcessorNumber].ProcessorId == INVALID_APIC_ID))
+ {
return EFI_INVALID_PARAMETER;
}
@@ -214,7 +217,7 @@ SmmRemoveProcessor ( }
gSmmCpuPrivate->ProcessorInfo[ProcessorNumber].ProcessorId = INVALID_APIC_ID;
- mCpuHotPlugData.ApicId[ProcessorNumber] = INVALID_APIC_ID;
+ mCpuHotPlugData.ApicId[ProcessorNumber] = INVALID_APIC_ID;
//
// Removal of the processor from the CPU list is pending until all SMI handlers are finished
@@ -237,12 +240,12 @@ SmmRemoveProcessor ( EFI_STATUS
EFIAPI
SmmWhoAmI (
- IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This,
- OUT UINTN *ProcessorNumber
+ IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This,
+ OUT UINTN *ProcessorNumber
)
{
- UINTN Index;
- UINT64 ApicId;
+ UINTN Index;
+ UINT64 ApicId;
//
// Check parameter
@@ -259,6 +262,7 @@ SmmWhoAmI ( return EFI_SUCCESS;
}
}
+
//
// This should not happen
//
@@ -276,15 +280,15 @@ SmmCpuUpdate ( VOID
)
{
- UINTN Index;
+ UINTN Index;
//
// Handle pending BSP switch operations
//
for (Index = 0; Index < mMaxNumberOfCpus; Index++) {
if (gSmmCpuPrivate->Operation[Index] == SmmCpuSwitchBsp) {
- gSmmCpuPrivate->Operation[Index] = SmmCpuNone;
- mSmmMpSyncData->SwitchBsp = TRUE;
+ gSmmCpuPrivate->Operation[Index] = SmmCpuNone;
+ mSmmMpSyncData->SwitchBsp = TRUE;
mSmmMpSyncData->CandidateBsp[Index] = TRUE;
}
}
@@ -330,10 +334,10 @@ SmmCpuUpdate ( EFI_STATUS
EFIAPI
SmmRegisterExceptionHandler (
- IN EFI_SMM_CPU_SERVICE_PROTOCOL *This,
- IN EFI_EXCEPTION_TYPE ExceptionType,
- IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
- )
+ IN EFI_SMM_CPU_SERVICE_PROTOCOL *This,
+ IN EFI_EXCEPTION_TYPE ExceptionType,
+ IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
+ )
{
return RegisterCpuInterruptHandler (ExceptionType, InterruptHandler);
}
@@ -352,7 +356,7 @@ InitializeSmmCpuServices ( IN EFI_HANDLE Handle
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
Status = gSmst->SmmInstallProtocolInterface (
&Handle,
@@ -363,4 +367,3 @@ InitializeSmmCpuServices ( ASSERT_EFI_ERROR (Status);
return Status;
}
-
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.h b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.h index 98b0feb42c..8847dbb851 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.h +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.h @@ -38,9 +38,9 @@ typedef enum { EFI_STATUS
EFIAPI
SmmGetProcessorInfo (
- IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This,
- IN UINTN ProcessorNumber,
- OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer
+ IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This,
+ IN UINTN ProcessorNumber,
+ OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer
);
/**
@@ -57,8 +57,8 @@ SmmGetProcessorInfo ( EFI_STATUS
EFIAPI
SmmSwitchBsp (
- IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This,
- IN UINTN ProcessorNumber
+ IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This,
+ IN UINTN ProcessorNumber
);
/**
@@ -115,8 +115,8 @@ SmmRemoveProcessor ( EFI_STATUS
EFIAPI
SmmWhoAmI (
- IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This,
- OUT UINTN *ProcessorNumber
+ IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This,
+ OUT UINTN *ProcessorNumber
);
/**
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c index 9c8e2d15ac..8ec8790c05 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c @@ -36,13 +36,13 @@ EnableCet ( **/
VOID
GetPageTable (
- OUT UINTN *Base,
- OUT BOOLEAN *FiveLevels OPTIONAL
+ OUT UINTN *Base,
+ OUT BOOLEAN *FiveLevels OPTIONAL
)
{
*Base = ((mInternalCr3 == 0) ?
- (AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64) :
- mInternalCr3);
+ (AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64) :
+ mInternalCr3);
if (FiveLevels != NULL) {
*FiveLevels = FALSE;
}
@@ -59,9 +59,9 @@ SmmInitPageTable ( VOID
)
{
- UINTN PageFaultHandlerHookAddress;
- IA32_IDT_GATE_DESCRIPTOR *IdtEntry;
- EFI_STATUS Status;
+ UINTN PageFaultHandlerHookAddress;
+ IA32_IDT_GATE_DESCRIPTOR *IdtEntry;
+ EFI_STATUS Status;
//
// Initialize spin lock
@@ -72,18 +72,19 @@ SmmInitPageTable ( if (FeaturePcdGet (PcdCpuSmmProfileEnable) ||
HEAP_GUARD_NONSTOP_MODE ||
- NULL_DETECTION_NONSTOP_MODE) {
+ NULL_DETECTION_NONSTOP_MODE)
+ {
//
// Set own Page Fault entry instead of the default one, because SMM Profile
// feature depends on IRET instruction to do Single Step
//
PageFaultHandlerHookAddress = (UINTN)PageFaultIdtHandlerSmmProfile;
- IdtEntry = (IA32_IDT_GATE_DESCRIPTOR *) gcSmiIdtr.Base;
- IdtEntry += EXCEPT_IA32_PAGE_FAULT;
- IdtEntry->Bits.OffsetLow = (UINT16)PageFaultHandlerHookAddress;
- IdtEntry->Bits.Reserved_0 = 0;
- IdtEntry->Bits.GateType = IA32_IDT_GATE_TYPE_INTERRUPT_32;
- IdtEntry->Bits.OffsetHigh = (UINT16)(PageFaultHandlerHookAddress >> 16);
+ IdtEntry = (IA32_IDT_GATE_DESCRIPTOR *)gcSmiIdtr.Base;
+ IdtEntry += EXCEPT_IA32_PAGE_FAULT;
+ IdtEntry->Bits.OffsetLow = (UINT16)PageFaultHandlerHookAddress;
+ IdtEntry->Bits.Reserved_0 = 0;
+ IdtEntry->Bits.GateType = IA32_IDT_GATE_TYPE_INTERRUPT_32;
+ IdtEntry->Bits.OffsetHigh = (UINT16)(PageFaultHandlerHookAddress >> 16);
} else {
//
// Register SMM Page Fault Handler
@@ -98,6 +99,7 @@ SmmInitPageTable ( if (FeaturePcdGet (PcdCpuSmmStackGuard)) {
InitializeIDTSmmStackGuard ();
}
+
return Gen4GPageTable (TRUE);
}
@@ -124,13 +126,13 @@ SmiDefaultPFHandler ( VOID
EFIAPI
SmiPFHandler (
- IN EFI_EXCEPTION_TYPE InterruptType,
- IN EFI_SYSTEM_CONTEXT SystemContext
+ IN EFI_EXCEPTION_TYPE InterruptType,
+ IN EFI_SYSTEM_CONTEXT SystemContext
)
{
- UINTN PFAddress;
- UINTN GuardPageAddress;
- UINTN CpuIndex;
+ UINTN PFAddress;
+ UINTN GuardPageAddress;
+ UINTN CpuIndex;
ASSERT (InterruptType == EXCEPT_IA32_PAGE_FAULT);
@@ -143,25 +145,27 @@ SmiPFHandler ( // or SMM page protection violation.
//
if ((PFAddress >= mCpuHotPlugData.SmrrBase) &&
- (PFAddress < (mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize))) {
+ (PFAddress < (mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize)))
+ {
DumpCpuContext (InterruptType, SystemContext);
- CpuIndex = GetCpuIndex ();
+ CpuIndex = GetCpuIndex ();
GuardPageAddress = (mSmmStackArrayBase + EFI_PAGE_SIZE + CpuIndex * mSmmStackSize);
if ((FeaturePcdGet (PcdCpuSmmStackGuard)) &&
(PFAddress >= GuardPageAddress) &&
- (PFAddress < (GuardPageAddress + EFI_PAGE_SIZE))) {
+ (PFAddress < (GuardPageAddress + EFI_PAGE_SIZE)))
+ {
DEBUG ((DEBUG_ERROR, "SMM stack overflow!\n"));
} else {
if ((SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_ID) != 0) {
DEBUG ((DEBUG_ERROR, "SMM exception at execution (0x%x)\n", PFAddress));
DEBUG_CODE (
DumpModuleInfoByIp (*(UINTN *)(UINTN)SystemContext.SystemContextIa32->Esp);
- );
+ );
} else {
DEBUG ((DEBUG_ERROR, "SMM exception at access (0x%x)\n", PFAddress));
DEBUG_CODE (
DumpModuleInfoByIp ((UINTN)SystemContext.SystemContextIa32->Eip);
- );
+ );
}
if (HEAP_GUARD_NONSTOP_MODE) {
@@ -169,6 +173,7 @@ SmiPFHandler ( goto Exit;
}
}
+
CpuDeadLoop ();
goto Exit;
}
@@ -177,13 +182,14 @@ SmiPFHandler ( // If a page fault occurs in non-SMRAM range.
//
if ((PFAddress < mCpuHotPlugData.SmrrBase) ||
- (PFAddress >= mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize)) {
+ (PFAddress >= mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize))
+ {
if ((SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_ID) != 0) {
DumpCpuContext (InterruptType, SystemContext);
DEBUG ((DEBUG_ERROR, "Code executed on IP(0x%x) out of SMM range after SMM is locked!\n", PFAddress));
DEBUG_CODE (
DumpModuleInfoByIp (*(UINTN *)(UINTN)SystemContext.SystemContextIa32->Esp);
- );
+ );
CpuDeadLoop ();
goto Exit;
}
@@ -191,13 +197,14 @@ SmiPFHandler ( //
// If NULL pointer was just accessed
//
- if ((PcdGet8 (PcdNullPointerDetectionPropertyMask) & BIT1) != 0 &&
- (PFAddress < EFI_PAGE_SIZE)) {
+ if (((PcdGet8 (PcdNullPointerDetectionPropertyMask) & BIT1) != 0) &&
+ (PFAddress < EFI_PAGE_SIZE))
+ {
DumpCpuContext (InterruptType, SystemContext);
DEBUG ((DEBUG_ERROR, "!!! NULL pointer access !!!\n"));
DEBUG_CODE (
DumpModuleInfoByIp ((UINTN)SystemContext.SystemContextIa32->Eip);
- );
+ );
if (NULL_DETECTION_NONSTOP_MODE) {
GuardPagePFHandler (SystemContext.SystemContextIa32->ExceptionData);
@@ -213,7 +220,7 @@ SmiPFHandler ( DEBUG ((DEBUG_ERROR, "Access SMM communication forbidden address (0x%x)!\n", PFAddress));
DEBUG_CODE (
DumpModuleInfoByIp ((UINTN)SystemContext.SystemContextIa32->Eip);
- );
+ );
CpuDeadLoop ();
goto Exit;
}
@@ -241,15 +248,15 @@ SetPageTableAttributes ( VOID
)
{
- UINTN Index2;
- UINTN Index3;
- UINT64 *L1PageTable;
- UINT64 *L2PageTable;
- UINT64 *L3PageTable;
- UINTN PageTableBase;
- BOOLEAN IsSplitted;
- BOOLEAN PageTableSplitted;
- BOOLEAN CetEnabled;
+ UINTN Index2;
+ UINTN Index3;
+ UINT64 *L1PageTable;
+ UINT64 *L2PageTable;
+ UINT64 *L3PageTable;
+ UINTN PageTableBase;
+ BOOLEAN IsSplitted;
+ BOOLEAN PageTableSplitted;
+ BOOLEAN CetEnabled;
//
// Don't mark page table to read-only if heap guard is enabled.
@@ -259,7 +266,7 @@ SetPageTableAttributes ( //
if ((PcdGet8 (PcdHeapGuardPropertyMask) & (BIT3 | BIT2)) != 0) {
DEBUG ((DEBUG_INFO, "Don't mark page table to read-only as heap guard is enabled\n"));
- return ;
+ return;
}
//
@@ -267,7 +274,7 @@ SetPageTableAttributes ( //
if (FeaturePcdGet (PcdCpuSmmProfileEnable)) {
DEBUG ((DEBUG_INFO, "Don't mark page table to read-only as SMM profile is enabled\n"));
- return ;
+ return;
}
DEBUG ((DEBUG_INFO, "SetPageTableAttributes\n"));
@@ -276,14 +283,15 @@ SetPageTableAttributes ( // Disable write protection, because we need mark page table to be write protected.
// We need *write* page table memory, to mark itself to be *read only*.
//
- CetEnabled = ((AsmReadCr4() & CR4_CET_ENABLE) != 0) ? TRUE : FALSE;
+ CetEnabled = ((AsmReadCr4 () & CR4_CET_ENABLE) != 0) ? TRUE : FALSE;
if (CetEnabled) {
//
// CET must be disabled if WP is disabled.
//
- DisableCet();
+ DisableCet ();
}
- AsmWriteCr0 (AsmReadCr0() & ~CR0_WP);
+
+ AsmWriteCr0 (AsmReadCr0 () & ~CR0_WP);
do {
DEBUG ((DEBUG_INFO, "Start...\n"));
@@ -304,15 +312,17 @@ SetPageTableAttributes ( SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)(UINTN)L2PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted);
PageTableSplitted = (PageTableSplitted || IsSplitted);
- for (Index2 = 0; Index2 < SIZE_4KB/sizeof(UINT64); Index2++) {
+ for (Index2 = 0; Index2 < SIZE_4KB/sizeof (UINT64); Index2++) {
if ((L2PageTable[Index2] & IA32_PG_PS) != 0) {
// 2M
continue;
}
+
L1PageTable = (UINT64 *)(UINTN)(L2PageTable[Index2] & ~mAddressEncMask & PAGING_4K_ADDRESS_MASK_64);
if (L1PageTable == NULL) {
continue;
}
+
SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)(UINTN)L1PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted);
PageTableSplitted = (PageTableSplitted || IsSplitted);
}
@@ -322,15 +332,15 @@ SetPageTableAttributes ( //
// Enable write protection, after page table updated.
//
- AsmWriteCr0 (AsmReadCr0() | CR0_WP);
+ AsmWriteCr0 (AsmReadCr0 () | CR0_WP);
if (CetEnabled) {
//
// re-enable CET.
//
- EnableCet();
+ EnableCet ();
}
- return ;
+ return;
}
/**
@@ -343,7 +353,7 @@ SaveCr2 ( OUT UINTN *Cr2
)
{
- return ;
+ return;
}
/**
@@ -356,7 +366,7 @@ RestoreCr2 ( IN UINTN Cr2
)
{
- return ;
+ return;
}
/**
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Semaphore.c b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Semaphore.c index 31ee067ad6..a9fcc89dda 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Semaphore.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Semaphore.c @@ -32,7 +32,7 @@ SemaphoreHook ( mRebasedFlag = RebasedFlag;
- CpuState = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET);
+ CpuState = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET);
mSmmRelocationOriginalAddress = (UINTN)HookReturnFromSmm (
CpuIndex,
CpuState,
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmFuncsArch.c b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmFuncsArch.c index ef277349d4..6c48a53f67 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmFuncsArch.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmFuncsArch.c @@ -8,18 +8,18 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include "PiSmmCpuDxeSmm.h"
-extern UINT64 gTaskGateDescriptor;
+extern UINT64 gTaskGateDescriptor;
-EFI_PHYSICAL_ADDRESS mGdtBuffer;
-UINTN mGdtBufferSize;
+EFI_PHYSICAL_ADDRESS mGdtBuffer;
+UINTN mGdtBufferSize;
-extern BOOLEAN mCetSupported;
-extern UINTN mSmmShadowStackSize;
+extern BOOLEAN mCetSupported;
+extern UINTN mSmmShadowStackSize;
-X86_ASSEMBLY_PATCH_LABEL mPatchCetPl0Ssp;
-X86_ASSEMBLY_PATCH_LABEL mPatchCetInterruptSsp;
-UINT32 mCetPl0Ssp;
-UINT32 mCetInterruptSsp;
+X86_ASSEMBLY_PATCH_LABEL mPatchCetPl0Ssp;
+X86_ASSEMBLY_PATCH_LABEL mPatchCetInterruptSsp;
+UINT32 mCetPl0Ssp;
+UINT32 mCetInterruptSsp;
/**
Initialize IDT for SMM Stack Guard.
@@ -38,8 +38,8 @@ InitializeIDTSmmStackGuard ( // is a Task Gate Descriptor so that when a Page Fault Exception occurs,
// the processors can use a known good stack in case stack is ran out.
//
- IdtGate = (IA32_IDT_GATE_DESCRIPTOR *)gcSmiIdtr.Base;
- IdtGate += EXCEPT_IA32_PAGE_FAULT;
+ IdtGate = (IA32_IDT_GATE_DESCRIPTOR *)gcSmiIdtr.Base;
+ IdtGate += EXCEPT_IA32_PAGE_FAULT;
IdtGate->Uint64 = gTaskGateDescriptor;
}
@@ -58,13 +58,13 @@ InitGdt ( OUT UINTN *GdtStepSize
)
{
- UINTN Index;
- IA32_SEGMENT_DESCRIPTOR *GdtDescriptor;
- UINTN TssBase;
- UINTN GdtTssTableSize;
- UINT8 *GdtTssTables;
- UINTN GdtTableStepSize;
- UINTN InterruptShadowStack;
+ UINTN Index;
+ IA32_SEGMENT_DESCRIPTOR *GdtDescriptor;
+ UINTN TssBase;
+ UINTN GdtTssTableSize;
+ UINT8 *GdtTssTables;
+ UINTN GdtTableStepSize;
+ UINTN InterruptShadowStack;
if (FeaturePcdGet (PcdCpuSmmStackGuard)) {
//
@@ -79,46 +79,46 @@ InitGdt ( gcSmiGdtr.Limit += (UINT16)(2 * sizeof (IA32_SEGMENT_DESCRIPTOR));
GdtTssTableSize = (gcSmiGdtr.Limit + 1 + TSS_SIZE + EXCEPTION_TSS_SIZE + 7) & ~7; // 8 bytes aligned
- mGdtBufferSize = GdtTssTableSize * gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus;
+ mGdtBufferSize = GdtTssTableSize * gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus;
//
// IA32 Stack Guard need use task switch to switch stack that need
// write GDT and TSS, so AllocateCodePages() could not be used here
// as code pages will be set to RO.
//
- GdtTssTables = (UINT8*)AllocatePages (EFI_SIZE_TO_PAGES (mGdtBufferSize));
+ GdtTssTables = (UINT8 *)AllocatePages (EFI_SIZE_TO_PAGES (mGdtBufferSize));
ASSERT (GdtTssTables != NULL);
- mGdtBuffer = (UINTN)GdtTssTables;
+ mGdtBuffer = (UINTN)GdtTssTables;
GdtTableStepSize = GdtTssTableSize;
for (Index = 0; Index < gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus; Index++) {
- CopyMem (GdtTssTables + GdtTableStepSize * Index, (VOID*)(UINTN)gcSmiGdtr.Base, gcSmiGdtr.Limit + 1 + TSS_SIZE + EXCEPTION_TSS_SIZE);
+ CopyMem (GdtTssTables + GdtTableStepSize * Index, (VOID *)(UINTN)gcSmiGdtr.Base, gcSmiGdtr.Limit + 1 + TSS_SIZE + EXCEPTION_TSS_SIZE);
//
// Fixup TSS descriptors
//
- TssBase = (UINTN)(GdtTssTables + GdtTableStepSize * Index + gcSmiGdtr.Limit + 1);
- GdtDescriptor = (IA32_SEGMENT_DESCRIPTOR *)(TssBase) - 2;
- GdtDescriptor->Bits.BaseLow = (UINT16)TssBase;
- GdtDescriptor->Bits.BaseMid = (UINT8)(TssBase >> 16);
+ TssBase = (UINTN)(GdtTssTables + GdtTableStepSize * Index + gcSmiGdtr.Limit + 1);
+ GdtDescriptor = (IA32_SEGMENT_DESCRIPTOR *)(TssBase) - 2;
+ GdtDescriptor->Bits.BaseLow = (UINT16)TssBase;
+ GdtDescriptor->Bits.BaseMid = (UINT8)(TssBase >> 16);
GdtDescriptor->Bits.BaseHigh = (UINT8)(TssBase >> 24);
TssBase += TSS_SIZE;
GdtDescriptor++;
- GdtDescriptor->Bits.BaseLow = (UINT16)TssBase;
- GdtDescriptor->Bits.BaseMid = (UINT8)(TssBase >> 16);
+ GdtDescriptor->Bits.BaseLow = (UINT16)TssBase;
+ GdtDescriptor->Bits.BaseMid = (UINT8)(TssBase >> 16);
GdtDescriptor->Bits.BaseHigh = (UINT8)(TssBase >> 24);
//
// Fixup TSS segments
//
// ESP as known good stack
//
- *(UINTN *)(TssBase + TSS_IA32_ESP_OFFSET) = mSmmStackArrayBase + EFI_PAGE_SIZE + Index * mSmmStackSize;
+ *(UINTN *)(TssBase + TSS_IA32_ESP_OFFSET) = mSmmStackArrayBase + EFI_PAGE_SIZE + Index * mSmmStackSize;
*(UINT32 *)(TssBase + TSS_IA32_CR3_OFFSET) = Cr3;
//
// Setup ShadowStack for stack switch
//
if ((PcdGet32 (PcdControlFlowEnforcementPropertyMask) != 0) && mCetSupported) {
- InterruptShadowStack = (UINTN)(mSmmStackArrayBase + mSmmStackSize + EFI_PAGES_TO_SIZE (1) - sizeof(UINT64) + (mSmmStackSize + mSmmShadowStackSize) * Index);
+ InterruptShadowStack = (UINTN)(mSmmStackArrayBase + mSmmStackSize + EFI_PAGES_TO_SIZE (1) - sizeof (UINT64) + (mSmmStackSize + mSmmShadowStackSize) * Index);
*(UINT32 *)(TssBase + TSS_IA32_SSP_OFFSET) = (UINT32)InterruptShadowStack;
}
}
@@ -127,14 +127,14 @@ InitGdt ( // Just use original table, AllocatePage and copy them here to make sure GDTs are covered in page memory.
//
GdtTssTableSize = gcSmiGdtr.Limit + 1;
- mGdtBufferSize = GdtTssTableSize * gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus;
- GdtTssTables = (UINT8*)AllocateCodePages (EFI_SIZE_TO_PAGES (mGdtBufferSize));
+ mGdtBufferSize = GdtTssTableSize * gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus;
+ GdtTssTables = (UINT8 *)AllocateCodePages (EFI_SIZE_TO_PAGES (mGdtBufferSize));
ASSERT (GdtTssTables != NULL);
- mGdtBuffer = (UINTN)GdtTssTables;
+ mGdtBuffer = (UINTN)GdtTssTables;
GdtTableStepSize = GdtTssTableSize;
for (Index = 0; Index < gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus; Index++) {
- CopyMem (GdtTssTables + GdtTableStepSize * Index, (VOID*)(UINTN)gcSmiGdtr.Base, gcSmiGdtr.Limit + 1);
+ CopyMem (GdtTssTables + GdtTableStepSize * Index, (VOID *)(UINTN)gcSmiGdtr.Base, gcSmiGdtr.Limit + 1);
}
}
@@ -181,24 +181,24 @@ InitShadowStack ( IN VOID *ShadowStack
)
{
- UINTN SmmShadowStackSize;
+ UINTN SmmShadowStackSize;
if ((PcdGet32 (PcdControlFlowEnforcementPropertyMask) != 0) && mCetSupported) {
SmmShadowStackSize = EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuSmmShadowStackSize)));
if (FeaturePcdGet (PcdCpuSmmStackGuard)) {
SmmShadowStackSize += EFI_PAGES_TO_SIZE (2);
}
- mCetPl0Ssp = (UINT32)((UINTN)ShadowStack + SmmShadowStackSize - sizeof(UINT64));
+
+ mCetPl0Ssp = (UINT32)((UINTN)ShadowStack + SmmShadowStackSize - sizeof (UINT64));
PatchInstructionX86 (mPatchCetPl0Ssp, mCetPl0Ssp, 4);
DEBUG ((DEBUG_INFO, "mCetPl0Ssp - 0x%x\n", mCetPl0Ssp));
DEBUG ((DEBUG_INFO, "ShadowStack - 0x%x\n", ShadowStack));
DEBUG ((DEBUG_INFO, " SmmShadowStackSize - 0x%x\n", SmmShadowStackSize));
if (FeaturePcdGet (PcdCpuSmmStackGuard)) {
- mCetInterruptSsp = (UINT32)((UINTN)ShadowStack + EFI_PAGES_TO_SIZE(1) - sizeof(UINT64));
+ mCetInterruptSsp = (UINT32)((UINTN)ShadowStack + EFI_PAGES_TO_SIZE (1) - sizeof (UINT64));
PatchInstructionX86 (mPatchCetInterruptSsp, mCetInterruptSsp, 4);
DEBUG ((DEBUG_INFO, "mCetInterruptSsp - 0x%x\n", mCetInterruptSsp));
}
}
}
-
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmProfileArch.c b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmProfileArch.c index e83031fc01..bba4a6f058 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmProfileArch.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmProfileArch.c @@ -20,7 +20,7 @@ InitSmmS3Cr3 ( {
mSmmS3ResumeState->SmmS3Cr3 = Gen4GPageTable (TRUE);
- return ;
+ return;
}
/**
@@ -49,11 +49,11 @@ InitPagesForPFHandler ( **/
VOID
RestorePageTableAbove4G (
- UINT64 *PageTable,
- UINT64 PFAddress,
- UINTN CpuIndex,
- UINTN ErrorCode,
- BOOLEAN *IsValidPFAddress
+ UINT64 *PageTable,
+ UINT64 PFAddress,
+ UINTN CpuIndex,
+ UINTN ErrorCode,
+ BOOLEAN *IsValidPFAddress
)
{
}
@@ -67,7 +67,7 @@ RestorePageTableAbove4G ( **/
VOID
ClearTrapFlag (
- IN OUT EFI_SYSTEM_CONTEXT SystemContext
+ IN OUT EFI_SYSTEM_CONTEXT SystemContext
)
{
SystemContext.SystemContextIa32->Eflags &= (UINTN) ~BIT8;
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmProfileArch.h b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmProfileArch.h index 533e8561b2..6c95f2bb19 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmProfileArch.h +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmProfileArch.h @@ -12,42 +12,42 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #pragma pack (1)
typedef struct _MSR_DS_AREA_STRUCT {
- UINT32 BTSBufferBase;
- UINT32 BTSIndex;
- UINT32 BTSAbsoluteMaximum;
- UINT32 BTSInterruptThreshold;
- UINT32 PEBSBufferBase;
- UINT32 PEBSIndex;
- UINT32 PEBSAbsoluteMaximum;
- UINT32 PEBSInterruptThreshold;
- UINT32 PEBSCounterReset[4];
- UINT32 Reserved;
+ UINT32 BTSBufferBase;
+ UINT32 BTSIndex;
+ UINT32 BTSAbsoluteMaximum;
+ UINT32 BTSInterruptThreshold;
+ UINT32 PEBSBufferBase;
+ UINT32 PEBSIndex;
+ UINT32 PEBSAbsoluteMaximum;
+ UINT32 PEBSInterruptThreshold;
+ UINT32 PEBSCounterReset[4];
+ UINT32 Reserved;
} MSR_DS_AREA_STRUCT;
typedef struct _BRANCH_TRACE_RECORD {
- UINT32 LastBranchFrom;
- UINT32 LastBranchTo;
- UINT32 Rsvd0 : 4;
- UINT32 BranchPredicted : 1;
- UINT32 Rsvd1 : 27;
+ UINT32 LastBranchFrom;
+ UINT32 LastBranchTo;
+ UINT32 Rsvd0 : 4;
+ UINT32 BranchPredicted : 1;
+ UINT32 Rsvd1 : 27;
} BRANCH_TRACE_RECORD;
typedef struct _PEBS_RECORD {
- UINT32 Eflags;
- UINT32 LinearIP;
- UINT32 Eax;
- UINT32 Ebx;
- UINT32 Ecx;
- UINT32 Edx;
- UINT32 Esi;
- UINT32 Edi;
- UINT32 Ebp;
- UINT32 Esp;
+ UINT32 Eflags;
+ UINT32 LinearIP;
+ UINT32 Eax;
+ UINT32 Ebx;
+ UINT32 Ecx;
+ UINT32 Edx;
+ UINT32 Esi;
+ UINT32 Edi;
+ UINT32 Ebp;
+ UINT32 Esp;
} PEBS_RECORD;
#pragma pack ()
-#define PHYSICAL_ADDRESS_MASK ((1ull << 32) - SIZE_4KB)
+#define PHYSICAL_ADDRESS_MASK ((1ull << 32) - SIZE_4KB)
/**
Update page table to map the memory correctly in order to make the instruction
@@ -63,11 +63,11 @@ typedef struct _PEBS_RECORD { **/
VOID
RestorePageTableAbove4G (
- UINT64 *PageTable,
- UINT64 PFAddress,
- UINTN CpuIndex,
- UINTN ErrorCode,
- BOOLEAN *IsValidPFAddress
+ UINT64 *PageTable,
+ UINT64 PFAddress,
+ UINTN CpuIndex,
+ UINTN ErrorCode,
+ BOOLEAN *IsValidPFAddress
);
/**
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c index 48f9c330b8..882dee4fe2 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c @@ -13,18 +13,18 @@ SPDX-License-Identifier: BSD-2-Clause-Patent //
// Slots for all MTRR( FIXED MTRR + VARIABLE MTRR + MTRR_LIB_IA32_MTRR_DEF_TYPE)
//
-MTRR_SETTINGS gSmiMtrrs;
-UINT64 gPhyMask;
-SMM_DISPATCHER_MP_SYNC_DATA *mSmmMpSyncData = NULL;
-UINTN mSmmMpSyncDataSize;
-SMM_CPU_SEMAPHORES mSmmCpuSemaphores;
-UINTN mSemaphoreSize;
-SPIN_LOCK *mPFLock = NULL;
-SMM_CPU_SYNC_MODE mCpuSmmSyncMode;
-BOOLEAN mMachineCheckSupported = FALSE;
-MM_COMPLETION mSmmStartupThisApToken;
-
-extern UINTN mSmmShadowStackSize;
+MTRR_SETTINGS gSmiMtrrs;
+UINT64 gPhyMask;
+SMM_DISPATCHER_MP_SYNC_DATA *mSmmMpSyncData = NULL;
+UINTN mSmmMpSyncDataSize;
+SMM_CPU_SEMAPHORES mSmmCpuSemaphores;
+UINTN mSemaphoreSize;
+SPIN_LOCK *mPFLock = NULL;
+SMM_CPU_SYNC_MODE mCpuSmmSyncMode;
+BOOLEAN mMachineCheckSupported = FALSE;
+MM_COMPLETION mSmmStartupThisApToken;
+
+extern UINTN mSmmShadowStackSize;
/**
Performs an atomic compare exchange operation to get semaphore.
@@ -38,27 +38,29 @@ extern UINTN mSmmShadowStackSize; **/
UINT32
WaitForSemaphore (
- IN OUT volatile UINT32 *Sem
+ IN OUT volatile UINT32 *Sem
)
{
- UINT32 Value;
+ UINT32 Value;
- for (;;) {
+ for ( ; ;) {
Value = *Sem;
- if (Value != 0 &&
- InterlockedCompareExchange32 (
- (UINT32*)Sem,
- Value,
- Value - 1
- ) == Value) {
+ if ((Value != 0) &&
+ (InterlockedCompareExchange32 (
+ (UINT32 *)Sem,
+ Value,
+ Value - 1
+ ) == Value))
+ {
break;
}
+
CpuPause ();
}
+
return Value - 1;
}
-
/**
Performs an atomic compare exchange operation to release semaphore.
The compare exchange operation must be performed using
@@ -71,19 +73,20 @@ WaitForSemaphore ( **/
UINT32
ReleaseSemaphore (
- IN OUT volatile UINT32 *Sem
+ IN OUT volatile UINT32 *Sem
)
{
- UINT32 Value;
+ UINT32 Value;
do {
Value = *Sem;
} while (Value + 1 != 0 &&
InterlockedCompareExchange32 (
- (UINT32*)Sem,
+ (UINT32 *)Sem,
Value,
Value + 1
) != Value);
+
return Value + 1;
}
@@ -99,17 +102,19 @@ ReleaseSemaphore ( **/
UINT32
LockdownSemaphore (
- IN OUT volatile UINT32 *Sem
+ IN OUT volatile UINT32 *Sem
)
{
- UINT32 Value;
+ UINT32 Value;
do {
Value = *Sem;
} while (InterlockedCompareExchange32 (
- (UINT32*)Sem,
- Value, (UINT32)-1
+ (UINT32 *)Sem,
+ Value,
+ (UINT32)-1
) != Value);
+
return Value;
}
@@ -121,10 +126,10 @@ LockdownSemaphore ( **/
VOID
WaitForAllAPs (
- IN UINTN NumberOfAPs
+ IN UINTN NumberOfAPs
)
{
- UINTN BspIndex;
+ UINTN BspIndex;
BspIndex = mSmmMpSyncData->BspIndex;
while (NumberOfAPs-- > 0) {
@@ -142,7 +147,7 @@ ReleaseAllAPs ( VOID
)
{
- UINTN Index;
+ UINTN Index;
for (Index = 0; Index < mMaxNumberOfCpus; Index++) {
if (IsPresentAp (Index)) {
@@ -165,9 +170,9 @@ AllCpusInSmmWithExceptions ( SMM_CPU_ARRIVAL_EXCEPTIONS Exceptions
)
{
- UINTN Index;
- SMM_CPU_DATA_BLOCK *CpuData;
- EFI_PROCESSOR_INFORMATION *ProcessorInfo;
+ UINTN Index;
+ SMM_CPU_DATA_BLOCK *CpuData;
+ EFI_PROCESSOR_INFORMATION *ProcessorInfo;
ASSERT (*mSmmMpSyncData->Counter <= mNumberOfCpus);
@@ -175,24 +180,26 @@ AllCpusInSmmWithExceptions ( return TRUE;
}
- CpuData = mSmmMpSyncData->CpuData;
+ CpuData = mSmmMpSyncData->CpuData;
ProcessorInfo = gSmmCpuPrivate->ProcessorInfo;
for (Index = 0; Index < mMaxNumberOfCpus; Index++) {
- if (!(*(CpuData[Index].Present)) && ProcessorInfo[Index].ProcessorId != INVALID_APIC_ID) {
- if (((Exceptions & ARRIVAL_EXCEPTION_DELAYED) != 0) && SmmCpuFeaturesGetSmmRegister (Index, SmmRegSmmDelayed) != 0) {
+ if (!(*(CpuData[Index].Present)) && (ProcessorInfo[Index].ProcessorId != INVALID_APIC_ID)) {
+ if (((Exceptions & ARRIVAL_EXCEPTION_DELAYED) != 0) && (SmmCpuFeaturesGetSmmRegister (Index, SmmRegSmmDelayed) != 0)) {
continue;
}
- if (((Exceptions & ARRIVAL_EXCEPTION_BLOCKED) != 0) && SmmCpuFeaturesGetSmmRegister (Index, SmmRegSmmBlocked) != 0) {
+
+ if (((Exceptions & ARRIVAL_EXCEPTION_BLOCKED) != 0) && (SmmCpuFeaturesGetSmmRegister (Index, SmmRegSmmBlocked) != 0)) {
continue;
}
- if (((Exceptions & ARRIVAL_EXCEPTION_SMI_DISABLED) != 0) && SmmCpuFeaturesGetSmmRegister (Index, SmmRegSmmEnable) != 0) {
+
+ if (((Exceptions & ARRIVAL_EXCEPTION_SMI_DISABLED) != 0) && (SmmCpuFeaturesGetSmmRegister (Index, SmmRegSmmEnable) != 0)) {
continue;
}
+
return FALSE;
}
}
-
return TRUE;
}
@@ -223,7 +230,7 @@ IsLmceOsEnabled ( }
McgExtCtrl.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_EXT_CTL);
- return (BOOLEAN) (McgExtCtrl.Bits.LMCE_EN == 1);
+ return (BOOLEAN)(McgExtCtrl.Bits.LMCE_EN == 1);
}
/**
@@ -241,10 +248,10 @@ IsLmceSignaled ( VOID
)
{
- MSR_IA32_MCG_STATUS_REGISTER McgStatus;
+ MSR_IA32_MCG_STATUS_REGISTER McgStatus;
McgStatus.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_STATUS);
- return (BOOLEAN) (McgStatus.Bits.LMCE_S == 1);
+ return (BOOLEAN)(McgStatus.Bits.LMCE_S == 1);
}
/**
@@ -257,10 +264,10 @@ SmmWaitForApArrival ( VOID
)
{
- UINT64 Timer;
- UINTN Index;
- BOOLEAN LmceEn;
- BOOLEAN LmceSignal;
+ UINT64 Timer;
+ UINTN Index;
+ BOOLEAN LmceEn;
+ BOOLEAN LmceSignal;
ASSERT (*mSmmMpSyncData->Counter <= mNumberOfCpus);
@@ -268,7 +275,7 @@ SmmWaitForApArrival ( LmceSignal = FALSE;
if (mMachineCheckSupported) {
LmceEn = IsLmceOsEnabled ();
- LmceSignal = IsLmceSignaled();
+ LmceSignal = IsLmceSignaled ();
}
//
@@ -287,8 +294,9 @@ SmmWaitForApArrival ( //
for (Timer = StartSyncTimer ();
!IsSyncTimerTimeout (Timer) && !(LmceEn && LmceSignal) &&
- !AllCpusInSmmWithExceptions (ARRIVAL_EXCEPTION_BLOCKED | ARRIVAL_EXCEPTION_SMI_DISABLED );
- ) {
+ !AllCpusInSmmWithExceptions (ARRIVAL_EXCEPTION_BLOCKED | ARRIVAL_EXCEPTION_SMI_DISABLED);
+ )
+ {
CpuPause ();
}
@@ -313,7 +321,7 @@ SmmWaitForApArrival ( // Send SMI IPIs to bring outside processors in
//
for (Index = 0; Index < mMaxNumberOfCpus; Index++) {
- if (!(*(mSmmMpSyncData->CpuData[Index].Present)) && gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId != INVALID_APIC_ID) {
+ if (!(*(mSmmMpSyncData->CpuData[Index].Present)) && (gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId != INVALID_APIC_ID)) {
SendSmiIpi ((UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId);
}
}
@@ -323,8 +331,9 @@ SmmWaitForApArrival ( //
for (Timer = StartSyncTimer ();
!IsSyncTimerTimeout (Timer) &&
- !AllCpusInSmmWithExceptions (ARRIVAL_EXCEPTION_BLOCKED | ARRIVAL_EXCEPTION_SMI_DISABLED );
- ) {
+ !AllCpusInSmmWithExceptions (ARRIVAL_EXCEPTION_BLOCKED | ARRIVAL_EXCEPTION_SMI_DISABLED);
+ )
+ {
CpuPause ();
}
}
@@ -332,7 +341,6 @@ SmmWaitForApArrival ( return;
}
-
/**
Replace OS MTRR's with SMI MTRR's.
@@ -341,7 +349,7 @@ SmmWaitForApArrival ( **/
VOID
ReplaceOSMtrrs (
- IN UINTN CpuIndex
+ IN UINTN CpuIndex
)
{
SmmCpuFeaturesDisableSmrr ();
@@ -363,25 +371,25 @@ ReplaceOSMtrrs ( **/
BOOLEAN
WaitForAllAPsNotBusy (
- IN BOOLEAN BlockMode
+ IN BOOLEAN BlockMode
)
{
- UINTN Index;
+ UINTN Index;
for (Index = 0; Index < mMaxNumberOfCpus; Index++) {
//
// Ignore BSP and APs which not call in SMM.
//
- if (!IsPresentAp(Index)) {
+ if (!IsPresentAp (Index)) {
continue;
}
if (BlockMode) {
- AcquireSpinLock(mSmmMpSyncData->CpuData[Index].Busy);
- ReleaseSpinLock(mSmmMpSyncData->CpuData[Index].Busy);
+ AcquireSpinLock (mSmmMpSyncData->CpuData[Index].Busy);
+ ReleaseSpinLock (mSmmMpSyncData->CpuData[Index].Busy);
} else {
if (AcquireSpinLockOrFail (mSmmMpSyncData->CpuData[Index].Busy)) {
- ReleaseSpinLock(mSmmMpSyncData->CpuData[Index].Busy);
+ ReleaseSpinLock (mSmmMpSyncData->CpuData[Index].Busy);
} else {
return FALSE;
}
@@ -402,11 +410,11 @@ WaitForAllAPsNotBusy ( **/
BOOLEAN
IsPresentAp (
- IN UINTN CpuIndex
+ IN UINTN CpuIndex
)
{
return ((CpuIndex != gSmmCpuPrivate->SmmCoreEntryContext.CurrentlyExecutingCpu) &&
- *(mSmmMpSyncData->CpuData[CpuIndex].Present));
+ *(mSmmMpSyncData->CpuData[CpuIndex].Present));
}
/**
@@ -417,10 +425,10 @@ IsPresentAp ( **/
VOID
ReleaseToken (
- IN UINTN CpuIndex
+ IN UINTN CpuIndex
)
{
- PROCEDURE_TOKEN *Token;
+ PROCEDURE_TOKEN *Token;
Token = mSmmMpSyncData->CpuData[CpuIndex].Token;
@@ -455,15 +463,15 @@ ResetTokens ( **/
VOID
BSPHandler (
- IN UINTN CpuIndex,
- IN SMM_CPU_SYNC_MODE SyncMode
+ IN UINTN CpuIndex,
+ IN SMM_CPU_SYNC_MODE SyncMode
)
{
- UINTN Index;
- MTRR_SETTINGS Mtrrs;
- UINTN ApCount;
- BOOLEAN ClearTopLevelSmiResult;
- UINTN PresentCount;
+ UINTN Index;
+ MTRR_SETTINGS Mtrrs;
+ UINTN ApCount;
+ BOOLEAN ClearTopLevelSmiResult;
+ UINTN PresentCount;
ASSERT (CpuIndex == mSmmMpSyncData->BspIndex);
ApCount = 0;
@@ -488,7 +496,7 @@ BSPHandler ( // we cleared it after SMI handlers are run, we would miss the SMI that
// occurs after SMI handlers are done and before SMI status bit is cleared.
//
- ClearTopLevelSmiResult = ClearTopLevelSmiStatus();
+ ClearTopLevelSmiResult = ClearTopLevelSmiStatus ();
ASSERT (ClearTopLevelSmiResult == TRUE);
//
@@ -499,25 +507,24 @@ BSPHandler ( //
// If Traditional Sync Mode or need to configure MTRRs: gather all available APs.
//
- if (SyncMode == SmmCpuSyncModeTradition || SmmCpuFeaturesNeedConfigureMtrrs()) {
-
+ if ((SyncMode == SmmCpuSyncModeTradition) || SmmCpuFeaturesNeedConfigureMtrrs ()) {
//
// Wait for APs to arrive
//
- SmmWaitForApArrival();
+ SmmWaitForApArrival ();
//
// Lock the counter down and retrieve the number of APs
//
*mSmmMpSyncData->AllCpusInSync = TRUE;
- ApCount = LockdownSemaphore (mSmmMpSyncData->Counter) - 1;
+ ApCount = LockdownSemaphore (mSmmMpSyncData->Counter) - 1;
//
// Wait for all APs to get ready for programming MTRRs
//
WaitForAllAPs (ApCount);
- if (SmmCpuFeaturesNeedConfigureMtrrs()) {
+ if (SmmCpuFeaturesNeedConfigureMtrrs ()) {
//
// Signal all APs it's time for backup MTRRs
//
@@ -531,7 +538,7 @@ BSPHandler ( // We do the backup first and then set MTRR to avoid race condition for threads
// in the same core.
//
- MtrrGetAllMtrrs(&Mtrrs);
+ MtrrGetAllMtrrs (&Mtrrs);
//
// Wait for all APs to complete their MTRR saving
@@ -587,13 +594,12 @@ BSPHandler ( // make those APs to exit SMI synchronously. APs which arrive later will be excluded and
// will run through freely.
//
- if (SyncMode != SmmCpuSyncModeTradition && !SmmCpuFeaturesNeedConfigureMtrrs()) {
-
+ if ((SyncMode != SmmCpuSyncModeTradition) && !SmmCpuFeaturesNeedConfigureMtrrs ()) {
//
// Lock the counter down and retrieve the number of APs
//
*mSmmMpSyncData->AllCpusInSync = TRUE;
- ApCount = LockdownSemaphore (mSmmMpSyncData->Counter) - 1;
+ ApCount = LockdownSemaphore (mSmmMpSyncData->Counter) - 1;
//
// Make sure all APs have their Present flag set
//
@@ -601,9 +607,10 @@ BSPHandler ( PresentCount = 0;
for (Index = 0; Index < mMaxNumberOfCpus; Index++) {
if (*(mSmmMpSyncData->CpuData[Index].Present)) {
- PresentCount ++;
+ PresentCount++;
}
}
+
if (PresentCount > ApCount) {
break;
}
@@ -621,7 +628,7 @@ BSPHandler ( //
WaitForAllAPs (ApCount);
- if (SmmCpuFeaturesNeedConfigureMtrrs()) {
+ if (SmmCpuFeaturesNeedConfigureMtrrs ()) {
//
// Signal APs to restore MTRRs
//
@@ -631,7 +638,7 @@ BSPHandler ( // Restore OS MTRRs
//
SmmCpuFeaturesReenableSmrr ();
- MtrrSetAllMtrrs(&Mtrrs);
+ MtrrSetAllMtrrs (&Mtrrs);
//
// Wait for all APs to complete MTRR programming
@@ -681,7 +688,7 @@ BSPHandler ( //
// Allow APs to check in from this point on
//
- *mSmmMpSyncData->Counter = 0;
+ *mSmmMpSyncData->Counter = 0;
*mSmmMpSyncData->AllCpusInSync = FALSE;
}
@@ -695,15 +702,15 @@ BSPHandler ( **/
VOID
APHandler (
- IN UINTN CpuIndex,
- IN BOOLEAN ValidSmi,
- IN SMM_CPU_SYNC_MODE SyncMode
+ IN UINTN CpuIndex,
+ IN BOOLEAN ValidSmi,
+ IN SMM_CPU_SYNC_MODE SyncMode
)
{
- UINT64 Timer;
- UINTN BspIndex;
- MTRR_SETTINGS Mtrrs;
- EFI_STATUS ProcedureStatus;
+ UINT64 Timer;
+ UINTN BspIndex;
+ MTRR_SETTINGS Mtrrs;
+ EFI_STATUS ProcedureStatus;
//
// Timeout BSP
@@ -711,7 +718,8 @@ APHandler ( for (Timer = StartSyncTimer ();
!IsSyncTimerTimeout (Timer) &&
!(*mSmmMpSyncData->InsideSmm);
- ) {
+ )
+ {
CpuPause ();
}
@@ -737,7 +745,8 @@ APHandler ( for (Timer = StartSyncTimer ();
!IsSyncTimerTimeout (Timer) &&
!(*mSmmMpSyncData->InsideSmm);
- ) {
+ )
+ {
CpuPause ();
}
@@ -768,14 +777,14 @@ APHandler ( //
*(mSmmMpSyncData->CpuData[CpuIndex].Present) = TRUE;
- if (SyncMode == SmmCpuSyncModeTradition || SmmCpuFeaturesNeedConfigureMtrrs()) {
+ if ((SyncMode == SmmCpuSyncModeTradition) || SmmCpuFeaturesNeedConfigureMtrrs ()) {
//
// Notify BSP of arrival at this point
//
ReleaseSemaphore (mSmmMpSyncData->CpuData[BspIndex].Run);
}
- if (SmmCpuFeaturesNeedConfigureMtrrs()) {
+ if (SmmCpuFeaturesNeedConfigureMtrrs ()) {
//
// Wait for the signal from BSP to backup MTRRs
//
@@ -784,7 +793,7 @@ APHandler ( //
// Backup OS MTRRs
//
- MtrrGetAllMtrrs(&Mtrrs);
+ MtrrGetAllMtrrs (&Mtrrs);
//
// Signal BSP the completion of this AP
@@ -830,9 +839,9 @@ APHandler ( //
// Invoke the scheduled procedure
//
- ProcedureStatus = (*mSmmMpSyncData->CpuData[CpuIndex].Procedure) (
- (VOID*)mSmmMpSyncData->CpuData[CpuIndex].Parameter
- );
+ ProcedureStatus = (*mSmmMpSyncData->CpuData[CpuIndex].Procedure)(
+ (VOID *)mSmmMpSyncData->CpuData[CpuIndex].Parameter
+ );
if (mSmmMpSyncData->CpuData[CpuIndex].Status != NULL) {
*mSmmMpSyncData->CpuData[CpuIndex].Status = ProcedureStatus;
}
@@ -847,7 +856,7 @@ APHandler ( ReleaseSpinLock (mSmmMpSyncData->CpuData[CpuIndex].Busy);
}
- if (SmmCpuFeaturesNeedConfigureMtrrs()) {
+ if (SmmCpuFeaturesNeedConfigureMtrrs ()) {
//
// Notify BSP the readiness of this AP to program MTRRs
//
@@ -862,7 +871,7 @@ APHandler ( // Restore OS MTRRs
//
SmmCpuFeaturesReenableSmrr ();
- MtrrSetAllMtrrs(&Mtrrs);
+ MtrrSetAllMtrrs (&Mtrrs);
}
//
@@ -884,7 +893,6 @@ APHandler ( // Notify BSP the readiness of this AP to exit SMM
//
ReleaseSemaphore (mSmmMpSyncData->CpuData[BspIndex].Run);
-
}
/**
@@ -896,7 +904,7 @@ APHandler ( **/
UINT32
Gen4GPageTable (
- IN BOOLEAN Is32BitPageTable
+ IN BOOLEAN Is32BitPageTable
)
{
VOID *PageTable;
@@ -911,9 +919,9 @@ Gen4GPageTable ( UINTN PageIndex;
UINTN PageAddress;
- Low2MBoundary = 0;
+ Low2MBoundary = 0;
High2MBoundary = 0;
- PagesNeeded = 0;
+ PagesNeeded = 0;
if (FeaturePcdGet (PcdCpuSmmStackGuard)) {
//
// Add one more page for known good stack, then find the lower 2MB aligned address.
@@ -924,8 +932,9 @@ Gen4GPageTable ( // then find the lower 2MB aligned address.
//
High2MBoundary = (mSmmStackArrayEnd - mSmmStackSize - mSmmShadowStackSize + EFI_PAGE_SIZE * 2) & ~(SIZE_2MB-1);
- PagesNeeded = ((High2MBoundary - Low2MBoundary) / SIZE_2MB) + 1;
+ PagesNeeded = ((High2MBoundary - Low2MBoundary) / SIZE_2MB) + 1;
}
+
//
// Allocate the page table
//
@@ -933,7 +942,7 @@ Gen4GPageTable ( ASSERT (PageTable != NULL);
PageTable = (VOID *)((UINTN)PageTable);
- Pte = (UINT64*)PageTable;
+ Pte = (UINT64 *)PageTable;
//
// Zero out all page table entries first
@@ -945,8 +954,9 @@ Gen4GPageTable ( //
for (Index = 0; Index < 4; Index++) {
Pte[Index] = ((UINTN)PageTable + EFI_PAGE_SIZE * (Index + 1)) | mAddressEncMask |
- (Is32BitPageTable ? IA32_PAE_PDPTE_ATTRIBUTE_BITS : PAGE_ATTRIBUTE_BITS);
+ (Is32BitPageTable ? IA32_PAE_PDPTE_ATTRIBUTE_BITS : PAGE_ATTRIBUTE_BITS);
}
+
Pte += EFI_PAGE_SIZE / sizeof (*Pte);
//
@@ -956,17 +966,17 @@ Gen4GPageTable ( Pte[Index] = (Index << 21) | mAddressEncMask | IA32_PG_PS | PAGE_ATTRIBUTE_BITS;
}
- Pdpte = (UINT64*)PageTable;
+ Pdpte = (UINT64 *)PageTable;
if (FeaturePcdGet (PcdCpuSmmStackGuard)) {
- Pages = (UINTN)PageTable + EFI_PAGES_TO_SIZE (5);
+ Pages = (UINTN)PageTable + EFI_PAGES_TO_SIZE (5);
GuardPage = mSmmStackArrayBase + EFI_PAGE_SIZE;
for (PageIndex = Low2MBoundary; PageIndex <= High2MBoundary; PageIndex += SIZE_2MB) {
- Pte = (UINT64*)(UINTN)(Pdpte[BitFieldRead32 ((UINT32)PageIndex, 30, 31)] & ~mAddressEncMask & ~(EFI_PAGE_SIZE - 1));
+ Pte = (UINT64 *)(UINTN)(Pdpte[BitFieldRead32 ((UINT32)PageIndex, 30, 31)] & ~mAddressEncMask & ~(EFI_PAGE_SIZE - 1));
Pte[BitFieldRead32 ((UINT32)PageIndex, 21, 29)] = (UINT64)Pages | mAddressEncMask | PAGE_ATTRIBUTE_BITS;
//
// Fill in Page Table Entries
//
- Pte = (UINT64*)Pages;
+ Pte = (UINT64 *)Pages;
PageAddress = PageIndex;
for (Index = 0; Index < EFI_PAGE_SIZE / sizeof (*Pte); Index++) {
if (PageAddress == GuardPage) {
@@ -981,17 +991,19 @@ Gen4GPageTable ( } else {
Pte[Index] = PageAddress | mAddressEncMask | PAGE_ATTRIBUTE_BITS;
}
- PageAddress+= EFI_PAGE_SIZE;
+
+ PageAddress += EFI_PAGE_SIZE;
}
+
Pages += EFI_PAGE_SIZE;
}
}
if ((PcdGet8 (PcdNullPointerDetectionPropertyMask) & BIT1) != 0) {
- Pte = (UINT64*)(UINTN)(Pdpte[0] & ~mAddressEncMask & ~(EFI_PAGE_SIZE - 1));
+ Pte = (UINT64 *)(UINTN)(Pdpte[0] & ~mAddressEncMask & ~(EFI_PAGE_SIZE - 1));
if ((Pte[0] & IA32_PG_PS) == 0) {
// 4K-page entries are already mapped. Just hide the first one anyway.
- Pte = (UINT64*)(UINTN)(Pte[0] & ~mAddressEncMask & ~(EFI_PAGE_SIZE - 1));
+ Pte = (UINT64 *)(UINTN)(Pte[0] & ~mAddressEncMask & ~(EFI_PAGE_SIZE - 1));
Pte[0] &= ~(UINT64)IA32_PG_P; // Hide page 0
} else {
// Create 4K-page entries
@@ -1000,12 +1012,12 @@ Gen4GPageTable ( Pte[0] = (UINT64)(Pages | mAddressEncMask | PAGE_ATTRIBUTE_BITS);
- Pte = (UINT64*)Pages;
+ Pte = (UINT64 *)Pages;
PageAddress = 0;
- Pte[0] = PageAddress | mAddressEncMask; // Hide page 0 but present left
+ Pte[0] = PageAddress | mAddressEncMask; // Hide page 0 but present left
for (Index = 1; Index < EFI_PAGE_SIZE / sizeof (*Pte); Index++) {
PageAddress += EFI_PAGE_SIZE;
- Pte[Index] = PageAddress | mAddressEncMask | PAGE_ATTRIBUTE_BITS;
+ Pte[Index] = PageAddress | mAddressEncMask | PAGE_ATTRIBUTE_BITS;
}
}
}
@@ -1024,11 +1036,11 @@ Gen4GPageTable ( **/
BOOLEAN
IsTokenInUse (
- IN SPIN_LOCK *Token
+ IN SPIN_LOCK *Token
)
{
- LIST_ENTRY *Link;
- PROCEDURE_TOKEN *ProcToken;
+ LIST_ENTRY *Link;
+ PROCEDURE_TOKEN *ProcToken;
if (Token == NULL) {
return FALSE;
@@ -1061,12 +1073,12 @@ AllocateTokenBuffer ( VOID
)
{
- UINTN SpinLockSize;
- UINT32 TokenCountPerChunk;
- UINTN Index;
- SPIN_LOCK *SpinLock;
- UINT8 *SpinLockBuffer;
- PROCEDURE_TOKEN *ProcTokens;
+ UINTN SpinLockSize;
+ UINT32 TokenCountPerChunk;
+ UINTN Index;
+ SPIN_LOCK *SpinLock;
+ UINT8 *SpinLockBuffer;
+ PROCEDURE_TOKEN *ProcTokens;
SpinLockSize = GetSpinLockProperties ();
@@ -1076,6 +1088,7 @@ AllocateTokenBuffer ( DEBUG ((DEBUG_ERROR, "PcdCpuSmmMpTokenCountPerChunk should not be Zero!\n"));
CpuDeadLoop ();
}
+
DEBUG ((DEBUG_INFO, "CpuSmm: SpinLock Size = 0x%x, PcdCpuSmmMpTokenCountPerChunk = 0x%x\n", SpinLockSize, TokenCountPerChunk));
//
@@ -1113,7 +1126,7 @@ AllocateTokenBuffer ( **/
PROCEDURE_TOKEN *
GetFreeToken (
- IN UINT32 RunningApsCount
+ IN UINT32 RunningApsCount
)
{
PROCEDURE_TOKEN *NewToken;
@@ -1125,7 +1138,8 @@ GetFreeToken ( if (gSmmCpuPrivate->FirstFreeToken == &gSmmCpuPrivate->TokenList) {
gSmmCpuPrivate->FirstFreeToken = AllocateTokenBuffer ();
}
- NewToken = PROCEDURE_TOKEN_FROM_LINK (gSmmCpuPrivate->FirstFreeToken);
+
+ NewToken = PROCEDURE_TOKEN_FROM_LINK (gSmmCpuPrivate->FirstFreeToken);
gSmmCpuPrivate->FirstFreeToken = GetNextNode (&gSmmCpuPrivate->TokenList, gSmmCpuPrivate->FirstFreeToken);
NewToken->RunningApCount = RunningApsCount;
@@ -1148,7 +1162,7 @@ GetFreeToken ( **/
EFI_STATUS
IsApReady (
- IN SPIN_LOCK *Token
+ IN SPIN_LOCK *Token
)
{
if (AcquireSpinLockOrFail (Token)) {
@@ -1196,42 +1210,50 @@ IsApReady ( **/
EFI_STATUS
InternalSmmStartupThisAp (
- IN EFI_AP_PROCEDURE2 Procedure,
- IN UINTN CpuIndex,
- IN OUT VOID *ProcArguments OPTIONAL,
- IN MM_COMPLETION *Token,
- IN UINTN TimeoutInMicroseconds,
- IN OUT EFI_STATUS *CpuStatus
+ IN EFI_AP_PROCEDURE2 Procedure,
+ IN UINTN CpuIndex,
+ IN OUT VOID *ProcArguments OPTIONAL,
+ IN MM_COMPLETION *Token,
+ IN UINTN TimeoutInMicroseconds,
+ IN OUT EFI_STATUS *CpuStatus
)
{
- PROCEDURE_TOKEN *ProcToken;
+ PROCEDURE_TOKEN *ProcToken;
if (CpuIndex >= gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus) {
- DEBUG((DEBUG_ERROR, "CpuIndex(%d) >= gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus(%d)\n", CpuIndex, gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus));
+ DEBUG ((DEBUG_ERROR, "CpuIndex(%d) >= gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus(%d)\n", CpuIndex, gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus));
return EFI_INVALID_PARAMETER;
}
+
if (CpuIndex == gSmmCpuPrivate->SmmCoreEntryContext.CurrentlyExecutingCpu) {
- DEBUG((DEBUG_ERROR, "CpuIndex(%d) == gSmmCpuPrivate->SmmCoreEntryContext.CurrentlyExecutingCpu\n", CpuIndex));
+ DEBUG ((DEBUG_ERROR, "CpuIndex(%d) == gSmmCpuPrivate->SmmCoreEntryContext.CurrentlyExecutingCpu\n", CpuIndex));
return EFI_INVALID_PARAMETER;
}
+
if (gSmmCpuPrivate->ProcessorInfo[CpuIndex].ProcessorId == INVALID_APIC_ID) {
return EFI_INVALID_PARAMETER;
}
+
if (!(*(mSmmMpSyncData->CpuData[CpuIndex].Present))) {
if (mSmmMpSyncData->EffectiveSyncMode == SmmCpuSyncModeTradition) {
- DEBUG((DEBUG_ERROR, "!mSmmMpSyncData->CpuData[%d].Present\n", CpuIndex));
+ DEBUG ((DEBUG_ERROR, "!mSmmMpSyncData->CpuData[%d].Present\n", CpuIndex));
}
+
return EFI_INVALID_PARAMETER;
}
+
if (gSmmCpuPrivate->Operation[CpuIndex] == SmmCpuRemove) {
if (!FeaturePcdGet (PcdCpuHotPlugSupport)) {
- DEBUG((DEBUG_ERROR, "gSmmCpuPrivate->Operation[%d] == SmmCpuRemove\n", CpuIndex));
+ DEBUG ((DEBUG_ERROR, "gSmmCpuPrivate->Operation[%d] == SmmCpuRemove\n", CpuIndex));
}
+
return EFI_INVALID_PARAMETER;
}
+
if ((TimeoutInMicroseconds != 0) && ((mSmmMp.Attributes & EFI_MM_MP_TIMEOUT_SUPPORTED) == 0)) {
return EFI_INVALID_PARAMETER;
}
+
if (Procedure == NULL) {
return EFI_INVALID_PARAMETER;
}
@@ -1257,12 +1279,13 @@ InternalSmmStartupThisAp ( // 2. Get a free token from the token buffer.
// 3. Call ReleaseToken() in APHandler().
//
- ProcToken = GetFreeToken (1);
+ ProcToken = GetFreeToken (1);
mSmmMpSyncData->CpuData[CpuIndex].Token = ProcToken;
- *Token = (MM_COMPLETION)ProcToken->SpinLock;
+ *Token = (MM_COMPLETION)ProcToken->SpinLock;
}
}
- mSmmMpSyncData->CpuData[CpuIndex].Status = CpuStatus;
+
+ mSmmMpSyncData->CpuData[CpuIndex].Status = CpuStatus;
if (mSmmMpSyncData->CpuData[CpuIndex].Status != NULL) {
*mSmmMpSyncData->CpuData[CpuIndex].Status = EFI_NOT_READY;
}
@@ -1309,20 +1332,21 @@ InternalSmmStartupThisAp ( **/
EFI_STATUS
InternalSmmStartupAllAPs (
- IN EFI_AP_PROCEDURE2 Procedure,
- IN UINTN TimeoutInMicroseconds,
- IN OUT VOID *ProcedureArguments OPTIONAL,
- IN OUT MM_COMPLETION *Token,
- IN OUT EFI_STATUS *CPUStatus
+ IN EFI_AP_PROCEDURE2 Procedure,
+ IN UINTN TimeoutInMicroseconds,
+ IN OUT VOID *ProcedureArguments OPTIONAL,
+ IN OUT MM_COMPLETION *Token,
+ IN OUT EFI_STATUS *CPUStatus
)
{
- UINTN Index;
- UINTN CpuCount;
- PROCEDURE_TOKEN *ProcToken;
+ UINTN Index;
+ UINTN CpuCount;
+ PROCEDURE_TOKEN *ProcToken;
if ((TimeoutInMicroseconds != 0) && ((mSmmMp.Attributes & EFI_MM_MP_TIMEOUT_SUPPORTED) == 0)) {
return EFI_INVALID_PARAMETER;
}
+
if (Procedure == NULL) {
return EFI_INVALID_PARAMETER;
}
@@ -1330,25 +1354,27 @@ InternalSmmStartupAllAPs ( CpuCount = 0;
for (Index = 0; Index < mMaxNumberOfCpus; Index++) {
if (IsPresentAp (Index)) {
- CpuCount ++;
+ CpuCount++;
if (gSmmCpuPrivate->Operation[Index] == SmmCpuRemove) {
return EFI_INVALID_PARAMETER;
}
- if (!AcquireSpinLockOrFail(mSmmMpSyncData->CpuData[Index].Busy)) {
+ if (!AcquireSpinLockOrFail (mSmmMpSyncData->CpuData[Index].Busy)) {
return EFI_NOT_READY;
}
+
ReleaseSpinLock (mSmmMpSyncData->CpuData[Index].Busy);
}
}
+
if (CpuCount == 0) {
return EFI_NOT_STARTED;
}
if (Token != NULL) {
ProcToken = GetFreeToken ((UINT32)mMaxNumberOfCpus);
- *Token = (MM_COMPLETION)ProcToken->SpinLock;
+ *Token = (MM_COMPLETION)ProcToken->SpinLock;
} else {
ProcToken = NULL;
}
@@ -1368,13 +1394,14 @@ InternalSmmStartupAllAPs ( for (Index = 0; Index < mMaxNumberOfCpus; Index++) {
if (IsPresentAp (Index)) {
- mSmmMpSyncData->CpuData[Index].Procedure = (EFI_AP_PROCEDURE2) Procedure;
+ mSmmMpSyncData->CpuData[Index].Procedure = (EFI_AP_PROCEDURE2)Procedure;
mSmmMpSyncData->CpuData[Index].Parameter = ProcedureArguments;
if (ProcToken != NULL) {
- mSmmMpSyncData->CpuData[Index].Token = ProcToken;
+ mSmmMpSyncData->CpuData[Index].Token = ProcToken;
}
+
if (CPUStatus != NULL) {
- mSmmMpSyncData->CpuData[Index].Status = &CPUStatus[Index];
+ mSmmMpSyncData->CpuData[Index].Status = &CPUStatus[Index];
if (mSmmMpSyncData->CpuData[Index].Status != NULL) {
*mSmmMpSyncData->CpuData[Index].Status = EFI_NOT_READY;
}
@@ -1426,10 +1453,10 @@ InternalSmmStartupAllAPs ( EFI_STATUS
EFIAPI
ProcedureWrapper (
- IN VOID *Buffer
+ IN VOID *Buffer
)
{
- PROCEDURE_WRAPPER *Wrapper;
+ PROCEDURE_WRAPPER *Wrapper;
Wrapper = Buffer;
Wrapper->Procedure (Wrapper->ProcedureArgument);
@@ -1454,14 +1481,14 @@ ProcedureWrapper ( EFI_STATUS
EFIAPI
SmmBlockingStartupThisAp (
- IN EFI_AP_PROCEDURE Procedure,
- IN UINTN CpuIndex,
- IN OUT VOID *ProcArguments OPTIONAL
+ IN EFI_AP_PROCEDURE Procedure,
+ IN UINTN CpuIndex,
+ IN OUT VOID *ProcArguments OPTIONAL
)
{
PROCEDURE_WRAPPER Wrapper;
- Wrapper.Procedure = Procedure;
+ Wrapper.Procedure = Procedure;
Wrapper.ProcedureArgument = ProcArguments;
//
@@ -1487,25 +1514,25 @@ SmmBlockingStartupThisAp ( EFI_STATUS
EFIAPI
SmmStartupThisAp (
- IN EFI_AP_PROCEDURE Procedure,
- IN UINTN CpuIndex,
- IN OUT VOID *ProcArguments OPTIONAL
+ IN EFI_AP_PROCEDURE Procedure,
+ IN UINTN CpuIndex,
+ IN OUT VOID *ProcArguments OPTIONAL
)
{
- gSmmCpuPrivate->ApWrapperFunc[CpuIndex].Procedure = Procedure;
+ gSmmCpuPrivate->ApWrapperFunc[CpuIndex].Procedure = Procedure;
gSmmCpuPrivate->ApWrapperFunc[CpuIndex].ProcedureArgument = ProcArguments;
//
// Use wrapper function to convert EFI_AP_PROCEDURE to EFI_AP_PROCEDURE2.
//
return InternalSmmStartupThisAp (
- ProcedureWrapper,
- CpuIndex,
- &gSmmCpuPrivate->ApWrapperFunc[CpuIndex],
- FeaturePcdGet (PcdCpuSmmBlockStartupThisAp) ? NULL : &mSmmStartupThisApToken,
- 0,
- NULL
- );
+ ProcedureWrapper,
+ CpuIndex,
+ &gSmmCpuPrivate->ApWrapperFunc[CpuIndex],
+ FeaturePcdGet (PcdCpuSmmBlockStartupThisAp) ? NULL : &mSmmStartupThisApToken,
+ 0,
+ NULL
+ );
}
/**
@@ -1524,10 +1551,10 @@ CpuSmmDebugEntry ( IN UINTN CpuIndex
)
{
- SMRAM_SAVE_STATE_MAP *CpuSaveState;
+ SMRAM_SAVE_STATE_MAP *CpuSaveState;
if (FeaturePcdGet (PcdCpuSmmDebug)) {
- ASSERT(CpuIndex < mMaxNumberOfCpus);
+ ASSERT (CpuIndex < mMaxNumberOfCpus);
CpuSaveState = (SMRAM_SAVE_STATE_MAP *)gSmmCpuPrivate->CpuSaveState[CpuIndex];
if (mSmmSaveStateRegisterLma == EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT) {
AsmWriteDr6 (CpuSaveState->x86._DR6);
@@ -1554,10 +1581,10 @@ CpuSmmDebugExit ( IN UINTN CpuIndex
)
{
- SMRAM_SAVE_STATE_MAP *CpuSaveState;
+ SMRAM_SAVE_STATE_MAP *CpuSaveState;
if (FeaturePcdGet (PcdCpuSmmDebug)) {
- ASSERT(CpuIndex < mMaxNumberOfCpus);
+ ASSERT (CpuIndex < mMaxNumberOfCpus);
CpuSaveState = (SMRAM_SAVE_STATE_MAP *)gSmmCpuPrivate->CpuSaveState[CpuIndex];
if (mSmmSaveStateRegisterLma == EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT) {
CpuSaveState->x86._DR7 = (UINT32)AsmReadDr7 ();
@@ -1578,17 +1605,17 @@ CpuSmmDebugExit ( VOID
EFIAPI
SmiRendezvous (
- IN UINTN CpuIndex
+ IN UINTN CpuIndex
)
{
- EFI_STATUS Status;
- BOOLEAN ValidSmi;
- BOOLEAN IsBsp;
- BOOLEAN BspInProgress;
- UINTN Index;
- UINTN Cr2;
+ EFI_STATUS Status;
+ BOOLEAN ValidSmi;
+ BOOLEAN IsBsp;
+ BOOLEAN BspInProgress;
+ UINTN Index;
+ UINTN Cr2;
- ASSERT(CpuIndex < mMaxNumberOfCpus);
+ ASSERT (CpuIndex < mMaxNumberOfCpus);
//
// Save Cr2 because Page Fault exception in SMM may override its value,
@@ -1612,7 +1639,7 @@ SmiRendezvous ( //
// Determine if this is a valid SMI
//
- ValidSmi = PlatformValidSmi();
+ ValidSmi = PlatformValidSmi ();
//
// Determine if BSP has been already in progress. Note this must be checked after
@@ -1644,9 +1671,9 @@ SmiRendezvous ( while (*mSmmMpSyncData->AllCpusInSync) {
CpuPause ();
}
+
goto Exit;
} else {
-
//
// The BUSY lock is initialized to Released state.
// This needs to be done early enough to be ready for BSP's SmmStartupThisAp() call.
@@ -1693,7 +1720,7 @@ SmiRendezvous ( // Platform hook fails to determine, use default BSP election method
//
InterlockedCompareExchange32 (
- (UINT32*)&mSmmMpSyncData->BspIndex,
+ (UINT32 *)&mSmmMpSyncData->BspIndex,
(UINT32)-1,
(UINT32)CpuIndex
);
@@ -1705,7 +1732,6 @@ SmiRendezvous ( // "mSmmMpSyncData->BspIndex == CpuIndex" means this is the BSP
//
if (mSmmMpSyncData->BspIndex == CpuIndex) {
-
//
// Clear last request for SwitchBsp.
//
@@ -1774,45 +1800,45 @@ InitializeSmmCpuSemaphores ( VOID
)
{
- UINTN ProcessorCount;
- UINTN TotalSize;
- UINTN GlobalSemaphoresSize;
- UINTN CpuSemaphoresSize;
- UINTN SemaphoreSize;
- UINTN Pages;
- UINTN *SemaphoreBlock;
- UINTN SemaphoreAddr;
-
- SemaphoreSize = GetSpinLockProperties ();
- ProcessorCount = gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus;
+ UINTN ProcessorCount;
+ UINTN TotalSize;
+ UINTN GlobalSemaphoresSize;
+ UINTN CpuSemaphoresSize;
+ UINTN SemaphoreSize;
+ UINTN Pages;
+ UINTN *SemaphoreBlock;
+ UINTN SemaphoreAddr;
+
+ SemaphoreSize = GetSpinLockProperties ();
+ ProcessorCount = gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus;
GlobalSemaphoresSize = (sizeof (SMM_CPU_SEMAPHORE_GLOBAL) / sizeof (VOID *)) * SemaphoreSize;
CpuSemaphoresSize = (sizeof (SMM_CPU_SEMAPHORE_CPU) / sizeof (VOID *)) * ProcessorCount * SemaphoreSize;
- TotalSize = GlobalSemaphoresSize + CpuSemaphoresSize;
- DEBUG((DEBUG_INFO, "One Semaphore Size = 0x%x\n", SemaphoreSize));
- DEBUG((DEBUG_INFO, "Total Semaphores Size = 0x%x\n", TotalSize));
- Pages = EFI_SIZE_TO_PAGES (TotalSize);
+ TotalSize = GlobalSemaphoresSize + CpuSemaphoresSize;
+ DEBUG ((DEBUG_INFO, "One Semaphore Size = 0x%x\n", SemaphoreSize));
+ DEBUG ((DEBUG_INFO, "Total Semaphores Size = 0x%x\n", TotalSize));
+ Pages = EFI_SIZE_TO_PAGES (TotalSize);
SemaphoreBlock = AllocatePages (Pages);
ASSERT (SemaphoreBlock != NULL);
ZeroMem (SemaphoreBlock, TotalSize);
- SemaphoreAddr = (UINTN)SemaphoreBlock;
+ SemaphoreAddr = (UINTN)SemaphoreBlock;
mSmmCpuSemaphores.SemaphoreGlobal.Counter = (UINT32 *)SemaphoreAddr;
- SemaphoreAddr += SemaphoreSize;
+ SemaphoreAddr += SemaphoreSize;
mSmmCpuSemaphores.SemaphoreGlobal.InsideSmm = (BOOLEAN *)SemaphoreAddr;
- SemaphoreAddr += SemaphoreSize;
+ SemaphoreAddr += SemaphoreSize;
mSmmCpuSemaphores.SemaphoreGlobal.AllCpusInSync = (BOOLEAN *)SemaphoreAddr;
- SemaphoreAddr += SemaphoreSize;
+ SemaphoreAddr += SemaphoreSize;
mSmmCpuSemaphores.SemaphoreGlobal.PFLock = (SPIN_LOCK *)SemaphoreAddr;
- SemaphoreAddr += SemaphoreSize;
+ SemaphoreAddr += SemaphoreSize;
mSmmCpuSemaphores.SemaphoreGlobal.CodeAccessCheckLock
- = (SPIN_LOCK *)SemaphoreAddr;
+ = (SPIN_LOCK *)SemaphoreAddr;
SemaphoreAddr += SemaphoreSize;
- SemaphoreAddr = (UINTN)SemaphoreBlock + GlobalSemaphoresSize;
+ SemaphoreAddr = (UINTN)SemaphoreBlock + GlobalSemaphoresSize;
mSmmCpuSemaphores.SemaphoreCpu.Busy = (SPIN_LOCK *)SemaphoreAddr;
- SemaphoreAddr += ProcessorCount * SemaphoreSize;
+ SemaphoreAddr += ProcessorCount * SemaphoreSize;
mSmmCpuSemaphores.SemaphoreCpu.Run = (UINT32 *)SemaphoreAddr;
- SemaphoreAddr += ProcessorCount * SemaphoreSize;
+ SemaphoreAddr += ProcessorCount * SemaphoreSize;
mSmmCpuSemaphores.SemaphoreCpu.Present = (BOOLEAN *)SemaphoreAddr;
mPFLock = mSmmCpuSemaphores.SemaphoreGlobal.PFLock;
@@ -1831,7 +1857,7 @@ InitializeMpSyncData ( VOID
)
{
- UINTN CpuIndex;
+ UINTN CpuIndex;
if (mSmmMpSyncData != NULL) {
//
@@ -1839,7 +1865,7 @@ InitializeMpSyncData ( // CpuData array of SMM_CPU_DATA_BLOCK and one CandidateBsp array of BOOLEAN.
//
ZeroMem (mSmmMpSyncData, mSmmMpSyncDataSize);
- mSmmMpSyncData->CpuData = (SMM_CPU_DATA_BLOCK *)((UINT8 *)mSmmMpSyncData + sizeof (SMM_DISPATCHER_MP_SYNC_DATA));
+ mSmmMpSyncData->CpuData = (SMM_CPU_DATA_BLOCK *)((UINT8 *)mSmmMpSyncData + sizeof (SMM_DISPATCHER_MP_SYNC_DATA));
mSmmMpSyncData->CandidateBsp = (BOOLEAN *)(mSmmMpSyncData->CpuData + gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus);
if (FeaturePcdGet (PcdCpuSmmEnableBspElection)) {
//
@@ -1847,21 +1873,24 @@ InitializeMpSyncData ( //
mSmmMpSyncData->BspIndex = (UINT32)-1;
}
+
mSmmMpSyncData->EffectiveSyncMode = mCpuSmmSyncMode;
mSmmMpSyncData->Counter = mSmmCpuSemaphores.SemaphoreGlobal.Counter;
mSmmMpSyncData->InsideSmm = mSmmCpuSemaphores.SemaphoreGlobal.InsideSmm;
mSmmMpSyncData->AllCpusInSync = mSmmCpuSemaphores.SemaphoreGlobal.AllCpusInSync;
- ASSERT (mSmmMpSyncData->Counter != NULL && mSmmMpSyncData->InsideSmm != NULL &&
- mSmmMpSyncData->AllCpusInSync != NULL);
+ ASSERT (
+ mSmmMpSyncData->Counter != NULL && mSmmMpSyncData->InsideSmm != NULL &&
+ mSmmMpSyncData->AllCpusInSync != NULL
+ );
*mSmmMpSyncData->Counter = 0;
*mSmmMpSyncData->InsideSmm = FALSE;
*mSmmMpSyncData->AllCpusInSync = FALSE;
- for (CpuIndex = 0; CpuIndex < gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus; CpuIndex ++) {
- mSmmMpSyncData->CpuData[CpuIndex].Busy =
+ for (CpuIndex = 0; CpuIndex < gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus; CpuIndex++) {
+ mSmmMpSyncData->CpuData[CpuIndex].Busy =
(SPIN_LOCK *)((UINTN)mSmmCpuSemaphores.SemaphoreCpu.Busy + mSemaphoreSize * CpuIndex);
- mSmmMpSyncData->CpuData[CpuIndex].Run =
+ mSmmMpSyncData->CpuData[CpuIndex].Run =
(UINT32 *)((UINTN)mSmmCpuSemaphores.SemaphoreCpu.Run + mSemaphoreSize * CpuIndex);
mSmmMpSyncData->CpuData[CpuIndex].Present =
(BOOLEAN *)((UINTN)mSmmCpuSemaphores.SemaphoreCpu.Present + mSemaphoreSize * CpuIndex);
@@ -1882,9 +1911,9 @@ InitializeMpSyncData ( **/
UINT32
InitializeMpServiceData (
- IN VOID *Stacks,
- IN UINTN StackSize,
- IN UINTN ShadowStackSize
+ IN VOID *Stacks,
+ IN UINTN StackSize,
+ IN UINTN ShadowStackSize
)
{
UINT32 Cr3;
@@ -1911,7 +1940,7 @@ InitializeMpServiceData ( //
mSmmMpSyncDataSize = sizeof (SMM_DISPATCHER_MP_SYNC_DATA) +
(sizeof (SMM_CPU_DATA_BLOCK) + sizeof (BOOLEAN)) * gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus;
- mSmmMpSyncData = (SMM_DISPATCHER_MP_SYNC_DATA*) AllocatePages (EFI_SIZE_TO_PAGES (mSmmMpSyncDataSize));
+ mSmmMpSyncData = (SMM_DISPATCHER_MP_SYNC_DATA *)AllocatePages (EFI_SIZE_TO_PAGES (mSmmMpSyncDataSize));
ASSERT (mSmmMpSyncData != NULL);
mCpuSmmSyncMode = (SMM_CPU_SYNC_MODE)PcdGet8 (PcdCpuSmmSyncMode);
InitializeMpSyncData ();
@@ -1926,7 +1955,8 @@ InitializeMpServiceData ( } else {
VirPhyAddressSize.Bits.PhysicalAddressBits = 36;
}
- gPhyMask = LShiftU64 (1, VirPhyAddressSize.Bits.PhysicalAddressBits) - 1;
+
+ gPhyMask = LShiftU64 (1, VirPhyAddressSize.Bits.PhysicalAddressBits) - 1;
//
// Clear the low 12 bits
//
@@ -1946,7 +1976,7 @@ InitializeMpServiceData ( InstallSmiHandler (
Index,
(UINT32)mCpuHotPlugData.SmBase[Index],
- (VOID*)((UINTN)Stacks + (StackSize + ShadowStackSize) * Index),
+ (VOID *)((UINTN)Stacks + (StackSize + ShadowStackSize) * Index),
StackSize,
(UINTN)(GdtTssTables + GdtTableStepSize * Index),
gcSmiGdtr.Limit + 1,
@@ -2009,13 +2039,14 @@ RegisterSmmEntry ( **/
EFI_STATUS
RegisterStartupProcedure (
- IN EFI_AP_PROCEDURE Procedure,
- IN OUT VOID *ProcedureArguments OPTIONAL
+ IN EFI_AP_PROCEDURE Procedure,
+ IN OUT VOID *ProcedureArguments OPTIONAL
)
{
- if (Procedure == NULL && ProcedureArguments != NULL) {
+ if ((Procedure == NULL) && (ProcedureArguments != NULL)) {
return EFI_INVALID_PARAMETER;
}
+
if (mSmmMpSyncData == NULL) {
return EFI_NOT_READY;
}
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c index fbf45d6525..40aabeda72 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c @@ -21,7 +21,9 @@ SMM_CPU_PRIVATE_DATA mSmmCpuPrivateData = { NULL, // Pointer to Operation array
NULL, // Pointer to CpuSaveStateSize array
NULL, // Pointer to CpuSaveState array
- { {0} }, // SmmReservedSmramRegion
+ {
+ { 0 }
+ }, // SmmReservedSmramRegion
{
SmmStartupThisAp, // SmmCoreEntryContext.SmmStartupThisAp
0, // SmmCoreEntryContext.CurrentlyExecutingCpu
@@ -35,10 +37,10 @@ SMM_CPU_PRIVATE_DATA mSmmCpuPrivateData = { RegisterSmmEntry // SmmConfiguration.RegisterSmmEntry
},
NULL, // pointer to Ap Wrapper Func array
- {NULL, NULL}, // List_Entry for Tokens.
+ { NULL, NULL }, // List_Entry for Tokens.
};
-CPU_HOT_PLUG_DATA mCpuHotPlugData = {
+CPU_HOT_PLUG_DATA mCpuHotPlugData = {
CPU_HOT_PLUG_DATA_REVISION_1, // Revision
0, // Array Length of SmBase and APIC ID
NULL, // Pointer to APIC ID array
@@ -67,7 +69,7 @@ EFI_HANDLE mSmmCpuHandle = NULL; ///
/// SMM CPU Protocol instance
///
-EFI_SMM_CPU_PROTOCOL mSmmCpu = {
+EFI_SMM_CPU_PROTOCOL mSmmCpu = {
SmmReadSaveState,
SmmWriteSaveState
};
@@ -75,60 +77,60 @@ EFI_SMM_CPU_PROTOCOL mSmmCpu = { ///
/// SMM Memory Attribute Protocol instance
///
-EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL mSmmMemoryAttribute = {
+EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL mSmmMemoryAttribute = {
EdkiiSmmGetMemoryAttributes,
EdkiiSmmSetMemoryAttributes,
EdkiiSmmClearMemoryAttributes
};
-EFI_CPU_INTERRUPT_HANDLER mExternalVectorTable[EXCEPTION_VECTOR_NUMBER];
+EFI_CPU_INTERRUPT_HANDLER mExternalVectorTable[EXCEPTION_VECTOR_NUMBER];
//
// SMM stack information
//
-UINTN mSmmStackArrayBase;
-UINTN mSmmStackArrayEnd;
-UINTN mSmmStackSize;
+UINTN mSmmStackArrayBase;
+UINTN mSmmStackArrayEnd;
+UINTN mSmmStackSize;
-UINTN mSmmShadowStackSize;
-BOOLEAN mCetSupported = TRUE;
+UINTN mSmmShadowStackSize;
+BOOLEAN mCetSupported = TRUE;
-UINTN mMaxNumberOfCpus = 1;
-UINTN mNumberOfCpus = 1;
+UINTN mMaxNumberOfCpus = 1;
+UINTN mNumberOfCpus = 1;
//
// SMM ready to lock flag
//
-BOOLEAN mSmmReadyToLock = FALSE;
+BOOLEAN mSmmReadyToLock = FALSE;
//
// Global used to cache PCD for SMM Code Access Check enable
//
-BOOLEAN mSmmCodeAccessCheckEnable = FALSE;
+BOOLEAN mSmmCodeAccessCheckEnable = FALSE;
//
// Global copy of the PcdPteMemoryEncryptionAddressOrMask
//
-UINT64 mAddressEncMask = 0;
+UINT64 mAddressEncMask = 0;
//
// Spin lock used to serialize setting of SMM Code Access Check feature
//
-SPIN_LOCK *mConfigSmmCodeAccessCheckLock = NULL;
+SPIN_LOCK *mConfigSmmCodeAccessCheckLock = NULL;
//
// Saved SMM ranges information
//
-EFI_SMRAM_DESCRIPTOR *mSmmCpuSmramRanges;
-UINTN mSmmCpuSmramRangeCount;
+EFI_SMRAM_DESCRIPTOR *mSmmCpuSmramRanges;
+UINTN mSmmCpuSmramRangeCount;
-UINT8 mPhysicalAddressBits;
+UINT8 mPhysicalAddressBits;
//
// Control register contents saved for SMM S3 resume state initialization.
//
-UINT32 mSmmCr0;
-UINT32 mSmmCr4;
+UINT32 mSmmCr0;
+UINT32 mSmmCr4;
/**
Initialize IDT to setup exception handlers for SMM.
@@ -139,19 +141,19 @@ InitializeSmmIdt ( VOID
)
{
- EFI_STATUS Status;
- BOOLEAN InterruptState;
- IA32_DESCRIPTOR DxeIdtr;
+ EFI_STATUS Status;
+ BOOLEAN InterruptState;
+ IA32_DESCRIPTOR DxeIdtr;
//
// There are 32 (not 255) entries in it since only processor
// generated exceptions will be handled.
//
- gcSmiIdtr.Limit = (sizeof(IA32_IDT_GATE_DESCRIPTOR) * 32) - 1;
+ gcSmiIdtr.Limit = (sizeof (IA32_IDT_GATE_DESCRIPTOR) * 32) - 1;
//
// Allocate page aligned IDT, because it might be set as read only.
//
- gcSmiIdtr.Base = (UINTN)AllocateCodePages (EFI_SIZE_TO_PAGES(gcSmiIdtr.Limit + 1));
+ gcSmiIdtr.Base = (UINTN)AllocateCodePages (EFI_SIZE_TO_PAGES (gcSmiIdtr.Limit + 1));
ASSERT (gcSmiIdtr.Base != 0);
ZeroMem ((VOID *)gcSmiIdtr.Base, gcSmiIdtr.Limit + 1);
@@ -173,7 +175,7 @@ InitializeSmmIdt ( //
// Restore DXE IDT table and CPU interrupt
//
- AsmWriteIdtr ((IA32_DESCRIPTOR *) &DxeIdtr);
+ AsmWriteIdtr ((IA32_DESCRIPTOR *)&DxeIdtr);
SetInterruptState (InterruptState);
}
@@ -185,19 +187,19 @@ InitializeSmmIdt ( **/
VOID
DumpModuleInfoByIp (
- IN UINTN CallerIpAddress
+ IN UINTN CallerIpAddress
)
{
- UINTN Pe32Data;
- VOID *PdbPointer;
+ UINTN Pe32Data;
+ VOID *PdbPointer;
//
// Find Image Base
//
Pe32Data = PeCoffSearchImageBase (CallerIpAddress);
if (Pe32Data != 0) {
- DEBUG ((DEBUG_ERROR, "It is invoked from the instruction before IP(0x%p)", (VOID *) CallerIpAddress));
- PdbPointer = PeCoffLoaderGetPdbPointer ((VOID *) Pe32Data);
+ DEBUG ((DEBUG_ERROR, "It is invoked from the instruction before IP(0x%p)", (VOID *)CallerIpAddress));
+ PdbPointer = PeCoffLoaderGetPdbPointer ((VOID *)Pe32Data);
if (PdbPointer != NULL) {
DEBUG ((DEBUG_ERROR, " in module (%a)\n", PdbPointer));
}
@@ -221,11 +223,11 @@ DumpModuleInfoByIp ( EFI_STATUS
EFIAPI
SmmReadSaveState (
- IN CONST EFI_SMM_CPU_PROTOCOL *This,
- IN UINTN Width,
- IN EFI_SMM_SAVE_STATE_REGISTER Register,
- IN UINTN CpuIndex,
- OUT VOID *Buffer
+ IN CONST EFI_SMM_CPU_PROTOCOL *This,
+ IN UINTN Width,
+ IN EFI_SMM_SAVE_STATE_REGISTER Register,
+ IN UINTN CpuIndex,
+ OUT VOID *Buffer
)
{
EFI_STATUS Status;
@@ -236,6 +238,7 @@ SmmReadSaveState ( if ((CpuIndex >= gSmst->NumberOfCpus) || (Buffer == NULL)) {
return EFI_INVALID_PARAMETER;
}
+
//
// The SpeculationBarrier() call here is to ensure the above check for the
// CpuIndex has been completed before the execution of subsequent codes.
@@ -252,6 +255,7 @@ SmmReadSaveState ( if (Width != sizeof (UINT64)) {
return EFI_INVALID_PARAMETER;
}
+
//
// If the processor is in SMM at the time the SMI occurred,
// the pseudo register value for EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID is returned in Buffer.
@@ -273,6 +277,7 @@ SmmReadSaveState ( if (Status == EFI_UNSUPPORTED) {
Status = ReadSaveStateRegister (CpuIndex, Register, Width, Buffer);
}
+
return Status;
}
@@ -293,11 +298,11 @@ SmmReadSaveState ( EFI_STATUS
EFIAPI
SmmWriteSaveState (
- IN CONST EFI_SMM_CPU_PROTOCOL *This,
- IN UINTN Width,
- IN EFI_SMM_SAVE_STATE_REGISTER Register,
- IN UINTN CpuIndex,
- IN CONST VOID *Buffer
+ IN CONST EFI_SMM_CPU_PROTOCOL *This,
+ IN UINTN Width,
+ IN EFI_SMM_SAVE_STATE_REGISTER Register,
+ IN UINTN CpuIndex,
+ IN CONST VOID *Buffer
)
{
EFI_STATUS Status;
@@ -324,10 +329,10 @@ SmmWriteSaveState ( if (Status == EFI_UNSUPPORTED) {
Status = WriteSaveStateRegister (CpuIndex, Register, Width, Buffer);
}
+
return Status;
}
-
/**
C function for SMI handler. To change all processor's SMMBase Register.
@@ -338,8 +343,8 @@ SmmInitHandler ( VOID
)
{
- UINT32 ApicId;
- UINTN Index;
+ UINT32 ApicId;
+ UINTN Index;
//
// Update SMM IDT entries' code segment and load IDT
@@ -384,6 +389,7 @@ SmmInitHandler ( return;
}
}
+
ASSERT (FALSE);
}
@@ -427,7 +433,7 @@ SmmRelocateBases ( gcSmiInitGdtr.Base = gcSmiGdtr.Base;
gcSmiInitGdtr.Limit = gcSmiGdtr.Limit;
- U8Ptr = (UINT8*)(UINTN)(SMM_DEFAULT_SMBASE + SMM_HANDLER_OFFSET);
+ U8Ptr = (UINT8 *)(UINTN)(SMM_DEFAULT_SMBASE + SMM_HANDLER_OFFSET);
CpuStatePtr = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET);
//
@@ -459,7 +465,8 @@ SmmRelocateBases ( //
// Wait for this AP to finish its 1st SMI
//
- while (!mRebased[Index]);
+ while (!mRebased[Index]) {
+ }
} else {
//
// BSP will be Relocated later
@@ -477,7 +484,8 @@ SmmRelocateBases ( //
// Wait for the BSP to finish its 1st SMI
//
- while (!mRebased[BspIndex]);
+ while (!mRebased[BspIndex]) {
+ }
//
// Restore contents at address 0x38000
@@ -537,24 +545,24 @@ PiCpuSmmEntry ( IN EFI_SYSTEM_TABLE *SystemTable
)
{
- EFI_STATUS Status;
- EFI_MP_SERVICES_PROTOCOL *MpServices;
- UINTN NumberOfEnabledProcessors;
- UINTN Index;
- VOID *Buffer;
- UINTN BufferPages;
- UINTN TileCodeSize;
- UINTN TileDataSize;
- UINTN TileSize;
- UINT8 *Stacks;
- VOID *Registration;
- UINT32 RegEax;
- UINT32 RegEbx;
- UINT32 RegEcx;
- UINT32 RegEdx;
- UINTN FamilyId;
- UINTN ModelId;
- UINT32 Cr3;
+ EFI_STATUS Status;
+ EFI_MP_SERVICES_PROTOCOL *MpServices;
+ UINTN NumberOfEnabledProcessors;
+ UINTN Index;
+ VOID *Buffer;
+ UINTN BufferPages;
+ UINTN TileCodeSize;
+ UINTN TileDataSize;
+ UINTN TileSize;
+ UINT8 *Stacks;
+ VOID *Registration;
+ UINT32 RegEax;
+ UINT32 RegEbx;
+ UINT32 RegEcx;
+ UINT32 RegEdx;
+ UINTN FamilyId;
+ UINTN ModelId;
+ UINT32 Cr3;
//
// Initialize address fixup
@@ -598,10 +606,10 @@ PiCpuSmmEntry ( // A constant BSP index makes no sense because it may be hot removed.
//
DEBUG_CODE_BEGIN ();
- if (FeaturePcdGet (PcdCpuHotPlugSupport)) {
+ if (FeaturePcdGet (PcdCpuHotPlugSupport)) {
+ ASSERT (FeaturePcdGet (PcdCpuSmmEnableBspElection));
+ }
- ASSERT (FeaturePcdGet (PcdCpuSmmEnableBspElection));
- }
DEBUG_CODE_END ();
//
@@ -625,6 +633,7 @@ PiCpuSmmEntry ( } else {
mMaxNumberOfCpus = mNumberOfCpus;
}
+
gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus = mMaxNumberOfCpus;
//
@@ -702,8 +711,8 @@ PiCpuSmmEntry ( //
AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, NULL);
FamilyId = (RegEax >> 8) & 0xf;
- ModelId = (RegEax >> 4) & 0xf;
- if (FamilyId == 0x06 || FamilyId == 0x0f) {
+ ModelId = (RegEax >> 4) & 0xf;
+ if ((FamilyId == 0x06) || (FamilyId == 0x0f)) {
ModelId = ModelId | ((RegEax >> 12) & 0xf0);
}
@@ -712,6 +721,7 @@ PiCpuSmmEntry ( if (RegEax >= CPUID_EXTENDED_CPU_SIG) {
AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, NULL, &RegEdx);
}
+
//
// Determine the mode of the CPU at the time an SMI occurs
// Intel(R) 64 and IA-32 Architectures Software Developer's Manual
@@ -721,8 +731,9 @@ PiCpuSmmEntry ( if ((RegEdx & BIT29) != 0) {
mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT;
}
+
if (FamilyId == 0x06) {
- if (ModelId == 0x17 || ModelId == 0x0f || ModelId == 0x1c) {
+ if ((ModelId == 0x17) || (ModelId == 0x0f) || (ModelId == 0x1c)) {
mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT;
}
}
@@ -739,17 +750,18 @@ PiCpuSmmEntry ( mCetSupported = FALSE;
PatchInstructionX86 (mPatchCetSupported, mCetSupported, 1);
}
+
if (mCetSupported) {
AsmCpuidEx (CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_SUB_LEAF, NULL, &RegEbx, &RegEcx, NULL);
DEBUG ((DEBUG_INFO, "CPUID[D/1] EBX - 0x%08x, ECX - 0x%08x\n", RegEbx, RegEcx));
AsmCpuidEx (CPUID_EXTENDED_STATE, 11, &RegEax, NULL, &RegEcx, NULL);
DEBUG ((DEBUG_INFO, "CPUID[D/11] EAX - 0x%08x, ECX - 0x%08x\n", RegEax, RegEcx));
- AsmCpuidEx(CPUID_EXTENDED_STATE, 12, &RegEax, NULL, &RegEcx, NULL);
+ AsmCpuidEx (CPUID_EXTENDED_STATE, 12, &RegEax, NULL, &RegEcx, NULL);
DEBUG ((DEBUG_INFO, "CPUID[D/12] EAX - 0x%08x, ECX - 0x%08x\n", RegEax, RegEcx));
}
} else {
mCetSupported = FALSE;
- PatchInstructionX86(mPatchCetSupported, mCetSupported, 1);
+ PatchInstructionX86 (mPatchCetSupported, mCetSupported, 1);
}
} else {
mCetSupported = FALSE;
@@ -762,11 +774,11 @@ PiCpuSmmEntry ( // This size is rounded up to nearest power of 2.
//
TileCodeSize = GetSmiHandlerSize ();
- TileCodeSize = ALIGN_VALUE(TileCodeSize, SIZE_4KB);
+ TileCodeSize = ALIGN_VALUE (TileCodeSize, SIZE_4KB);
TileDataSize = (SMRAM_SAVE_STATE_MAP_OFFSET - SMM_PSD_OFFSET) + sizeof (SMRAM_SAVE_STATE_MAP);
- TileDataSize = ALIGN_VALUE(TileDataSize, SIZE_4KB);
- TileSize = TileDataSize + TileCodeSize - 1;
- TileSize = 2 * GetPowerOfTwo32 ((UINT32)TileSize);
+ TileDataSize = ALIGN_VALUE (TileDataSize, SIZE_4KB);
+ TileSize = TileDataSize + TileCodeSize - 1;
+ TileSize = 2 * GetPowerOfTwo32 ((UINT32)TileSize);
DEBUG ((DEBUG_INFO, "SMRAM TileSize = 0x%08x (0x%08x, 0x%08x)\n", TileSize, TileCodeSize, TileDataSize));
//
@@ -796,8 +808,9 @@ PiCpuSmmEntry ( } else {
Buffer = AllocateAlignedCodePages (BufferPages, SIZE_4KB);
}
+
ASSERT (Buffer != NULL);
- DEBUG ((DEBUG_INFO, "SMRAM SaveState Buffer (0x%08x, 0x%08x)\n", Buffer, EFI_PAGES_TO_SIZE(BufferPages)));
+ DEBUG ((DEBUG_INFO, "SMRAM SaveState Buffer (0x%08x, 0x%08x)\n", Buffer, EFI_PAGES_TO_SIZE (BufferPages)));
//
// Allocate buffer for pointers to array in SMM_CPU_PRIVATE_DATA.
@@ -832,17 +845,19 @@ PiCpuSmmEntry ( // size for each CPU in the platform
//
for (Index = 0; Index < mMaxNumberOfCpus; Index++) {
- mCpuHotPlugData.SmBase[Index] = (UINTN)Buffer + Index * TileSize - SMM_HANDLER_OFFSET;
- gSmmCpuPrivate->CpuSaveStateSize[Index] = sizeof(SMRAM_SAVE_STATE_MAP);
+ mCpuHotPlugData.SmBase[Index] = (UINTN)Buffer + Index * TileSize - SMM_HANDLER_OFFSET;
+ gSmmCpuPrivate->CpuSaveStateSize[Index] = sizeof (SMRAM_SAVE_STATE_MAP);
gSmmCpuPrivate->CpuSaveState[Index] = (VOID *)(mCpuHotPlugData.SmBase[Index] + SMRAM_SAVE_STATE_MAP_OFFSET);
- gSmmCpuPrivate->Operation[Index] = SmmCpuNone;
+ gSmmCpuPrivate->Operation[Index] = SmmCpuNone;
if (Index < mNumberOfCpus) {
Status = MpServices->GetProcessorInfo (MpServices, Index, &gSmmCpuPrivate->ProcessorInfo[Index]);
ASSERT_EFI_ERROR (Status);
mCpuHotPlugData.ApicId[Index] = gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId;
- DEBUG ((DEBUG_INFO, "CPU[%03x] APIC ID=%04x SMBASE=%08x SaveState=%08x Size=%08x\n",
+ DEBUG ((
+ DEBUG_INFO,
+ "CPU[%03x] APIC ID=%04x SMBASE=%08x SaveState=%08x Size=%08x\n",
Index,
(UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId,
mCpuHotPlugData.SmBase[Index],
@@ -851,7 +866,7 @@ PiCpuSmmEntry ( ));
} else {
gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId = INVALID_APIC_ID;
- mCpuHotPlugData.ApicId[Index] = INVALID_APIC_ID;
+ mCpuHotPlugData.ApicId[Index] = INVALID_APIC_ID;
}
}
@@ -916,10 +931,10 @@ PiCpuSmmEntry ( }
}
- Stacks = (UINT8 *) AllocatePages (gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus * (EFI_SIZE_TO_PAGES (mSmmStackSize + mSmmShadowStackSize)));
+ Stacks = (UINT8 *)AllocatePages (gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus * (EFI_SIZE_TO_PAGES (mSmmStackSize + mSmmShadowStackSize)));
ASSERT (Stacks != NULL);
mSmmStackArrayBase = (UINTN)Stacks;
- mSmmStackArrayEnd = mSmmStackArrayBase + gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus * (mSmmStackSize + mSmmShadowStackSize) - 1;
+ mSmmStackArrayEnd = mSmmStackArrayBase + gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus * (mSmmStackSize + mSmmShadowStackSize) - 1;
DEBUG ((DEBUG_INFO, "Stacks - 0x%x\n", Stacks));
DEBUG ((DEBUG_INFO, "mSmmStackSize - 0x%x\n", mSmmStackSize));
@@ -933,7 +948,7 @@ PiCpuSmmEntry ( //
PatchInstructionX86 (
gPatchSmmInitStack,
- (UINTN) (Stacks + mSmmStackSize - sizeof (UINTN)),
+ (UINTN)(Stacks + mSmmStackSize - sizeof (UINTN)),
sizeof (UINTN)
);
@@ -977,8 +992,8 @@ PiCpuSmmEntry ( if (FeaturePcdGet (PcdCpuSmmStackGuard)) {
SetNotPresentPage (
Cr3,
- (EFI_PHYSICAL_ADDRESS)(UINTN)Stacks + mSmmStackSize + EFI_PAGES_TO_SIZE(1) + (mSmmStackSize + mSmmShadowStackSize) * Index,
- EFI_PAGES_TO_SIZE(1)
+ (EFI_PHYSICAL_ADDRESS)(UINTN)Stacks + mSmmStackSize + EFI_PAGES_TO_SIZE (1) + (mSmmStackSize + mSmmShadowStackSize) * Index,
+ EFI_PAGES_TO_SIZE (1)
);
}
}
@@ -997,7 +1012,8 @@ PiCpuSmmEntry ( //
Status = SystemTable->BootServices->InstallMultipleProtocolInterfaces (
&gSmmCpuPrivate->SmmCpuHandle,
- &gEfiSmmConfigurationProtocolGuid, &gSmmCpuPrivate->SmmConfiguration,
+ &gEfiSmmConfigurationProtocolGuid,
+ &gSmmCpuPrivate->SmmConfiguration,
NULL
);
ASSERT_EFI_ERROR (Status);
@@ -1087,17 +1103,17 @@ PiCpuSmmEntry ( **/
VOID
FindSmramInfo (
- OUT UINT32 *SmrrBase,
- OUT UINT32 *SmrrSize
+ OUT UINT32 *SmrrBase,
+ OUT UINT32 *SmrrSize
)
{
- EFI_STATUS Status;
- UINTN Size;
- EFI_SMM_ACCESS2_PROTOCOL *SmmAccess;
- EFI_SMRAM_DESCRIPTOR *CurrentSmramRange;
- UINTN Index;
- UINT64 MaxSize;
- BOOLEAN Found;
+ EFI_STATUS Status;
+ UINTN Size;
+ EFI_SMM_ACCESS2_PROTOCOL *SmmAccess;
+ EFI_SMRAM_DESCRIPTOR *CurrentSmramRange;
+ UINTN Index;
+ UINT64 MaxSize;
+ BOOLEAN Found;
//
// Get SMM Access Protocol
@@ -1108,7 +1124,7 @@ FindSmramInfo ( //
// Get SMRAM information
//
- Size = 0;
+ Size = 0;
Status = SmmAccess->GetCapabilities (SmmAccess, &Size, NULL);
ASSERT (Status == EFI_BUFFER_TOO_SMALL);
@@ -1135,7 +1151,7 @@ FindSmramInfo ( if (mSmmCpuSmramRanges[Index].CpuStart >= BASE_1MB) {
if ((mSmmCpuSmramRanges[Index].CpuStart + mSmmCpuSmramRanges[Index].PhysicalSize) <= SMRR_MAX_ADDRESS) {
if (mSmmCpuSmramRanges[Index].PhysicalSize >= MaxSize) {
- MaxSize = mSmmCpuSmramRanges[Index].PhysicalSize;
+ MaxSize = mSmmCpuSmramRanges[Index].PhysicalSize;
CurrentSmramRange = &mSmmCpuSmramRanges[Index];
}
}
@@ -1150,14 +1166,15 @@ FindSmramInfo ( do {
Found = FALSE;
for (Index = 0; Index < mSmmCpuSmramRangeCount; Index++) {
- if (mSmmCpuSmramRanges[Index].CpuStart < *SmrrBase &&
- *SmrrBase == (mSmmCpuSmramRanges[Index].CpuStart + mSmmCpuSmramRanges[Index].PhysicalSize)) {
+ if ((mSmmCpuSmramRanges[Index].CpuStart < *SmrrBase) &&
+ (*SmrrBase == (mSmmCpuSmramRanges[Index].CpuStart + mSmmCpuSmramRanges[Index].PhysicalSize)))
+ {
*SmrrBase = (UINT32)mSmmCpuSmramRanges[Index].CpuStart;
*SmrrSize = (UINT32)(*SmrrSize + mSmmCpuSmramRanges[Index].PhysicalSize);
- Found = TRUE;
- } else if ((*SmrrBase + *SmrrSize) == mSmmCpuSmramRanges[Index].CpuStart && mSmmCpuSmramRanges[Index].PhysicalSize > 0) {
+ Found = TRUE;
+ } else if (((*SmrrBase + *SmrrSize) == mSmmCpuSmramRanges[Index].CpuStart) && (mSmmCpuSmramRanges[Index].PhysicalSize > 0)) {
*SmrrSize = (UINT32)(*SmrrSize + mSmmCpuSmramRanges[Index].PhysicalSize);
- Found = TRUE;
+ Found = TRUE;
}
}
} while (Found);
@@ -1272,6 +1289,7 @@ ConfigSmmCodeAccessCheck ( //
continue;
}
+
//
// Acquire Config SMM Code Access Check spin lock. The AP will release the
// spin lock when it is done executing ConfigSmmCodeAccessCheckOnCurrentProcessor().
@@ -1316,7 +1334,7 @@ ConfigSmmCodeAccessCheck ( **/
VOID *
AllocatePageTableMemory (
- IN UINTN Pages
+ IN UINTN Pages
)
{
VOID *Buffer;
@@ -1325,6 +1343,7 @@ AllocatePageTableMemory ( if (Buffer != NULL) {
return Buffer;
}
+
return AllocatePages (Pages);
}
@@ -1337,7 +1356,7 @@ AllocatePageTableMemory ( **/
VOID *
AllocateCodePages (
- IN UINTN Pages
+ IN UINTN Pages
)
{
EFI_STATUS Status;
@@ -1351,7 +1370,8 @@ AllocateCodePages ( if (EFI_ERROR (Status)) {
return NULL;
}
- return (VOID *) (UINTN) Memory;
+
+ return (VOID *)(UINTN)Memory;
}
/**
@@ -1366,8 +1386,8 @@ AllocateCodePages ( **/
VOID *
AllocateAlignedCodePages (
- IN UINTN Pages,
- IN UINTN Alignment
+ IN UINTN Pages,
+ IN UINTN Alignment
)
{
EFI_STATUS Status;
@@ -1385,23 +1405,25 @@ AllocateAlignedCodePages ( if (Pages == 0) {
return NULL;
}
+
if (Alignment > EFI_PAGE_SIZE) {
//
// Calculate the total number of pages since alignment is larger than page size.
//
- AlignmentMask = Alignment - 1;
- RealPages = Pages + EFI_SIZE_TO_PAGES (Alignment);
+ AlignmentMask = Alignment - 1;
+ RealPages = Pages + EFI_SIZE_TO_PAGES (Alignment);
//
// Make sure that Pages plus EFI_SIZE_TO_PAGES (Alignment) does not overflow.
//
ASSERT (RealPages > Pages);
- Status = gSmst->SmmAllocatePages (AllocateAnyPages, EfiRuntimeServicesCode, RealPages, &Memory);
+ Status = gSmst->SmmAllocatePages (AllocateAnyPages, EfiRuntimeServicesCode, RealPages, &Memory);
if (EFI_ERROR (Status)) {
return NULL;
}
- AlignedMemory = ((UINTN) Memory + AlignmentMask) & ~AlignmentMask;
- UnalignedPages = EFI_SIZE_TO_PAGES (AlignedMemory - (UINTN) Memory);
+
+ AlignedMemory = ((UINTN)Memory + AlignmentMask) & ~AlignmentMask;
+ UnalignedPages = EFI_SIZE_TO_PAGES (AlignedMemory - (UINTN)Memory);
if (UnalignedPages > 0) {
//
// Free first unaligned page(s).
@@ -1409,6 +1431,7 @@ AllocateAlignedCodePages ( Status = gSmst->SmmFreePages (Memory, UnalignedPages);
ASSERT_EFI_ERROR (Status);
}
+
Memory = AlignedMemory + EFI_PAGES_TO_SIZE (Pages);
UnalignedPages = RealPages - Pages - UnalignedPages;
if (UnalignedPages > 0) {
@@ -1426,9 +1449,11 @@ AllocateAlignedCodePages ( if (EFI_ERROR (Status)) {
return NULL;
}
- AlignedMemory = (UINTN) Memory;
+
+ AlignedMemory = (UINTN)Memory;
}
- return (VOID *) AlignedMemory;
+
+ return (VOID *)AlignedMemory;
}
/**
@@ -1447,6 +1472,7 @@ PerformRemainingTasks ( if (FeaturePcdGet (PcdCpuSmmProfileEnable)) {
SmmProfileStart ();
}
+
//
// Create a mix of 2MB and 4KB page table. Update some memory ranges absent and execute-disable.
//
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h index fc9b748948..26d07c5b5e 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h @@ -74,69 +74,69 @@ SPDX-License-Identifier: BSD-2-Clause-Patent typedef union {
struct {
// enable shadow stacks
- UINT32 SH_STK_ENP:1;
+ UINT32 SH_STK_ENP : 1;
// enable the WRSS{D,Q}W instructions.
- UINT32 WR_SHSTK_EN:1;
+ UINT32 WR_SHSTK_EN : 1;
// enable tracking of indirect call/jmp targets to be ENDBRANCH instruction.
- UINT32 ENDBR_EN:1;
+ UINT32 ENDBR_EN : 1;
// enable legacy compatibility treatment for indirect call/jmp tracking.
- UINT32 LEG_IW_EN:1;
+ UINT32 LEG_IW_EN : 1;
// enable use of no-track prefix on indirect call/jmp.
- UINT32 NO_TRACK_EN:1;
+ UINT32 NO_TRACK_EN : 1;
// disable suppression of CET indirect branch tracking on legacy compatibility.
- UINT32 SUPPRESS_DIS:1;
- UINT32 RSVD:4;
+ UINT32 SUPPRESS_DIS : 1;
+ UINT32 RSVD : 4;
// indirect branch tracking is suppressed.
// This bit can be written to 1 only if TRACKER is written as IDLE.
- UINT32 SUPPRESS:1;
+ UINT32 SUPPRESS : 1;
// Value of the endbranch state machine
// Values: IDLE (0), WAIT_FOR_ENDBRANCH(1).
- UINT32 TRACKER:1;
+ UINT32 TRACKER : 1;
// linear address of a bitmap in memory indicating valid
// pages as target of CALL/JMP_indirect that do not land on ENDBRANCH when CET is enabled
// and not suppressed. Valid when ENDBR_EN is 1. Must be machine canonical when written on
// parts that support 64 bit mode. On parts that do not support 64 bit mode, the bits 63:32 are
// reserved and must be 0. This value is extended by 12 bits at the low end to form the base address
// (this automatically aligns the address on a 4-Kbyte boundary).
- UINT32 EB_LEG_BITMAP_BASE_low:12;
- UINT32 EB_LEG_BITMAP_BASE_high:32;
+ UINT32 EB_LEG_BITMAP_BASE_low : 12;
+ UINT32 EB_LEG_BITMAP_BASE_high : 32;
} Bits;
- UINT64 Uint64;
+ UINT64 Uint64;
} MSR_IA32_CET;
//
// MSRs required for configuration of SMM Code Access Check
//
-#define EFI_MSR_SMM_MCA_CAP 0x17D
-#define SMM_CODE_ACCESS_CHK_BIT BIT58
+#define EFI_MSR_SMM_MCA_CAP 0x17D
+#define SMM_CODE_ACCESS_CHK_BIT BIT58
-#define SMM_FEATURE_CONTROL_LOCK_BIT BIT0
-#define SMM_CODE_CHK_EN_BIT BIT2
+#define SMM_FEATURE_CONTROL_LOCK_BIT BIT0
+#define SMM_CODE_CHK_EN_BIT BIT2
///
/// Page Table Entry
///
-#define IA32_PG_P BIT0
-#define IA32_PG_RW BIT1
-#define IA32_PG_U BIT2
-#define IA32_PG_WT BIT3
-#define IA32_PG_CD BIT4
-#define IA32_PG_A BIT5
-#define IA32_PG_D BIT6
-#define IA32_PG_PS BIT7
-#define IA32_PG_PAT_2M BIT12
-#define IA32_PG_PAT_4K IA32_PG_PS
-#define IA32_PG_PMNT BIT62
-#define IA32_PG_NX BIT63
-
-#define PAGE_ATTRIBUTE_BITS (IA32_PG_D | IA32_PG_A | IA32_PG_U | IA32_PG_RW | IA32_PG_P)
+#define IA32_PG_P BIT0
+#define IA32_PG_RW BIT1
+#define IA32_PG_U BIT2
+#define IA32_PG_WT BIT3
+#define IA32_PG_CD BIT4
+#define IA32_PG_A BIT5
+#define IA32_PG_D BIT6
+#define IA32_PG_PS BIT7
+#define IA32_PG_PAT_2M BIT12
+#define IA32_PG_PAT_4K IA32_PG_PS
+#define IA32_PG_PMNT BIT62
+#define IA32_PG_NX BIT63
+
+#define PAGE_ATTRIBUTE_BITS (IA32_PG_D | IA32_PG_A | IA32_PG_U | IA32_PG_RW | IA32_PG_P)
//
// Bits 1, 2, 5, 6 are reserved in the IA32 PAE PDPTE
// X64 PAE PDPTE does not have such restriction
//
-#define IA32_PAE_PDPTE_ATTRIBUTE_BITS (IA32_PG_P)
+#define IA32_PAE_PDPTE_ATTRIBUTE_BITS (IA32_PG_P)
-#define PAGE_PROGATE_BITS (IA32_PG_NX | PAGE_ATTRIBUTE_BITS)
+#define PAGE_PROGATE_BITS (IA32_PG_NX | PAGE_ATTRIBUTE_BITS)
#define PAGING_4K_MASK 0xFFF
#define PAGING_2M_MASK 0x1FFFFF
@@ -144,11 +144,11 @@ typedef union { #define PAGING_PAE_INDEX_MASK 0x1FF
-#define PAGING_4K_ADDRESS_MASK_64 0x000FFFFFFFFFF000ull
-#define PAGING_2M_ADDRESS_MASK_64 0x000FFFFFFFE00000ull
-#define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull
+#define PAGING_4K_ADDRESS_MASK_64 0x000FFFFFFFFFF000ull
+#define PAGING_2M_ADDRESS_MASK_64 0x000FFFFFFFE00000ull
+#define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull
-#define SMRR_MAX_ADDRESS BASE_4GB
+#define SMRR_MAX_ADDRESS BASE_4GB
typedef enum {
PageNone,
@@ -158,28 +158,28 @@ typedef enum { } PAGE_ATTRIBUTE;
typedef struct {
- PAGE_ATTRIBUTE Attribute;
- UINT64 Length;
- UINT64 AddressMask;
+ PAGE_ATTRIBUTE Attribute;
+ UINT64 Length;
+ UINT64 AddressMask;
} PAGE_ATTRIBUTE_TABLE;
//
// Size of Task-State Segment defined in IA32 Manual
//
-#define TSS_SIZE 104
-#define EXCEPTION_TSS_SIZE (TSS_SIZE + 4) // Add 4 bytes SSP
-#define TSS_X64_IST1_OFFSET 36
-#define TSS_IA32_CR3_OFFSET 28
-#define TSS_IA32_ESP_OFFSET 56
-#define TSS_IA32_SSP_OFFSET 104
+#define TSS_SIZE 104
+#define EXCEPTION_TSS_SIZE (TSS_SIZE + 4) // Add 4 bytes SSP
+#define TSS_X64_IST1_OFFSET 36
+#define TSS_IA32_CR3_OFFSET 28
+#define TSS_IA32_ESP_OFFSET 56
+#define TSS_IA32_SSP_OFFSET 104
-#define CR0_WP BIT16
+#define CR0_WP BIT16
//
// Code select value
//
-#define PROTECT_MODE_CODE_SEGMENT 0x08
-#define LONG_MODE_CODE_SEGMENT 0x38
+#define PROTECT_MODE_CODE_SEGMENT 0x08
+#define LONG_MODE_CODE_SEGMENT 0x38
//
// The size 0x20 must be bigger than
@@ -189,31 +189,31 @@ typedef struct { //
#define BACK_BUF_SIZE 0x20
-#define EXCEPTION_VECTOR_NUMBER 0x20
+#define EXCEPTION_VECTOR_NUMBER 0x20
-#define INVALID_APIC_ID 0xFFFFFFFFFFFFFFFFULL
+#define INVALID_APIC_ID 0xFFFFFFFFFFFFFFFFULL
-typedef UINT32 SMM_CPU_ARRIVAL_EXCEPTIONS;
-#define ARRIVAL_EXCEPTION_BLOCKED 0x1
-#define ARRIVAL_EXCEPTION_DELAYED 0x2
-#define ARRIVAL_EXCEPTION_SMI_DISABLED 0x4
+typedef UINT32 SMM_CPU_ARRIVAL_EXCEPTIONS;
+#define ARRIVAL_EXCEPTION_BLOCKED 0x1
+#define ARRIVAL_EXCEPTION_DELAYED 0x2
+#define ARRIVAL_EXCEPTION_SMI_DISABLED 0x4
//
// Wrapper used to convert EFI_AP_PROCEDURE2 and EFI_AP_PROCEDURE.
//
typedef struct {
- EFI_AP_PROCEDURE Procedure;
- VOID *ProcedureArgument;
+ EFI_AP_PROCEDURE Procedure;
+ VOID *ProcedureArgument;
} PROCEDURE_WRAPPER;
#define PROCEDURE_TOKEN_SIGNATURE SIGNATURE_32 ('P', 'R', 'T', 'S')
typedef struct {
- UINTN Signature;
- LIST_ENTRY Link;
+ UINTN Signature;
+ LIST_ENTRY Link;
- SPIN_LOCK *SpinLock;
- volatile UINT32 RunningApCount;
+ SPIN_LOCK *SpinLock;
+ volatile UINT32 RunningApCount;
} PROCEDURE_TOKEN;
#define PROCEDURE_TOKEN_FROM_LINK(a) CR (a, PROCEDURE_TOKEN, Link, PROCEDURE_TOKEN_SIGNATURE)
@@ -221,10 +221,10 @@ typedef struct { #define TOKEN_BUFFER_SIGNATURE SIGNATURE_32 ('T', 'K', 'B', 'S')
typedef struct {
- UINTN Signature;
- LIST_ENTRY Link;
+ UINTN Signature;
+ LIST_ENTRY Link;
- UINT8 *Buffer;
+ UINT8 *Buffer;
} TOKEN_BUFFER;
#define TOKEN_BUFFER_FROM_LINK(a) CR (a, TOKEN_BUFFER, Link, TOKEN_BUFFER_SIGNATURE)
@@ -237,33 +237,33 @@ typedef struct { #define SMM_CPU_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('s', 'c', 'p', 'u')
typedef struct {
- UINTN Signature;
+ UINTN Signature;
- EFI_HANDLE SmmCpuHandle;
+ EFI_HANDLE SmmCpuHandle;
- EFI_PROCESSOR_INFORMATION *ProcessorInfo;
- SMM_CPU_OPERATION *Operation;
- UINTN *CpuSaveStateSize;
- VOID **CpuSaveState;
+ EFI_PROCESSOR_INFORMATION *ProcessorInfo;
+ SMM_CPU_OPERATION *Operation;
+ UINTN *CpuSaveStateSize;
+ VOID **CpuSaveState;
- EFI_SMM_RESERVED_SMRAM_REGION SmmReservedSmramRegion[1];
- EFI_SMM_ENTRY_CONTEXT SmmCoreEntryContext;
- EFI_SMM_ENTRY_POINT SmmCoreEntry;
+ EFI_SMM_RESERVED_SMRAM_REGION SmmReservedSmramRegion[1];
+ EFI_SMM_ENTRY_CONTEXT SmmCoreEntryContext;
+ EFI_SMM_ENTRY_POINT SmmCoreEntry;
- EFI_SMM_CONFIGURATION_PROTOCOL SmmConfiguration;
+ EFI_SMM_CONFIGURATION_PROTOCOL SmmConfiguration;
- PROCEDURE_WRAPPER *ApWrapperFunc;
- LIST_ENTRY TokenList;
- LIST_ENTRY *FirstFreeToken;
+ PROCEDURE_WRAPPER *ApWrapperFunc;
+ LIST_ENTRY TokenList;
+ LIST_ENTRY *FirstFreeToken;
} SMM_CPU_PRIVATE_DATA;
extern SMM_CPU_PRIVATE_DATA *gSmmCpuPrivate;
-extern CPU_HOT_PLUG_DATA mCpuHotPlugData;
-extern UINTN mMaxNumberOfCpus;
-extern UINTN mNumberOfCpus;
-extern EFI_SMM_CPU_PROTOCOL mSmmCpu;
-extern EFI_MM_MP_PROTOCOL mSmmMp;
-extern UINTN mInternalCr3;
+extern CPU_HOT_PLUG_DATA mCpuHotPlugData;
+extern UINTN mMaxNumberOfCpus;
+extern UINTN mNumberOfCpus;
+extern EFI_SMM_CPU_PROTOCOL mSmmCpu;
+extern EFI_MM_MP_PROTOCOL mSmmMp;
+extern UINTN mInternalCr3;
///
/// The mode of the CPU at the time an SMI occurs
@@ -291,11 +291,11 @@ extern UINT8 mSmmSaveStateRegisterLma; EFI_STATUS
EFIAPI
SmmReadSaveState (
- IN CONST EFI_SMM_CPU_PROTOCOL *This,
- IN UINTN Width,
- IN EFI_SMM_SAVE_STATE_REGISTER Register,
- IN UINTN CpuIndex,
- OUT VOID *Buffer
+ IN CONST EFI_SMM_CPU_PROTOCOL *This,
+ IN UINTN Width,
+ IN EFI_SMM_SAVE_STATE_REGISTER Register,
+ IN UINTN CpuIndex,
+ OUT VOID *Buffer
);
/**
@@ -315,11 +315,11 @@ SmmReadSaveState ( EFI_STATUS
EFIAPI
SmmWriteSaveState (
- IN CONST EFI_SMM_CPU_PROTOCOL *This,
- IN UINTN Width,
- IN EFI_SMM_SAVE_STATE_REGISTER Register,
- IN UINTN CpuIndex,
- IN CONST VOID *Buffer
+ IN CONST EFI_SMM_CPU_PROTOCOL *This,
+ IN UINTN Width,
+ IN EFI_SMM_SAVE_STATE_REGISTER Register,
+ IN UINTN CpuIndex,
+ IN CONST VOID *Buffer
);
/**
@@ -376,16 +376,16 @@ WriteSaveStateRegister ( IN CONST VOID *Buffer
);
-extern CONST UINT8 gcSmmInitTemplate[];
-extern CONST UINT16 gcSmmInitSize;
-X86_ASSEMBLY_PATCH_LABEL gPatchSmmCr0;
-extern UINT32 mSmmCr0;
-X86_ASSEMBLY_PATCH_LABEL gPatchSmmCr3;
-extern UINT32 mSmmCr4;
-X86_ASSEMBLY_PATCH_LABEL gPatchSmmCr4;
-X86_ASSEMBLY_PATCH_LABEL gPatchSmmInitStack;
-X86_ASSEMBLY_PATCH_LABEL mPatchCetSupported;
-extern BOOLEAN mCetSupported;
+extern CONST UINT8 gcSmmInitTemplate[];
+extern CONST UINT16 gcSmmInitSize;
+X86_ASSEMBLY_PATCH_LABEL gPatchSmmCr0;
+extern UINT32 mSmmCr0;
+X86_ASSEMBLY_PATCH_LABEL gPatchSmmCr3;
+extern UINT32 mSmmCr4;
+X86_ASSEMBLY_PATCH_LABEL gPatchSmmCr4;
+X86_ASSEMBLY_PATCH_LABEL gPatchSmmInitStack;
+X86_ASSEMBLY_PATCH_LABEL mPatchCetSupported;
+extern BOOLEAN mCetSupported;
/**
Semaphore operation for all processor relocate SMMBase.
@@ -400,13 +400,13 @@ SmmRelocationSemaphoreComplete ( /// The type of SMM CPU Information
///
typedef struct {
- SPIN_LOCK *Busy;
- volatile EFI_AP_PROCEDURE2 Procedure;
- volatile VOID *Parameter;
- volatile UINT32 *Run;
- volatile BOOLEAN *Present;
- PROCEDURE_TOKEN *Token;
- EFI_STATUS *Status;
+ SPIN_LOCK *Busy;
+ volatile EFI_AP_PROCEDURE2 Procedure;
+ volatile VOID *Parameter;
+ volatile UINT32 *Run;
+ volatile BOOLEAN *Present;
+ PROCEDURE_TOKEN *Token;
+ EFI_STATUS *Status;
} SMM_CPU_DATA_BLOCK;
typedef enum {
@@ -432,56 +432,56 @@ typedef struct { VOID *StartupProcArgs;
} SMM_DISPATCHER_MP_SYNC_DATA;
-#define SMM_PSD_OFFSET 0xfb00
+#define SMM_PSD_OFFSET 0xfb00
///
/// All global semaphores' pointer
///
typedef struct {
- volatile UINT32 *Counter;
- volatile BOOLEAN *InsideSmm;
- volatile BOOLEAN *AllCpusInSync;
- SPIN_LOCK *PFLock;
- SPIN_LOCK *CodeAccessCheckLock;
+ volatile UINT32 *Counter;
+ volatile BOOLEAN *InsideSmm;
+ volatile BOOLEAN *AllCpusInSync;
+ SPIN_LOCK *PFLock;
+ SPIN_LOCK *CodeAccessCheckLock;
} SMM_CPU_SEMAPHORE_GLOBAL;
///
/// All semaphores for each processor
///
typedef struct {
- SPIN_LOCK *Busy;
- volatile UINT32 *Run;
- volatile BOOLEAN *Present;
- SPIN_LOCK *Token;
+ SPIN_LOCK *Busy;
+ volatile UINT32 *Run;
+ volatile BOOLEAN *Present;
+ SPIN_LOCK *Token;
} SMM_CPU_SEMAPHORE_CPU;
///
/// All semaphores' information
///
typedef struct {
- SMM_CPU_SEMAPHORE_GLOBAL SemaphoreGlobal;
- SMM_CPU_SEMAPHORE_CPU SemaphoreCpu;
+ SMM_CPU_SEMAPHORE_GLOBAL SemaphoreGlobal;
+ SMM_CPU_SEMAPHORE_CPU SemaphoreCpu;
} SMM_CPU_SEMAPHORES;
-extern IA32_DESCRIPTOR gcSmiGdtr;
-extern EFI_PHYSICAL_ADDRESS mGdtBuffer;
-extern UINTN mGdtBufferSize;
-extern IA32_DESCRIPTOR gcSmiIdtr;
-extern VOID *gcSmiIdtrPtr;
-extern UINT64 gPhyMask;
-extern SMM_DISPATCHER_MP_SYNC_DATA *mSmmMpSyncData;
-extern UINTN mSmmStackArrayBase;
-extern UINTN mSmmStackArrayEnd;
-extern UINTN mSmmStackSize;
-extern EFI_SMM_CPU_SERVICE_PROTOCOL mSmmCpuService;
-extern IA32_DESCRIPTOR gcSmiInitGdtr;
-extern SMM_CPU_SEMAPHORES mSmmCpuSemaphores;
-extern UINTN mSemaphoreSize;
-extern SPIN_LOCK *mPFLock;
-extern SPIN_LOCK *mConfigSmmCodeAccessCheckLock;
-extern EFI_SMRAM_DESCRIPTOR *mSmmCpuSmramRanges;
-extern UINTN mSmmCpuSmramRangeCount;
-extern UINT8 mPhysicalAddressBits;
+extern IA32_DESCRIPTOR gcSmiGdtr;
+extern EFI_PHYSICAL_ADDRESS mGdtBuffer;
+extern UINTN mGdtBufferSize;
+extern IA32_DESCRIPTOR gcSmiIdtr;
+extern VOID *gcSmiIdtrPtr;
+extern UINT64 gPhyMask;
+extern SMM_DISPATCHER_MP_SYNC_DATA *mSmmMpSyncData;
+extern UINTN mSmmStackArrayBase;
+extern UINTN mSmmStackArrayEnd;
+extern UINTN mSmmStackSize;
+extern EFI_SMM_CPU_SERVICE_PROTOCOL mSmmCpuService;
+extern IA32_DESCRIPTOR gcSmiInitGdtr;
+extern SMM_CPU_SEMAPHORES mSmmCpuSemaphores;
+extern UINTN mSemaphoreSize;
+extern SPIN_LOCK *mPFLock;
+extern SPIN_LOCK *mConfigSmmCodeAccessCheckLock;
+extern EFI_SMRAM_DESCRIPTOR *mSmmCpuSmramRanges;
+extern UINTN mSmmCpuSmramRangeCount;
+extern UINT8 mPhysicalAddressBits;
//
// Copy of the PcdPteMemoryEncryptionAddressOrMask
@@ -497,10 +497,9 @@ extern UINT64 mAddressEncMask; **/
UINT32
Gen4GPageTable (
- IN BOOLEAN Is32BitPageTable
+ IN BOOLEAN Is32BitPageTable
);
-
/**
Initialize global data for MP synchronization.
@@ -511,9 +510,9 @@ Gen4GPageTable ( **/
UINT32
InitializeMpServiceData (
- IN VOID *Stacks,
- IN UINTN StackSize,
- IN UINTN ShadowStackSize
+ IN VOID *Stacks,
+ IN UINTN StackSize,
+ IN UINTN ShadowStackSize
);
/**
@@ -544,7 +543,7 @@ StartSyncTimer ( BOOLEAN
EFIAPI
IsSyncTimerTimeout (
- IN UINT64 Timer
+ IN UINT64 Timer
);
/**
@@ -567,8 +566,8 @@ InitializeIDTSmmStackGuard ( VOID
EFIAPI
InitializeIdtIst (
- IN EFI_EXCEPTION_TYPE ExceptionType,
- IN UINT8 Ist
+ IN EFI_EXCEPTION_TYPE ExceptionType,
+ IN UINT8 Ist
);
/**
@@ -631,9 +630,9 @@ SmmInitPageTable ( EFI_STATUS
EFIAPI
SmmStartupThisAp (
- IN EFI_AP_PROCEDURE Procedure,
- IN UINTN CpuIndex,
- IN OUT VOID *ProcArguments OPTIONAL
+ IN EFI_AP_PROCEDURE Procedure,
+ IN UINTN CpuIndex,
+ IN OUT VOID *ProcArguments OPTIONAL
);
/**
@@ -653,9 +652,9 @@ SmmStartupThisAp ( EFI_STATUS
EFIAPI
SmmBlockingStartupThisAp (
- IN EFI_AP_PROCEDURE Procedure,
- IN UINTN CpuIndex,
- IN OUT VOID *ProcArguments OPTIONAL
+ IN EFI_AP_PROCEDURE Procedure,
+ IN UINTN CpuIndex,
+ IN OUT VOID *ProcArguments OPTIONAL
);
/**
@@ -683,9 +682,9 @@ SmmBlockingStartupThisAp ( EFI_STATUS
EFIAPI
SmmSetMemoryAttributes (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length,
- IN UINT64 Attributes
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN UINT64 Attributes
);
/**
@@ -713,9 +712,9 @@ SmmSetMemoryAttributes ( EFI_STATUS
EFIAPI
SmmClearMemoryAttributes (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length,
- IN UINT64 Attributes
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN UINT64 Attributes
);
/**
@@ -738,8 +737,8 @@ InitializeMpSyncData ( **/
VOID
FindSmramInfo (
- OUT UINT32 *SmrrBase,
- OUT UINT32 *SmrrSize
+ OUT UINT32 *SmrrBase,
+ OUT UINT32 *SmrrSize
);
/**
@@ -765,8 +764,8 @@ SmmRelocateBases ( VOID
EFIAPI
SmiPFHandler (
- IN EFI_EXCEPTION_TYPE InterruptType,
- IN EFI_SYSTEM_CONTEXT SystemContext
+ IN EFI_EXCEPTION_TYPE InterruptType,
+ IN EFI_SYSTEM_CONTEXT SystemContext
);
/**
@@ -795,7 +794,7 @@ PerformPreTasks ( **/
VOID
InitMsrSpinLockByIndex (
- IN UINT32 MsrIndex
+ IN UINT32 MsrIndex
);
/**
@@ -908,7 +907,7 @@ InstallSmiHandler ( **/
VOID
DumpModuleInfoByIp (
- IN UINTN CallerIpAddress
+ IN UINTN CallerIpAddress
);
/**
@@ -964,8 +963,8 @@ SetPageTableAttributes ( **/
VOID
GetPageTable (
- OUT UINTN *Base,
- OUT BOOLEAN *FiveLevels OPTIONAL
+ OUT UINTN *Base,
+ OUT BOOLEAN *FiveLevels OPTIONAL
);
/**
@@ -994,10 +993,10 @@ GetPageTable ( EFI_STATUS
EFIAPI
SmmSetMemoryAttributesEx (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length,
- IN UINT64 Attributes,
- OUT BOOLEAN *IsSplitted OPTIONAL
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN UINT64 Attributes,
+ OUT BOOLEAN *IsSplitted OPTIONAL
);
/**
@@ -1026,10 +1025,10 @@ SmmSetMemoryAttributesEx ( EFI_STATUS
EFIAPI
SmmClearMemoryAttributesEx (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length,
- IN UINT64 Attributes,
- OUT BOOLEAN *IsSplitted OPTIONAL
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN UINT64 Attributes,
+ OUT BOOLEAN *IsSplitted OPTIONAL
);
/**
@@ -1049,7 +1048,7 @@ SmmClearMemoryAttributesEx ( **/
VOID *
AllocatePageTableMemory (
- IN UINTN Pages
+ IN UINTN Pages
);
/**
@@ -1061,7 +1060,7 @@ AllocatePageTableMemory ( **/
VOID *
AllocateCodePages (
- IN UINTN Pages
+ IN UINTN Pages
);
/**
@@ -1076,16 +1075,15 @@ AllocateCodePages ( **/
VOID *
AllocateAlignedCodePages (
- IN UINTN Pages,
- IN UINTN Alignment
+ IN UINTN Pages,
+ IN UINTN Alignment
);
-
//
// S3 related global variable and function prototype.
//
-extern BOOLEAN mSmmS3Flag;
+extern BOOLEAN mSmmS3Flag;
/**
Initialize SMM S3 resume state structure used during S3 Resume.
@@ -1151,9 +1149,9 @@ TransferApToSafeState ( **/
EFI_STATUS
SetShadowStack (
- IN UINTN Cr3,
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length
+ IN UINTN Cr3,
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
);
/**
@@ -1167,9 +1165,9 @@ SetShadowStack ( **/
EFI_STATUS
SetNotPresentPage (
- IN UINTN Cr3,
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length
+ IN UINTN Cr3,
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
);
/**
@@ -1210,10 +1208,10 @@ InitShadowStack ( EFI_STATUS
EFIAPI
EdkiiSmmSetMemoryAttributes (
- IN EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL *This,
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length,
- IN UINT64 Attributes
+ IN EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL *This,
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN UINT64 Attributes
);
/**
@@ -1242,10 +1240,10 @@ EdkiiSmmSetMemoryAttributes ( EFI_STATUS
EFIAPI
EdkiiSmmClearMemoryAttributes (
- IN EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL *This,
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length,
- IN UINT64 Attributes
+ IN EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL *This,
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN UINT64 Attributes
);
/**
@@ -1272,10 +1270,10 @@ EdkiiSmmClearMemoryAttributes ( EFI_STATUS
EFIAPI
EdkiiSmmGetMemoryAttributes (
- IN EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL *This,
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length,
- IN UINT64 *Attributes
+ IN EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL *This,
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN UINT64 *Attributes
);
/**
@@ -1285,7 +1283,7 @@ EdkiiSmmGetMemoryAttributes ( VOID
EFIAPI
PiSmmCpuSmmInitFixupAddress (
- );
+ );
/**
This function fixes up the address of the global variable or function
@@ -1294,7 +1292,7 @@ PiSmmCpuSmmInitFixupAddress ( VOID
EFIAPI
PiSmmCpuSmiEntryFixupAddress (
- );
+ );
/**
This function reads CR2 register when on-demand paging is enabled
@@ -1355,12 +1353,12 @@ RestoreCr2 ( **/
EFI_STATUS
InternalSmmStartupThisAp (
- IN EFI_AP_PROCEDURE2 Procedure,
- IN UINTN CpuIndex,
- IN OUT VOID *ProcArguments OPTIONAL,
- IN OUT MM_COMPLETION *Token,
- IN UINTN TimeoutInMicroseconds,
- IN OUT EFI_STATUS *CpuStatus
+ IN EFI_AP_PROCEDURE2 Procedure,
+ IN UINTN CpuIndex,
+ IN OUT VOID *ProcArguments OPTIONAL,
+ IN OUT MM_COMPLETION *Token,
+ IN UINTN TimeoutInMicroseconds,
+ IN OUT EFI_STATUS *CpuStatus
);
/**
@@ -1374,7 +1372,7 @@ InternalSmmStartupThisAp ( **/
BOOLEAN
IsTokenInUse (
- IN SPIN_LOCK *Token
+ IN SPIN_LOCK *Token
);
/**
@@ -1405,7 +1403,7 @@ IsApReady ( **/
BOOLEAN
IsPresentAp (
- IN UINTN CpuIndex
+ IN UINTN CpuIndex
);
/**
@@ -1439,11 +1437,11 @@ IsPresentAp ( **/
EFI_STATUS
InternalSmmStartupAllAPs (
- IN EFI_AP_PROCEDURE2 Procedure,
- IN UINTN TimeoutInMicroseconds,
- IN OUT VOID *ProcedureArguments OPTIONAL,
- IN OUT MM_COMPLETION *Token,
- IN OUT EFI_STATUS *CPUStatus
+ IN EFI_AP_PROCEDURE2 Procedure,
+ IN UINTN TimeoutInMicroseconds,
+ IN OUT VOID *ProcedureArguments OPTIONAL,
+ IN OUT MM_COMPLETION *Token,
+ IN OUT EFI_STATUS *CPUStatus
);
/**
@@ -1466,8 +1464,8 @@ InternalSmmStartupAllAPs ( **/
EFI_STATUS
RegisterStartupProcedure (
- IN EFI_AP_PROCEDURE Procedure,
- IN OUT VOID *ProcedureArguments OPTIONAL
+ IN EFI_AP_PROCEDURE Procedure,
+ IN OUT VOID *ProcedureArguments OPTIONAL
);
/**
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c index 12dde85cf1..1f7cc15727 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c @@ -17,19 +17,19 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #define PREVIOUS_MEMORY_DESCRIPTOR(MemoryDescriptor, Size) \
((EFI_MEMORY_DESCRIPTOR *)((UINT8 *)(MemoryDescriptor) - (Size)))
-EFI_MEMORY_DESCRIPTOR *mUefiMemoryMap;
-UINTN mUefiMemoryMapSize;
-UINTN mUefiDescriptorSize;
+EFI_MEMORY_DESCRIPTOR *mUefiMemoryMap;
+UINTN mUefiMemoryMapSize;
+UINTN mUefiDescriptorSize;
-EFI_GCD_MEMORY_SPACE_DESCRIPTOR *mGcdMemSpace = NULL;
-UINTN mGcdMemNumberOfDesc = 0;
+EFI_GCD_MEMORY_SPACE_DESCRIPTOR *mGcdMemSpace = NULL;
+UINTN mGcdMemNumberOfDesc = 0;
EFI_MEMORY_ATTRIBUTES_TABLE *mUefiMemoryAttributesTable = NULL;
-PAGE_ATTRIBUTE_TABLE mPageAttributeTable[] = {
- {Page4K, SIZE_4KB, PAGING_4K_ADDRESS_MASK_64},
- {Page2M, SIZE_2MB, PAGING_2M_ADDRESS_MASK_64},
- {Page1G, SIZE_1GB, PAGING_1G_ADDRESS_MASK_64},
+PAGE_ATTRIBUTE_TABLE mPageAttributeTable[] = {
+ { Page4K, SIZE_4KB, PAGING_4K_ADDRESS_MASK_64 },
+ { Page2M, SIZE_2MB, PAGING_2M_ADDRESS_MASK_64 },
+ { Page1G, SIZE_1GB, PAGING_1G_ADDRESS_MASK_64 },
};
UINTN mInternalCr3;
@@ -43,7 +43,7 @@ UINTN mInternalCr3; **/
VOID
SetPageTableBase (
- IN UINTN Cr3
+ IN UINTN Cr3
)
{
mInternalCr3 = Cr3;
@@ -62,11 +62,13 @@ PageAttributeToLength ( )
{
UINTN Index;
- for (Index = 0; Index < sizeof(mPageAttributeTable)/sizeof(mPageAttributeTable[0]); Index++) {
+
+ for (Index = 0; Index < sizeof (mPageAttributeTable)/sizeof (mPageAttributeTable[0]); Index++) {
if (PageAttribute == mPageAttributeTable[Index].Attribute) {
return (UINTN)mPageAttributeTable[Index].Length;
}
}
+
return 0;
}
@@ -83,11 +85,13 @@ PageAttributeToMask ( )
{
UINTN Index;
- for (Index = 0; Index < sizeof(mPageAttributeTable)/sizeof(mPageAttributeTable[0]); Index++) {
+
+ for (Index = 0; Index < sizeof (mPageAttributeTable)/sizeof (mPageAttributeTable[0]); Index++) {
if (PageAttribute == mPageAttributeTable[Index].Attribute) {
return (UINTN)mPageAttributeTable[Index].AddressMask;
}
}
+
return 0;
}
@@ -101,22 +105,22 @@ PageAttributeToMask ( **/
VOID *
GetPageTableEntry (
- IN PHYSICAL_ADDRESS Address,
- OUT PAGE_ATTRIBUTE *PageAttribute
+ IN PHYSICAL_ADDRESS Address,
+ OUT PAGE_ATTRIBUTE *PageAttribute
)
{
- UINTN Index1;
- UINTN Index2;
- UINTN Index3;
- UINTN Index4;
- UINTN Index5;
- UINT64 *L1PageTable;
- UINT64 *L2PageTable;
- UINT64 *L3PageTable;
- UINT64 *L4PageTable;
- UINT64 *L5PageTable;
- UINTN PageTableBase;
- BOOLEAN Enable5LevelPaging;
+ UINTN Index1;
+ UINTN Index2;
+ UINTN Index3;
+ UINTN Index4;
+ UINTN Index5;
+ UINT64 *L1PageTable;
+ UINT64 *L2PageTable;
+ UINT64 *L3PageTable;
+ UINT64 *L4PageTable;
+ UINT64 *L5PageTable;
+ UINTN PageTableBase;
+ BOOLEAN Enable5LevelPaging;
GetPageTable (&PageTableBase, &Enable5LevelPaging);
@@ -126,7 +130,7 @@ GetPageTableEntry ( Index2 = ((UINTN)Address >> 21) & PAGING_PAE_INDEX_MASK;
Index1 = ((UINTN)Address >> 12) & PAGING_PAE_INDEX_MASK;
- if (sizeof(UINTN) == sizeof(UINT64)) {
+ if (sizeof (UINTN) == sizeof (UINT64)) {
if (Enable5LevelPaging) {
L5PageTable = (UINT64 *)PageTableBase;
if (L5PageTable[Index5] == 0) {
@@ -138,6 +142,7 @@ GetPageTableEntry ( } else {
L4PageTable = (UINT64 *)PageTableBase;
}
+
if (L4PageTable[Index4] == 0) {
*PageAttribute = PageNone;
return NULL;
@@ -147,10 +152,12 @@ GetPageTableEntry ( } else {
L3PageTable = (UINT64 *)PageTableBase;
}
+
if (L3PageTable[Index3] == 0) {
*PageAttribute = PageNone;
return NULL;
}
+
if ((L3PageTable[Index3] & IA32_PG_PS) != 0) {
// 1G
*PageAttribute = Page1G;
@@ -162,6 +169,7 @@ GetPageTableEntry ( *PageAttribute = PageNone;
return NULL;
}
+
if ((L2PageTable[Index2] & IA32_PG_PS) != 0) {
// 2M
*PageAttribute = Page2M;
@@ -174,6 +182,7 @@ GetPageTableEntry ( *PageAttribute = PageNone;
return NULL;
}
+
*PageAttribute = Page4K;
return &L1PageTable[Index1];
}
@@ -187,20 +196,24 @@ GetPageTableEntry ( **/
UINT64
GetAttributesFromPageEntry (
- IN UINT64 *PageEntry
+ IN UINT64 *PageEntry
)
{
UINT64 Attributes;
+
Attributes = 0;
if ((*PageEntry & IA32_PG_P) == 0) {
Attributes |= EFI_MEMORY_RP;
}
+
if ((*PageEntry & IA32_PG_RW) == 0) {
Attributes |= EFI_MEMORY_RO;
}
+
if ((*PageEntry & IA32_PG_NX) != 0) {
Attributes |= EFI_MEMORY_XP;
}
+
return Attributes;
}
@@ -214,17 +227,17 @@ GetAttributesFromPageEntry ( **/
VOID
ConvertPageEntryAttribute (
- IN UINT64 *PageEntry,
- IN UINT64 Attributes,
- IN BOOLEAN IsSet,
- OUT BOOLEAN *IsModified
+ IN UINT64 *PageEntry,
+ IN UINT64 Attributes,
+ IN BOOLEAN IsSet,
+ OUT BOOLEAN *IsModified
)
{
UINT64 CurrentPageEntry;
UINT64 NewPageEntry;
CurrentPageEntry = *PageEntry;
- NewPageEntry = CurrentPageEntry;
+ NewPageEntry = CurrentPageEntry;
if ((Attributes & EFI_MEMORY_RP) != 0) {
if (IsSet) {
NewPageEntry &= ~(UINT64)IA32_PG_P;
@@ -232,6 +245,7 @@ ConvertPageEntryAttribute ( NewPageEntry |= IA32_PG_P;
}
}
+
if ((Attributes & EFI_MEMORY_RO) != 0) {
if (IsSet) {
NewPageEntry &= ~(UINT64)IA32_PG_RW;
@@ -250,6 +264,7 @@ ConvertPageEntryAttribute ( NewPageEntry |= IA32_PG_RW;
}
}
+
if ((Attributes & EFI_MEMORY_XP) != 0) {
if (mXdSupported) {
if (IsSet) {
@@ -259,6 +274,7 @@ ConvertPageEntryAttribute ( }
}
}
+
*PageEntry = NewPageEntry;
if (CurrentPageEntry != NewPageEntry) {
*IsModified = TRUE;
@@ -281,13 +297,13 @@ ConvertPageEntryAttribute ( **/
PAGE_ATTRIBUTE
NeedSplitPage (
- IN PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length,
- IN UINT64 *PageEntry,
- IN PAGE_ATTRIBUTE PageAttribute
+ IN PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN UINT64 *PageEntry,
+ IN PAGE_ATTRIBUTE PageAttribute
)
{
- UINT64 PageEntryLength;
+ UINT64 PageEntryLength;
PageEntryLength = PageAttributeToLength (PageAttribute);
@@ -315,14 +331,14 @@ NeedSplitPage ( **/
RETURN_STATUS
SplitPage (
- IN UINT64 *PageEntry,
- IN PAGE_ATTRIBUTE PageAttribute,
- IN PAGE_ATTRIBUTE SplitAttribute
+ IN UINT64 *PageEntry,
+ IN PAGE_ATTRIBUTE PageAttribute,
+ IN PAGE_ATTRIBUTE SplitAttribute
)
{
- UINT64 BaseAddress;
- UINT64 *NewPageEntry;
- UINTN Index;
+ UINT64 BaseAddress;
+ UINT64 *NewPageEntry;
+ UINTN Index;
ASSERT (PageAttribute == Page2M || PageAttribute == Page1G);
@@ -337,10 +353,12 @@ SplitPage ( if (NewPageEntry == NULL) {
return RETURN_OUT_OF_RESOURCES;
}
+
BaseAddress = *PageEntry & PAGING_2M_ADDRESS_MASK_64;
- for (Index = 0; Index < SIZE_4KB / sizeof(UINT64); Index++) {
+ for (Index = 0; Index < SIZE_4KB / sizeof (UINT64); Index++) {
NewPageEntry[Index] = (BaseAddress + SIZE_4KB * Index) | mAddressEncMask | ((*PageEntry) & PAGE_PROGATE_BITS);
}
+
(*PageEntry) = (UINT64)(UINTN)NewPageEntry | mAddressEncMask | PAGE_ATTRIBUTE_BITS;
return RETURN_SUCCESS;
} else {
@@ -352,16 +370,18 @@ SplitPage ( // No need support 1G->4K directly, we should use 1G->2M, then 2M->4K to get more compact page table.
//
ASSERT (SplitAttribute == Page2M || SplitAttribute == Page4K);
- if ((SplitAttribute == Page2M || SplitAttribute == Page4K)) {
+ if (((SplitAttribute == Page2M) || (SplitAttribute == Page4K))) {
NewPageEntry = AllocatePageTableMemory (1);
DEBUG ((DEBUG_VERBOSE, "Split - 0x%x\n", NewPageEntry));
if (NewPageEntry == NULL) {
return RETURN_OUT_OF_RESOURCES;
}
+
BaseAddress = *PageEntry & PAGING_1G_ADDRESS_MASK_64;
- for (Index = 0; Index < SIZE_4KB / sizeof(UINT64); Index++) {
+ for (Index = 0; Index < SIZE_4KB / sizeof (UINT64); Index++) {
NewPageEntry[Index] = (BaseAddress + SIZE_2MB * Index) | mAddressEncMask | IA32_PG_PS | ((*PageEntry) & PAGE_PROGATE_BITS);
}
+
(*PageEntry) = (UINT64)(UINTN)NewPageEntry | mAddressEncMask | PAGE_ATTRIBUTE_BITS;
return RETURN_SUCCESS;
} else {
@@ -401,21 +421,21 @@ SplitPage ( RETURN_STATUS
EFIAPI
ConvertMemoryPageAttributes (
- IN PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length,
- IN UINT64 Attributes,
- IN BOOLEAN IsSet,
- OUT BOOLEAN *IsSplitted OPTIONAL,
- OUT BOOLEAN *IsModified OPTIONAL
+ IN PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN UINT64 Attributes,
+ IN BOOLEAN IsSet,
+ OUT BOOLEAN *IsSplitted OPTIONAL,
+ OUT BOOLEAN *IsModified OPTIONAL
)
{
- UINT64 *PageEntry;
- PAGE_ATTRIBUTE PageAttribute;
- UINTN PageEntryLength;
- PAGE_ATTRIBUTE SplitAttribute;
- RETURN_STATUS Status;
- BOOLEAN IsEntryModified;
- EFI_PHYSICAL_ADDRESS MaximumSupportMemAddress;
+ UINT64 *PageEntry;
+ PAGE_ATTRIBUTE PageAttribute;
+ UINTN PageEntryLength;
+ PAGE_ATTRIBUTE SplitAttribute;
+ RETURN_STATUS Status;
+ BOOLEAN IsEntryModified;
+ EFI_PHYSICAL_ADDRESS MaximumSupportMemAddress;
ASSERT (Attributes != 0);
ASSERT ((Attributes & ~EFI_MEMORY_ATTRIBUTE_MASK) == 0);
@@ -431,18 +451,21 @@ ConvertMemoryPageAttributes ( if (BaseAddress > MaximumSupportMemAddress) {
return RETURN_UNSUPPORTED;
}
+
if (Length > MaximumSupportMemAddress) {
return RETURN_UNSUPPORTED;
}
+
if ((Length != 0) && (BaseAddress > MaximumSupportMemAddress - (Length - 1))) {
return RETURN_UNSUPPORTED;
}
-// DEBUG ((DEBUG_ERROR, "ConvertMemoryPageAttributes(%x) - %016lx, %016lx, %02lx\n", IsSet, BaseAddress, Length, Attributes));
+ // DEBUG ((DEBUG_ERROR, "ConvertMemoryPageAttributes(%x) - %016lx, %016lx, %02lx\n", IsSet, BaseAddress, Length, Attributes));
if (IsSplitted != NULL) {
*IsSplitted = FALSE;
}
+
if (IsModified != NULL) {
*IsModified = FALSE;
}
@@ -455,8 +478,9 @@ ConvertMemoryPageAttributes ( if (PageEntry == NULL) {
return RETURN_UNSUPPORTED;
}
+
PageEntryLength = PageAttributeToLength (PageAttribute);
- SplitAttribute = NeedSplitPage (BaseAddress, Length, PageEntry, PageAttribute);
+ SplitAttribute = NeedSplitPage (BaseAddress, Length, PageEntry, PageAttribute);
if (SplitAttribute == PageNone) {
ConvertPageEntryAttribute (PageEntry, Attributes, IsSet, &IsEntryModified);
if (IsEntryModified) {
@@ -464,22 +488,26 @@ ConvertMemoryPageAttributes ( *IsModified = TRUE;
}
}
+
//
// Convert success, move to next
//
BaseAddress += PageEntryLength;
- Length -= PageEntryLength;
+ Length -= PageEntryLength;
} else {
Status = SplitPage (PageEntry, PageAttribute, SplitAttribute);
if (RETURN_ERROR (Status)) {
return RETURN_UNSUPPORTED;
}
+
if (IsSplitted != NULL) {
*IsSplitted = TRUE;
}
+
if (IsModified != NULL) {
*IsModified = TRUE;
}
+
//
// Just split current page
// Convert success in next around
@@ -512,7 +540,7 @@ FlushTlbForAll ( VOID
)
{
- UINTN Index;
+ UINTN Index;
FlushTlbOnCurrentProcessor (NULL);
@@ -551,22 +579,22 @@ FlushTlbForAll ( EFI_STATUS
EFIAPI
SmmSetMemoryAttributesEx (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length,
- IN UINT64 Attributes,
- OUT BOOLEAN *IsSplitted OPTIONAL
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN UINT64 Attributes,
+ OUT BOOLEAN *IsSplitted OPTIONAL
)
{
EFI_STATUS Status;
BOOLEAN IsModified;
Status = ConvertMemoryPageAttributes (BaseAddress, Length, Attributes, TRUE, IsSplitted, &IsModified);
- if (!EFI_ERROR(Status)) {
+ if (!EFI_ERROR (Status)) {
if (IsModified) {
//
// Flush TLB as last step
//
- FlushTlbForAll();
+ FlushTlbForAll ();
}
}
@@ -599,22 +627,22 @@ SmmSetMemoryAttributesEx ( EFI_STATUS
EFIAPI
SmmClearMemoryAttributesEx (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length,
- IN UINT64 Attributes,
- OUT BOOLEAN *IsSplitted OPTIONAL
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN UINT64 Attributes,
+ OUT BOOLEAN *IsSplitted OPTIONAL
)
{
EFI_STATUS Status;
BOOLEAN IsModified;
Status = ConvertMemoryPageAttributes (BaseAddress, Length, Attributes, FALSE, IsSplitted, &IsModified);
- if (!EFI_ERROR(Status)) {
+ if (!EFI_ERROR (Status)) {
if (IsModified) {
//
// Flush TLB as last step
//
- FlushTlbForAll();
+ FlushTlbForAll ();
}
}
@@ -646,9 +674,9 @@ SmmClearMemoryAttributesEx ( EFI_STATUS
EFIAPI
SmmSetMemoryAttributes (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length,
- IN UINT64 Attributes
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN UINT64 Attributes
)
{
return SmmSetMemoryAttributesEx (BaseAddress, Length, Attributes, NULL);
@@ -679,9 +707,9 @@ SmmSetMemoryAttributes ( EFI_STATUS
EFIAPI
SmmClearMemoryAttributes (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length,
- IN UINT64 Attributes
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN UINT64 Attributes
)
{
return SmmClearMemoryAttributesEx (BaseAddress, Length, Attributes, NULL);
@@ -698,9 +726,9 @@ SmmClearMemoryAttributes ( **/
EFI_STATUS
SetShadowStack (
- IN UINTN Cr3,
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length
+ IN UINTN Cr3,
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
)
{
EFI_STATUS Status;
@@ -725,9 +753,9 @@ SetShadowStack ( **/
EFI_STATUS
SetNotPresentPage (
- IN UINTN Cr3,
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length
+ IN UINTN Cr3,
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
)
{
EFI_STATUS Status;
@@ -759,7 +787,7 @@ SmmGetSystemConfigurationTable ( OUT VOID **Table
)
{
- UINTN Index;
+ UINTN Index;
ASSERT (TableGuid != NULL);
ASSERT (Table != NULL);
@@ -789,11 +817,11 @@ PatchSmmSaveStateMap ( UINTN TileSize;
TileCodeSize = GetSmiHandlerSize ();
- TileCodeSize = ALIGN_VALUE(TileCodeSize, SIZE_4KB);
+ TileCodeSize = ALIGN_VALUE (TileCodeSize, SIZE_4KB);
TileDataSize = (SMRAM_SAVE_STATE_MAP_OFFSET - SMM_PSD_OFFSET) + sizeof (SMRAM_SAVE_STATE_MAP);
- TileDataSize = ALIGN_VALUE(TileDataSize, SIZE_4KB);
- TileSize = TileDataSize + TileCodeSize - 1;
- TileSize = 2 * GetPowerOfTwo32 ((UINT32)TileSize);
+ TileDataSize = ALIGN_VALUE (TileDataSize, SIZE_4KB);
+ TileSize = TileDataSize + TileCodeSize - 1;
+ TileSize = 2 * GetPowerOfTwo32 ((UINT32)TileSize);
DEBUG ((DEBUG_INFO, "PatchSmmSaveStateMap:\n"));
for (Index = 0; Index < mMaxNumberOfCpus - 1; Index++) {
@@ -863,8 +891,8 @@ PatchGdtIdtMap ( VOID
)
{
- EFI_PHYSICAL_ADDRESS BaseAddress;
- UINTN Size;
+ EFI_PHYSICAL_ADDRESS BaseAddress;
+ UINTN Size;
//
// GDT
@@ -872,7 +900,7 @@ PatchGdtIdtMap ( DEBUG ((DEBUG_INFO, "PatchGdtIdtMap - GDT:\n"));
BaseAddress = mGdtBuffer;
- Size = ALIGN_VALUE(mGdtBufferSize, SIZE_4KB);
+ Size = ALIGN_VALUE (mGdtBufferSize, SIZE_4KB);
//
// The range should have been set to RO
// if it is allocated with EfiRuntimeServicesCode.
@@ -889,7 +917,7 @@ PatchGdtIdtMap ( DEBUG ((DEBUG_INFO, "PatchGdtIdtMap - IDT:\n"));
BaseAddress = gcSmiIdtr.Base;
- Size = ALIGN_VALUE(gcSmiIdtr.Limit + 1, SIZE_4KB);
+ Size = ALIGN_VALUE (gcSmiIdtr.Limit + 1, SIZE_4KB);
//
// The range should have been set to RO
// if it is allocated with EfiRuntimeServicesCode.
@@ -909,17 +937,17 @@ SetMemMapAttributes ( VOID
)
{
- EFI_MEMORY_DESCRIPTOR *MemoryMap;
- EFI_MEMORY_DESCRIPTOR *MemoryMapStart;
- UINTN MemoryMapEntryCount;
- UINTN DescriptorSize;
- UINTN Index;
- EDKII_PI_SMM_MEMORY_ATTRIBUTES_TABLE *MemoryAttributesTable;
+ EFI_MEMORY_DESCRIPTOR *MemoryMap;
+ EFI_MEMORY_DESCRIPTOR *MemoryMapStart;
+ UINTN MemoryMapEntryCount;
+ UINTN DescriptorSize;
+ UINTN Index;
+ EDKII_PI_SMM_MEMORY_ATTRIBUTES_TABLE *MemoryAttributesTable;
SmmGetSystemConfigurationTable (&gEdkiiPiSmmMemoryAttributesTableGuid, (VOID **)&MemoryAttributesTable);
if (MemoryAttributesTable == NULL) {
DEBUG ((DEBUG_INFO, "MemoryAttributesTable - NULL\n"));
- return ;
+ return;
}
DEBUG ((DEBUG_INFO, "MemoryAttributesTable:\n"));
@@ -928,9 +956,9 @@ SetMemMapAttributes ( DEBUG ((DEBUG_INFO, " DescriptorSize - 0x%08x\n", MemoryAttributesTable->DescriptorSize));
MemoryMapEntryCount = MemoryAttributesTable->NumberOfEntries;
- DescriptorSize = MemoryAttributesTable->DescriptorSize;
- MemoryMapStart = (EFI_MEMORY_DESCRIPTOR *)(MemoryAttributesTable + 1);
- MemoryMap = MemoryMapStart;
+ DescriptorSize = MemoryAttributesTable->DescriptorSize;
+ MemoryMapStart = (EFI_MEMORY_DESCRIPTOR *)(MemoryAttributesTable + 1);
+ MemoryMap = MemoryMapStart;
for (Index = 0; Index < MemoryMapEntryCount; Index++) {
DEBUG ((DEBUG_INFO, "Entry (0x%x)\n", MemoryMap));
DEBUG ((DEBUG_INFO, " Type - 0x%x\n", MemoryMap->Type));
@@ -938,42 +966,43 @@ SetMemMapAttributes ( DEBUG ((DEBUG_INFO, " VirtualStart - 0x%016lx\n", MemoryMap->VirtualStart));
DEBUG ((DEBUG_INFO, " NumberOfPages - 0x%016lx\n", MemoryMap->NumberOfPages));
DEBUG ((DEBUG_INFO, " Attribute - 0x%016lx\n", MemoryMap->Attribute));
- MemoryMap = NEXT_MEMORY_DESCRIPTOR(MemoryMap, DescriptorSize);
+ MemoryMap = NEXT_MEMORY_DESCRIPTOR (MemoryMap, DescriptorSize);
}
MemoryMap = MemoryMapStart;
for (Index = 0; Index < MemoryMapEntryCount; Index++) {
DEBUG ((DEBUG_VERBOSE, "SetAttribute: Memory Entry - 0x%lx, 0x%x\n", MemoryMap->PhysicalStart, MemoryMap->NumberOfPages));
switch (MemoryMap->Type) {
- case EfiRuntimeServicesCode:
- SmmSetMemoryAttributes (
- MemoryMap->PhysicalStart,
- EFI_PAGES_TO_SIZE((UINTN)MemoryMap->NumberOfPages),
- EFI_MEMORY_RO
- );
- break;
- case EfiRuntimeServicesData:
- SmmSetMemoryAttributes (
- MemoryMap->PhysicalStart,
- EFI_PAGES_TO_SIZE((UINTN)MemoryMap->NumberOfPages),
- EFI_MEMORY_XP
- );
- break;
- default:
- SmmSetMemoryAttributes (
- MemoryMap->PhysicalStart,
- EFI_PAGES_TO_SIZE((UINTN)MemoryMap->NumberOfPages),
- EFI_MEMORY_XP
- );
- break;
+ case EfiRuntimeServicesCode:
+ SmmSetMemoryAttributes (
+ MemoryMap->PhysicalStart,
+ EFI_PAGES_TO_SIZE ((UINTN)MemoryMap->NumberOfPages),
+ EFI_MEMORY_RO
+ );
+ break;
+ case EfiRuntimeServicesData:
+ SmmSetMemoryAttributes (
+ MemoryMap->PhysicalStart,
+ EFI_PAGES_TO_SIZE ((UINTN)MemoryMap->NumberOfPages),
+ EFI_MEMORY_XP
+ );
+ break;
+ default:
+ SmmSetMemoryAttributes (
+ MemoryMap->PhysicalStart,
+ EFI_PAGES_TO_SIZE ((UINTN)MemoryMap->NumberOfPages),
+ EFI_MEMORY_XP
+ );
+ break;
}
- MemoryMap = NEXT_MEMORY_DESCRIPTOR(MemoryMap, DescriptorSize);
+
+ MemoryMap = NEXT_MEMORY_DESCRIPTOR (MemoryMap, DescriptorSize);
}
PatchSmmSaveStateMap ();
PatchGdtIdtMap ();
- return ;
+ return;
}
/**
@@ -992,27 +1021,27 @@ SortMemoryMap ( IN UINTN DescriptorSize
)
{
- EFI_MEMORY_DESCRIPTOR *MemoryMapEntry;
- EFI_MEMORY_DESCRIPTOR *NextMemoryMapEntry;
- EFI_MEMORY_DESCRIPTOR *MemoryMapEnd;
- EFI_MEMORY_DESCRIPTOR TempMemoryMap;
+ EFI_MEMORY_DESCRIPTOR *MemoryMapEntry;
+ EFI_MEMORY_DESCRIPTOR *NextMemoryMapEntry;
+ EFI_MEMORY_DESCRIPTOR *MemoryMapEnd;
+ EFI_MEMORY_DESCRIPTOR TempMemoryMap;
- MemoryMapEntry = MemoryMap;
+ MemoryMapEntry = MemoryMap;
NextMemoryMapEntry = NEXT_MEMORY_DESCRIPTOR (MemoryMapEntry, DescriptorSize);
- MemoryMapEnd = (EFI_MEMORY_DESCRIPTOR *) ((UINT8 *) MemoryMap + MemoryMapSize);
+ MemoryMapEnd = (EFI_MEMORY_DESCRIPTOR *)((UINT8 *)MemoryMap + MemoryMapSize);
while (MemoryMapEntry < MemoryMapEnd) {
while (NextMemoryMapEntry < MemoryMapEnd) {
if (MemoryMapEntry->PhysicalStart > NextMemoryMapEntry->PhysicalStart) {
- CopyMem (&TempMemoryMap, MemoryMapEntry, sizeof(EFI_MEMORY_DESCRIPTOR));
- CopyMem (MemoryMapEntry, NextMemoryMapEntry, sizeof(EFI_MEMORY_DESCRIPTOR));
- CopyMem (NextMemoryMapEntry, &TempMemoryMap, sizeof(EFI_MEMORY_DESCRIPTOR));
+ CopyMem (&TempMemoryMap, MemoryMapEntry, sizeof (EFI_MEMORY_DESCRIPTOR));
+ CopyMem (MemoryMapEntry, NextMemoryMapEntry, sizeof (EFI_MEMORY_DESCRIPTOR));
+ CopyMem (NextMemoryMapEntry, &TempMemoryMap, sizeof (EFI_MEMORY_DESCRIPTOR));
}
NextMemoryMapEntry = NEXT_MEMORY_DESCRIPTOR (NextMemoryMapEntry, DescriptorSize);
}
- MemoryMapEntry = NEXT_MEMORY_DESCRIPTOR (MemoryMapEntry, DescriptorSize);
- NextMemoryMapEntry = NEXT_MEMORY_DESCRIPTOR (MemoryMapEntry, DescriptorSize);
+ MemoryMapEntry = NEXT_MEMORY_DESCRIPTOR (MemoryMapEntry, DescriptorSize);
+ NextMemoryMapEntry = NEXT_MEMORY_DESCRIPTOR (MemoryMapEntry, DescriptorSize);
}
}
@@ -1034,16 +1063,16 @@ IsUefiPageNotPresent ( )
{
switch (MemoryMap->Type) {
- case EfiLoaderCode:
- case EfiLoaderData:
- case EfiBootServicesCode:
- case EfiBootServicesData:
- case EfiConventionalMemory:
- case EfiUnusableMemory:
- case EfiACPIReclaimMemory:
- return TRUE;
- default:
- return FALSE;
+ case EfiLoaderCode:
+ case EfiLoaderData:
+ case EfiBootServicesCode:
+ case EfiBootServicesData:
+ case EfiConventionalMemory:
+ case EfiUnusableMemory:
+ case EfiACPIReclaimMemory:
+ return TRUE;
+ default:
+ return FALSE;
}
}
@@ -1069,24 +1098,25 @@ MergeMemoryMapForNotPresentEntry ( IN UINTN DescriptorSize
)
{
- EFI_MEMORY_DESCRIPTOR *MemoryMapEntry;
- EFI_MEMORY_DESCRIPTOR *MemoryMapEnd;
- UINT64 MemoryBlockLength;
- EFI_MEMORY_DESCRIPTOR *NewMemoryMapEntry;
- EFI_MEMORY_DESCRIPTOR *NextMemoryMapEntry;
+ EFI_MEMORY_DESCRIPTOR *MemoryMapEntry;
+ EFI_MEMORY_DESCRIPTOR *MemoryMapEnd;
+ UINT64 MemoryBlockLength;
+ EFI_MEMORY_DESCRIPTOR *NewMemoryMapEntry;
+ EFI_MEMORY_DESCRIPTOR *NextMemoryMapEntry;
- MemoryMapEntry = MemoryMap;
+ MemoryMapEntry = MemoryMap;
NewMemoryMapEntry = MemoryMap;
- MemoryMapEnd = (EFI_MEMORY_DESCRIPTOR *) ((UINT8 *) MemoryMap + *MemoryMapSize);
+ MemoryMapEnd = (EFI_MEMORY_DESCRIPTOR *)((UINT8 *)MemoryMap + *MemoryMapSize);
while ((UINTN)MemoryMapEntry < (UINTN)MemoryMapEnd) {
- CopyMem (NewMemoryMapEntry, MemoryMapEntry, sizeof(EFI_MEMORY_DESCRIPTOR));
+ CopyMem (NewMemoryMapEntry, MemoryMapEntry, sizeof (EFI_MEMORY_DESCRIPTOR));
NextMemoryMapEntry = NEXT_MEMORY_DESCRIPTOR (MemoryMapEntry, DescriptorSize);
do {
- MemoryBlockLength = (UINT64) (EFI_PAGES_TO_SIZE((UINTN)MemoryMapEntry->NumberOfPages));
+ MemoryBlockLength = (UINT64)(EFI_PAGES_TO_SIZE ((UINTN)MemoryMapEntry->NumberOfPages));
if (((UINTN)NextMemoryMapEntry < (UINTN)MemoryMapEnd) &&
- IsUefiPageNotPresent(MemoryMapEntry) && IsUefiPageNotPresent(NextMemoryMapEntry) &&
- ((MemoryMapEntry->PhysicalStart + MemoryBlockLength) == NextMemoryMapEntry->PhysicalStart)) {
+ IsUefiPageNotPresent (MemoryMapEntry) && IsUefiPageNotPresent (NextMemoryMapEntry) &&
+ ((MemoryMapEntry->PhysicalStart + MemoryBlockLength) == NextMemoryMapEntry->PhysicalStart))
+ {
MemoryMapEntry->NumberOfPages += NextMemoryMapEntry->NumberOfPages;
if (NewMemoryMapEntry != MemoryMapEntry) {
NewMemoryMapEntry->NumberOfPages += NextMemoryMapEntry->NumberOfPages;
@@ -1100,13 +1130,13 @@ MergeMemoryMapForNotPresentEntry ( }
} while (TRUE);
- MemoryMapEntry = NEXT_MEMORY_DESCRIPTOR (MemoryMapEntry, DescriptorSize);
+ MemoryMapEntry = NEXT_MEMORY_DESCRIPTOR (MemoryMapEntry, DescriptorSize);
NewMemoryMapEntry = NEXT_MEMORY_DESCRIPTOR (NewMemoryMapEntry, DescriptorSize);
}
*MemoryMapSize = (UINTN)NewMemoryMapEntry - (UINTN)MemoryMap;
- return ;
+ return;
}
/**
@@ -1124,15 +1154,16 @@ GetGcdMemoryMap ( Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemSpaceMap);
if (EFI_ERROR (Status)) {
- return ;
+ return;
}
mGcdMemNumberOfDesc = 0;
for (Index = 0; Index < NumberOfDescriptors; Index++) {
- if (MemSpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeReserved &&
- (MemSpaceMap[Index].Capabilities & (EFI_MEMORY_PRESENT | EFI_MEMORY_INITIALIZED | EFI_MEMORY_TESTED)) ==
- (EFI_MEMORY_PRESENT | EFI_MEMORY_INITIALIZED)
- ) {
+ if ((MemSpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeReserved) &&
+ ((MemSpaceMap[Index].Capabilities & (EFI_MEMORY_PRESENT | EFI_MEMORY_INITIALIZED | EFI_MEMORY_TESTED)) ==
+ (EFI_MEMORY_PRESENT | EFI_MEMORY_INITIALIZED))
+ )
+ {
mGcdMemNumberOfDesc++;
}
}
@@ -1142,19 +1173,20 @@ GetGcdMemoryMap ( if (mGcdMemSpace == NULL) {
mGcdMemNumberOfDesc = 0;
gBS->FreePool (MemSpaceMap);
- return ;
+ return;
}
mGcdMemNumberOfDesc = 0;
for (Index = 0; Index < NumberOfDescriptors; Index++) {
- if (MemSpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeReserved &&
- (MemSpaceMap[Index].Capabilities & (EFI_MEMORY_PRESENT | EFI_MEMORY_INITIALIZED | EFI_MEMORY_TESTED)) ==
- (EFI_MEMORY_PRESENT | EFI_MEMORY_INITIALIZED)
- ) {
+ if ((MemSpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeReserved) &&
+ ((MemSpaceMap[Index].Capabilities & (EFI_MEMORY_PRESENT | EFI_MEMORY_INITIALIZED | EFI_MEMORY_TESTED)) ==
+ (EFI_MEMORY_PRESENT | EFI_MEMORY_INITIALIZED))
+ )
+ {
CopyMem (
&mGcdMemSpace[mGcdMemNumberOfDesc],
&MemSpaceMap[Index],
- sizeof(EFI_GCD_MEMORY_SPACE_DESCRIPTOR)
+ sizeof (EFI_GCD_MEMORY_SPACE_DESCRIPTOR)
);
mGcdMemNumberOfDesc++;
}
@@ -1177,7 +1209,7 @@ GetUefiMemoryAttributesTable ( Status = EfiGetSystemConfigurationTable (&gEfiMemoryAttributesTableGuid, (VOID **)&MemoryAttributesTable);
if (!EFI_ERROR (Status) && (MemoryAttributesTable != NULL)) {
- MemoryAttributesTableSize = sizeof(EFI_MEMORY_ATTRIBUTES_TABLE) + MemoryAttributesTable->DescriptorSize * MemoryAttributesTable->NumberOfEntries;
+ MemoryAttributesTableSize = sizeof (EFI_MEMORY_ATTRIBUTES_TABLE) + MemoryAttributesTable->DescriptorSize * MemoryAttributesTable->NumberOfEntries;
mUefiMemoryAttributesTable = AllocateCopyPool (MemoryAttributesTableSize, MemoryAttributesTable);
ASSERT (mUefiMemoryAttributesTable != NULL);
}
@@ -1191,30 +1223,30 @@ GetUefiMemoryMap ( VOID
)
{
- EFI_STATUS Status;
- UINTN MapKey;
- UINT32 DescriptorVersion;
- EFI_MEMORY_DESCRIPTOR *MemoryMap;
- UINTN UefiMemoryMapSize;
+ EFI_STATUS Status;
+ UINTN MapKey;
+ UINT32 DescriptorVersion;
+ EFI_MEMORY_DESCRIPTOR *MemoryMap;
+ UINTN UefiMemoryMapSize;
DEBUG ((DEBUG_INFO, "GetUefiMemoryMap\n"));
UefiMemoryMapSize = 0;
- MemoryMap = NULL;
- Status = gBS->GetMemoryMap (
- &UefiMemoryMapSize,
- MemoryMap,
- &MapKey,
- &mUefiDescriptorSize,
- &DescriptorVersion
- );
+ MemoryMap = NULL;
+ Status = gBS->GetMemoryMap (
+ &UefiMemoryMapSize,
+ MemoryMap,
+ &MapKey,
+ &mUefiDescriptorSize,
+ &DescriptorVersion
+ );
ASSERT (Status == EFI_BUFFER_TOO_SMALL);
do {
Status = gBS->AllocatePool (EfiBootServicesData, UefiMemoryMapSize, (VOID **)&MemoryMap);
ASSERT (MemoryMap != NULL);
if (MemoryMap == NULL) {
- return ;
+ return;
}
Status = gBS->GetMemoryMap (
@@ -1231,14 +1263,14 @@ GetUefiMemoryMap ( } while (Status == EFI_BUFFER_TOO_SMALL);
if (MemoryMap == NULL) {
- return ;
+ return;
}
SortMemoryMap (MemoryMap, UefiMemoryMapSize, mUefiDescriptorSize);
MergeMemoryMapForNotPresentEntry (MemoryMap, &UefiMemoryMapSize, mUefiDescriptorSize);
mUefiMemoryMapSize = UefiMemoryMapSize;
- mUefiMemoryMap = AllocateCopyPool (UefiMemoryMapSize, MemoryMap);
+ mUefiMemoryMap = AllocateCopyPool (UefiMemoryMapSize, MemoryMap);
ASSERT (mUefiMemoryMap != NULL);
gBS->FreePool (MemoryMap);
@@ -1266,35 +1298,37 @@ SetUefiMemMapAttributes ( VOID
)
{
- EFI_STATUS Status;
- EFI_MEMORY_DESCRIPTOR *MemoryMap;
- UINTN MemoryMapEntryCount;
- UINTN Index;
- EFI_MEMORY_DESCRIPTOR *Entry;
+ EFI_STATUS Status;
+ EFI_MEMORY_DESCRIPTOR *MemoryMap;
+ UINTN MemoryMapEntryCount;
+ UINTN Index;
+ EFI_MEMORY_DESCRIPTOR *Entry;
DEBUG ((DEBUG_INFO, "SetUefiMemMapAttributes\n"));
if (mUefiMemoryMap != NULL) {
MemoryMapEntryCount = mUefiMemoryMapSize/mUefiDescriptorSize;
- MemoryMap = mUefiMemoryMap;
+ MemoryMap = mUefiMemoryMap;
for (Index = 0; Index < MemoryMapEntryCount; Index++) {
- if (IsUefiPageNotPresent(MemoryMap)) {
+ if (IsUefiPageNotPresent (MemoryMap)) {
Status = SmmSetMemoryAttributes (
MemoryMap->PhysicalStart,
- EFI_PAGES_TO_SIZE((UINTN)MemoryMap->NumberOfPages),
+ EFI_PAGES_TO_SIZE ((UINTN)MemoryMap->NumberOfPages),
EFI_MEMORY_RP
);
DEBUG ((
DEBUG_INFO,
"UefiMemory protection: 0x%lx - 0x%lx %r\n",
MemoryMap->PhysicalStart,
- MemoryMap->PhysicalStart + (UINT64)EFI_PAGES_TO_SIZE((UINTN)MemoryMap->NumberOfPages),
+ MemoryMap->PhysicalStart + (UINT64)EFI_PAGES_TO_SIZE ((UINTN)MemoryMap->NumberOfPages),
Status
));
}
- MemoryMap = NEXT_MEMORY_DESCRIPTOR(MemoryMap, mUefiDescriptorSize);
+
+ MemoryMap = NEXT_MEMORY_DESCRIPTOR (MemoryMap, mUefiDescriptorSize);
}
}
+
//
// Do not free mUefiMemoryMap, it will be checked in IsSmmCommBufferForbiddenAddress().
//
@@ -1318,6 +1352,7 @@ SetUefiMemMapAttributes ( ));
}
}
+
//
// Do not free mGcdMemSpace, it will be checked in IsSmmCommBufferForbiddenAddress().
//
@@ -1328,25 +1363,27 @@ SetUefiMemMapAttributes ( if (mUefiMemoryAttributesTable != NULL) {
Entry = (EFI_MEMORY_DESCRIPTOR *)(mUefiMemoryAttributesTable + 1);
for (Index = 0; Index < mUefiMemoryAttributesTable->NumberOfEntries; Index++) {
- if (Entry->Type == EfiRuntimeServicesCode || Entry->Type == EfiRuntimeServicesData) {
+ if ((Entry->Type == EfiRuntimeServicesCode) || (Entry->Type == EfiRuntimeServicesData)) {
if ((Entry->Attribute & EFI_MEMORY_RO) != 0) {
Status = SmmSetMemoryAttributes (
Entry->PhysicalStart,
- EFI_PAGES_TO_SIZE((UINTN)Entry->NumberOfPages),
+ EFI_PAGES_TO_SIZE ((UINTN)Entry->NumberOfPages),
EFI_MEMORY_RP
);
DEBUG ((
DEBUG_INFO,
"UefiMemoryAttribute protection: 0x%lx - 0x%lx %r\n",
Entry->PhysicalStart,
- Entry->PhysicalStart + (UINT64)EFI_PAGES_TO_SIZE((UINTN)Entry->NumberOfPages),
+ Entry->PhysicalStart + (UINT64)EFI_PAGES_TO_SIZE ((UINTN)Entry->NumberOfPages),
Status
));
}
}
+
Entry = NEXT_MEMORY_DESCRIPTOR (Entry, mUefiMemoryAttributesTable->DescriptorSize);
}
}
+
//
// Do not free mUefiMemoryAttributesTable, it will be checked in IsSmmCommBufferForbiddenAddress().
//
@@ -1365,29 +1402,32 @@ IsSmmCommBufferForbiddenAddress ( IN UINT64 Address
)
{
- EFI_MEMORY_DESCRIPTOR *MemoryMap;
- UINTN MemoryMapEntryCount;
- UINTN Index;
- EFI_MEMORY_DESCRIPTOR *Entry;
+ EFI_MEMORY_DESCRIPTOR *MemoryMap;
+ UINTN MemoryMapEntryCount;
+ UINTN Index;
+ EFI_MEMORY_DESCRIPTOR *Entry;
if (mUefiMemoryMap != NULL) {
- MemoryMap = mUefiMemoryMap;
+ MemoryMap = mUefiMemoryMap;
MemoryMapEntryCount = mUefiMemoryMapSize/mUefiDescriptorSize;
for (Index = 0; Index < MemoryMapEntryCount; Index++) {
if (IsUefiPageNotPresent (MemoryMap)) {
if ((Address >= MemoryMap->PhysicalStart) &&
- (Address < MemoryMap->PhysicalStart + EFI_PAGES_TO_SIZE((UINTN)MemoryMap->NumberOfPages)) ) {
+ (Address < MemoryMap->PhysicalStart + EFI_PAGES_TO_SIZE ((UINTN)MemoryMap->NumberOfPages)))
+ {
return TRUE;
}
}
- MemoryMap = NEXT_MEMORY_DESCRIPTOR(MemoryMap, mUefiDescriptorSize);
+
+ MemoryMap = NEXT_MEMORY_DESCRIPTOR (MemoryMap, mUefiDescriptorSize);
}
}
if (mGcdMemSpace != NULL) {
for (Index = 0; Index < mGcdMemNumberOfDesc; Index++) {
if ((Address >= mGcdMemSpace[Index].BaseAddress) &&
- (Address < mGcdMemSpace[Index].BaseAddress + mGcdMemSpace[Index].Length) ) {
+ (Address < mGcdMemSpace[Index].BaseAddress + mGcdMemSpace[Index].Length))
+ {
return TRUE;
}
}
@@ -1396,17 +1436,20 @@ IsSmmCommBufferForbiddenAddress ( if (mUefiMemoryAttributesTable != NULL) {
Entry = (EFI_MEMORY_DESCRIPTOR *)(mUefiMemoryAttributesTable + 1);
for (Index = 0; Index < mUefiMemoryAttributesTable->NumberOfEntries; Index++) {
- if (Entry->Type == EfiRuntimeServicesCode || Entry->Type == EfiRuntimeServicesData) {
+ if ((Entry->Type == EfiRuntimeServicesCode) || (Entry->Type == EfiRuntimeServicesData)) {
if ((Entry->Attribute & EFI_MEMORY_RO) != 0) {
if ((Address >= Entry->PhysicalStart) &&
- (Address < Entry->PhysicalStart + LShiftU64 (Entry->NumberOfPages, EFI_PAGE_SHIFT))) {
+ (Address < Entry->PhysicalStart + LShiftU64 (Entry->NumberOfPages, EFI_PAGE_SHIFT)))
+ {
return TRUE;
}
+
Entry = NEXT_MEMORY_DESCRIPTOR (Entry, mUefiMemoryAttributesTable->DescriptorSize);
}
}
}
}
+
return FALSE;
}
@@ -1436,10 +1479,10 @@ IsSmmCommBufferForbiddenAddress ( EFI_STATUS
EFIAPI
EdkiiSmmSetMemoryAttributes (
- IN EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL *This,
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length,
- IN UINT64 Attributes
+ IN EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL *This,
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN UINT64 Attributes
)
{
return SmmSetMemoryAttributes (BaseAddress, Length, Attributes);
@@ -1471,10 +1514,10 @@ EdkiiSmmSetMemoryAttributes ( EFI_STATUS
EFIAPI
EdkiiSmmClearMemoryAttributes (
- IN EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL *This,
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length,
- IN UINT64 Attributes
+ IN EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL *This,
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN UINT64 Attributes
)
{
return SmmClearMemoryAttributes (BaseAddress, Length, Attributes);
@@ -1504,10 +1547,10 @@ EdkiiSmmClearMemoryAttributes ( EFI_STATUS
EFIAPI
EdkiiSmmGetMemoryAttributes (
- IN EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL *This,
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length,
- OUT UINT64 *Attributes
+ IN EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL *This,
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ OUT UINT64 *Attributes
)
{
EFI_PHYSICAL_ADDRESS Address;
@@ -1516,17 +1559,16 @@ EdkiiSmmGetMemoryAttributes ( PAGE_ATTRIBUTE PageAttr;
INT64 Size;
- if (Length < SIZE_4KB || Attributes == NULL) {
+ if ((Length < SIZE_4KB) || (Attributes == NULL)) {
return EFI_INVALID_PARAMETER;
}
- Size = (INT64)Length;
+ Size = (INT64)Length;
MemAttr = (UINT64)-1;
do {
-
PageEntry = GetPageTableEntry (BaseAddress, &PageAttr);
- if (PageEntry == NULL || PageAttr == PageNone) {
+ if ((PageEntry == NULL) || (PageAttr == PageNone)) {
return EFI_UNSUPPORTED;
}
@@ -1535,35 +1577,34 @@ EdkiiSmmGetMemoryAttributes ( // share the same attribute. Return EFI_NO_MAPPING if not.
//
*Attributes = GetAttributesFromPageEntry (PageEntry);
- if (MemAttr != (UINT64)-1 && *Attributes != MemAttr) {
+ if ((MemAttr != (UINT64)-1) && (*Attributes != MemAttr)) {
return EFI_NO_MAPPING;
}
switch (PageAttr) {
- case Page4K:
- Address = *PageEntry & ~mAddressEncMask & PAGING_4K_ADDRESS_MASK_64;
- Size -= (SIZE_4KB - (BaseAddress - Address));
- BaseAddress += (SIZE_4KB - (BaseAddress - Address));
- break;
-
- case Page2M:
- Address = *PageEntry & ~mAddressEncMask & PAGING_2M_ADDRESS_MASK_64;
- Size -= SIZE_2MB - (BaseAddress - Address);
- BaseAddress += SIZE_2MB - (BaseAddress - Address);
- break;
-
- case Page1G:
- Address = *PageEntry & ~mAddressEncMask & PAGING_1G_ADDRESS_MASK_64;
- Size -= SIZE_1GB - (BaseAddress - Address);
- BaseAddress += SIZE_1GB - (BaseAddress - Address);
- break;
+ case Page4K:
+ Address = *PageEntry & ~mAddressEncMask & PAGING_4K_ADDRESS_MASK_64;
+ Size -= (SIZE_4KB - (BaseAddress - Address));
+ BaseAddress += (SIZE_4KB - (BaseAddress - Address));
+ break;
- default:
- return EFI_UNSUPPORTED;
+ case Page2M:
+ Address = *PageEntry & ~mAddressEncMask & PAGING_2M_ADDRESS_MASK_64;
+ Size -= SIZE_2MB - (BaseAddress - Address);
+ BaseAddress += SIZE_2MB - (BaseAddress - Address);
+ break;
+
+ case Page1G:
+ Address = *PageEntry & ~mAddressEncMask & PAGING_1G_ADDRESS_MASK_64;
+ Size -= SIZE_1GB - (BaseAddress - Address);
+ BaseAddress += SIZE_1GB - (BaseAddress - Address);
+ break;
+
+ default:
+ return EFI_UNSUPPORTED;
}
MemAttr = *Attributes;
-
} while (Size > 0);
return EFI_SUCCESS;
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmMp.c b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmMp.c index 9b2b191e03..6cc5f016ca 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmMp.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmMp.c @@ -13,7 +13,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent ///
/// SMM MP Protocol instance
///
-EFI_MM_MP_PROTOCOL mSmmMp = {
+EFI_MM_MP_PROTOCOL mSmmMp = {
EFI_MM_MP_PROTOCOL_REVISION,
0,
SmmMpGetNumberOfProcessors,
@@ -37,8 +37,8 @@ EFI_MM_MP_PROTOCOL mSmmMp = { EFI_STATUS
EFIAPI
SmmMpGetNumberOfProcessors (
- IN CONST EFI_MM_MP_PROTOCOL *This,
- OUT UINTN *NumberOfProcessors
+ IN CONST EFI_MM_MP_PROTOCOL *This,
+ OUT UINTN *NumberOfProcessors
)
{
if (NumberOfProcessors == NULL) {
@@ -114,23 +114,23 @@ SmmMpGetNumberOfProcessors ( EFI_STATUS
EFIAPI
SmmMpDispatchProcedure (
- IN CONST EFI_MM_MP_PROTOCOL *This,
- IN EFI_AP_PROCEDURE2 Procedure,
- IN UINTN CpuNumber,
- IN UINTN TimeoutInMicroseconds,
- IN OUT VOID *ProcedureArguments OPTIONAL,
- IN OUT MM_COMPLETION *Token,
- IN OUT EFI_STATUS *CPUStatus
+ IN CONST EFI_MM_MP_PROTOCOL *This,
+ IN EFI_AP_PROCEDURE2 Procedure,
+ IN UINTN CpuNumber,
+ IN UINTN TimeoutInMicroseconds,
+ IN OUT VOID *ProcedureArguments OPTIONAL,
+ IN OUT MM_COMPLETION *Token,
+ IN OUT EFI_STATUS *CPUStatus
)
{
return InternalSmmStartupThisAp (
- Procedure,
- CpuNumber,
- ProcedureArguments,
- Token,
- TimeoutInMicroseconds,
- CPUStatus
- );
+ Procedure,
+ CpuNumber,
+ ProcedureArguments,
+ Token,
+ TimeoutInMicroseconds,
+ CPUStatus
+ );
}
/**
@@ -202,21 +202,21 @@ SmmMpDispatchProcedure ( EFI_STATUS
EFIAPI
SmmMpBroadcastProcedure (
- IN CONST EFI_MM_MP_PROTOCOL *This,
- IN EFI_AP_PROCEDURE2 Procedure,
- IN UINTN TimeoutInMicroseconds,
- IN OUT VOID *ProcedureArguments OPTIONAL,
- IN OUT MM_COMPLETION *Token,
- IN OUT EFI_STATUS *CPUStatus
+ IN CONST EFI_MM_MP_PROTOCOL *This,
+ IN EFI_AP_PROCEDURE2 Procedure,
+ IN UINTN TimeoutInMicroseconds,
+ IN OUT VOID *ProcedureArguments OPTIONAL,
+ IN OUT MM_COMPLETION *Token,
+ IN OUT EFI_STATUS *CPUStatus
)
{
- return InternalSmmStartupAllAPs(
- Procedure,
- TimeoutInMicroseconds,
- ProcedureArguments,
- Token,
- CPUStatus
- );
+ return InternalSmmStartupAllAPs (
+ Procedure,
+ TimeoutInMicroseconds,
+ ProcedureArguments,
+ Token,
+ CPUStatus
+ );
}
/**
@@ -286,8 +286,8 @@ SmmMpSetStartupProcedure ( EFI_STATUS
EFIAPI
SmmMpCheckForProcedure (
- IN CONST EFI_MM_MP_PROTOCOL *This,
- IN MM_COMPLETION Token
+ IN CONST EFI_MM_MP_PROTOCOL *This,
+ IN MM_COMPLETION Token
)
{
if (Token == NULL) {
@@ -329,11 +329,11 @@ SmmMpCheckForProcedure ( EFI_STATUS
EFIAPI
SmmMpWaitForProcedure (
- IN CONST EFI_MM_MP_PROTOCOL *This,
- IN MM_COMPLETION Token
+ IN CONST EFI_MM_MP_PROTOCOL *This,
+ IN MM_COMPLETION Token
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
do {
Status = SmmMpCheckForProcedure (This, Token);
@@ -341,4 +341,3 @@ SmmMpWaitForProcedure ( return Status;
}
-
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmMp.h b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmMp.h index b95ed8c6f8..e2dac6c7d4 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmMp.h +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmMp.h @@ -27,11 +27,10 @@ SPDX-License-Identifier: BSD-2-Clause-Patent EFI_STATUS
EFIAPI
SmmMpGetNumberOfProcessors (
- IN CONST EFI_MM_MP_PROTOCOL *This,
- OUT UINTN *NumberOfProcessors
+ IN CONST EFI_MM_MP_PROTOCOL *This,
+ OUT UINTN *NumberOfProcessors
);
-
/**
This service allows the caller to invoke a procedure one of the application processors (AP). This
function uses an optional token parameter to support blocking and non-blocking modes. If the token
@@ -96,13 +95,13 @@ SmmMpGetNumberOfProcessors ( EFI_STATUS
EFIAPI
SmmMpDispatchProcedure (
- IN CONST EFI_MM_MP_PROTOCOL *This,
- IN EFI_AP_PROCEDURE2 Procedure,
- IN UINTN CpuNumber,
- IN UINTN TimeoutInMicroseconds,
- IN OUT VOID *ProcedureArguments OPTIONAL,
- IN OUT MM_COMPLETION *Token,
- IN OUT EFI_STATUS *CPUStatus
+ IN CONST EFI_MM_MP_PROTOCOL *This,
+ IN EFI_AP_PROCEDURE2 Procedure,
+ IN UINTN CpuNumber,
+ IN UINTN TimeoutInMicroseconds,
+ IN OUT VOID *ProcedureArguments OPTIONAL,
+ IN OUT MM_COMPLETION *Token,
+ IN OUT EFI_STATUS *CPUStatus
);
/**
@@ -174,15 +173,14 @@ SmmMpDispatchProcedure ( EFI_STATUS
EFIAPI
SmmMpBroadcastProcedure (
- IN CONST EFI_MM_MP_PROTOCOL *This,
- IN EFI_AP_PROCEDURE2 Procedure,
- IN UINTN TimeoutInMicroseconds,
- IN OUT VOID *ProcedureArguments OPTIONAL,
- IN OUT MM_COMPLETION *Token,
- IN OUT EFI_STATUS *CPUStatus
+ IN CONST EFI_MM_MP_PROTOCOL *This,
+ IN EFI_AP_PROCEDURE2 Procedure,
+ IN UINTN TimeoutInMicroseconds,
+ IN OUT VOID *ProcedureArguments OPTIONAL,
+ IN OUT MM_COMPLETION *Token,
+ IN OUT EFI_STATUS *CPUStatus
);
-
/**
This service allows the caller to set a startup procedure that will be executed when an AP powers
up from a state where core configuration and context is lost. The procedure is execution has the
@@ -246,8 +244,8 @@ SmmMpSetStartupProcedure ( EFI_STATUS
EFIAPI
SmmMpCheckForProcedure (
- IN CONST EFI_MM_MP_PROTOCOL *This,
- IN MM_COMPLETION Token
+ IN CONST EFI_MM_MP_PROTOCOL *This,
+ IN MM_COMPLETION Token
);
/**
@@ -278,8 +276,8 @@ SmmMpCheckForProcedure ( EFI_STATUS
EFIAPI
SmmMpWaitForProcedure (
- IN CONST EFI_MM_MP_PROTOCOL *This,
- IN MM_COMPLETION Token
+ IN CONST EFI_MM_MP_PROTOCOL *This,
+ IN MM_COMPLETION Token
);
#endif
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c index c3f9794b95..c1efda7126 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c @@ -11,80 +11,84 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include "PiSmmCpuDxeSmm.h"
#include "SmmProfileInternal.h"
-UINT32 mSmmProfileCr3;
+UINT32 mSmmProfileCr3;
-SMM_PROFILE_HEADER *mSmmProfileBase;
-MSR_DS_AREA_STRUCT *mMsrDsAreaBase;
+SMM_PROFILE_HEADER *mSmmProfileBase;
+MSR_DS_AREA_STRUCT *mMsrDsAreaBase;
//
// The buffer to store SMM profile data.
//
-UINTN mSmmProfileSize;
+UINTN mSmmProfileSize;
//
// The buffer to enable branch trace store.
//
-UINTN mMsrDsAreaSize = SMM_PROFILE_DTS_SIZE;
+UINTN mMsrDsAreaSize = SMM_PROFILE_DTS_SIZE;
//
// The flag indicates if execute-disable is supported by processor.
//
-BOOLEAN mXdSupported = TRUE;
+BOOLEAN mXdSupported = TRUE;
//
// The flag indicates if execute-disable is enabled on processor.
//
-BOOLEAN mXdEnabled = FALSE;
+BOOLEAN mXdEnabled = FALSE;
//
// The flag indicates if BTS is supported by processor.
//
-BOOLEAN mBtsSupported = TRUE;
+BOOLEAN mBtsSupported = TRUE;
//
// The flag indicates if SMM profile starts to record data.
//
-BOOLEAN mSmmProfileStart = FALSE;
+BOOLEAN mSmmProfileStart = FALSE;
//
// The flag indicates if #DB will be setup in #PF handler.
//
-BOOLEAN mSetupDebugTrap = FALSE;
+BOOLEAN mSetupDebugTrap = FALSE;
//
// Record the page fault exception count for one instruction execution.
//
-UINTN *mPFEntryCount;
+UINTN *mPFEntryCount;
-UINT64 (*mLastPFEntryValue)[MAX_PF_ENTRY_COUNT];
+UINT64 (*mLastPFEntryValue)[MAX_PF_ENTRY_COUNT];
UINT64 *(*mLastPFEntryPointer)[MAX_PF_ENTRY_COUNT];
-MSR_DS_AREA_STRUCT **mMsrDsArea;
-BRANCH_TRACE_RECORD **mMsrBTSRecord;
-UINTN mBTSRecordNumber;
-PEBS_RECORD **mMsrPEBSRecord;
+MSR_DS_AREA_STRUCT **mMsrDsArea;
+BRANCH_TRACE_RECORD **mMsrBTSRecord;
+UINTN mBTSRecordNumber;
+PEBS_RECORD **mMsrPEBSRecord;
//
// These memory ranges are always present, they does not generate the access type of page fault exception,
// but they possibly generate instruction fetch type of page fault exception.
//
-MEMORY_PROTECTION_RANGE *mProtectionMemRange = NULL;
-UINTN mProtectionMemRangeCount = 0;
+MEMORY_PROTECTION_RANGE *mProtectionMemRange = NULL;
+UINTN mProtectionMemRangeCount = 0;
//
// Some predefined memory ranges.
//
-MEMORY_PROTECTION_RANGE mProtectionMemRangeTemplate[] = {
+MEMORY_PROTECTION_RANGE mProtectionMemRangeTemplate[] = {
//
// SMRAM range (to be fixed in runtime).
// It is always present and instruction fetches are allowed.
//
- {{0x00000000, 0x00000000},TRUE,FALSE},
+ {
+ { 0x00000000, 0x00000000 }, TRUE, FALSE
+ },
//
// SMM profile data range( to be fixed in runtime).
// It is always present and instruction fetches are not allowed.
//
- {{0x00000000, 0x00000000},TRUE,TRUE},
+ {
+ { 0x00000000, 0x00000000 }, TRUE, TRUE
+ },
//
// SMRAM ranges not covered by mCpuHotPlugData.SmrrBase/mCpuHotPlugData.SmrrSiz (to be fixed in runtime).
@@ -105,13 +109,13 @@ MEMORY_PROTECTION_RANGE mProtectionMemRangeTemplate[] = { //
// These memory ranges are mapped by 4KB-page instead of 2MB-page.
//
-MEMORY_RANGE *mSplitMemRange = NULL;
-UINTN mSplitMemRangeCount = 0;
+MEMORY_RANGE *mSplitMemRange = NULL;
+UINTN mSplitMemRangeCount = 0;
//
// SMI command port.
//
-UINT32 mSmiCommandPort;
+UINT32 mSmiCommandPort;
/**
Disable branch trace store.
@@ -146,8 +150,8 @@ GetCpuIndex ( VOID
)
{
- UINTN Index;
- UINT32 ApicId;
+ UINTN Index;
+ UINT32 ApicId;
ApicId = GetApicId ();
@@ -156,6 +160,7 @@ GetCpuIndex ( return Index;
}
}
+
ASSERT (FALSE);
return 0;
}
@@ -169,8 +174,8 @@ GetCpuIndex ( **/
UINT64
GetSourceFromDestinationOnBts (
- UINTN CpuIndex,
- UINT64 DestinationIP
+ UINTN CpuIndex,
+ UINT64 DestinationIP
)
{
BRANCH_TRACE_RECORD *CurrentBTSRecord;
@@ -186,8 +191,9 @@ GetSourceFromDestinationOnBts ( // Underflow
//
CurrentBTSRecord = (BRANCH_TRACE_RECORD *)((UINTN)mMsrDsArea[CpuIndex]->BTSAbsoluteMaximum - 1);
- CurrentBTSRecord --;
+ CurrentBTSRecord--;
}
+
if (CurrentBTSRecord->LastBranchTo == DestinationIP) {
//
// Good! find 1st one, then find 2nd one.
@@ -204,6 +210,7 @@ GetSourceFromDestinationOnBts ( return CurrentBTSRecord->LastBranchFrom;
}
}
+
CurrentBTSRecord--;
}
@@ -221,8 +228,8 @@ GetSourceFromDestinationOnBts ( VOID
EFIAPI
DebugExceptionHandler (
- IN EFI_EXCEPTION_TYPE InterruptType,
- IN EFI_SYSTEM_CONTEXT SystemContext
+ IN EFI_EXCEPTION_TYPE InterruptType,
+ IN EFI_SYSTEM_CONTEXT SystemContext
)
{
UINTN CpuIndex;
@@ -230,9 +237,11 @@ DebugExceptionHandler ( if (!mSmmProfileStart &&
!HEAP_GUARD_NONSTOP_MODE &&
- !NULL_DETECTION_NONSTOP_MODE) {
+ !NULL_DETECTION_NONSTOP_MODE)
+ {
return;
}
+
CpuIndex = GetCpuIndex ();
//
@@ -268,7 +277,7 @@ DebugExceptionHandler ( **/
BOOLEAN
IsInSmmRanges (
- IN EFI_PHYSICAL_ADDRESS Address
+ IN EFI_PHYSICAL_ADDRESS Address
)
{
UINTN Index;
@@ -276,12 +285,15 @@ IsInSmmRanges ( if ((Address >= mCpuHotPlugData.SmrrBase) && (Address < mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize)) {
return TRUE;
}
+
for (Index = 0; Index < mSmmCpuSmramRangeCount; Index++) {
- if (Address >= mSmmCpuSmramRanges[Index].CpuStart &&
- Address < mSmmCpuSmramRanges[Index].CpuStart + mSmmCpuSmramRanges[Index].PhysicalSize) {
+ if ((Address >= mSmmCpuSmramRanges[Index].CpuStart) &&
+ (Address < mSmmCpuSmramRanges[Index].CpuStart + mSmmCpuSmramRanges[Index].PhysicalSize))
+ {
return TRUE;
}
}
+
return FALSE;
}
@@ -294,8 +306,8 @@ IsInSmmRanges ( **/
BOOLEAN
IsAddressValid (
- IN EFI_PHYSICAL_ADDRESS Address,
- IN BOOLEAN *Nx
+ IN EFI_PHYSICAL_ADDRESS Address,
+ IN BOOLEAN *Nx
)
{
UINTN Index;
@@ -310,14 +322,15 @@ IsAddressValid ( return mProtectionMemRange[Index].Present;
}
}
+
*Nx = TRUE;
return FALSE;
-
} else {
*Nx = TRUE;
if (IsInSmmRanges (Address)) {
*Nx = FALSE;
}
+
return TRUE;
}
}
@@ -330,7 +343,7 @@ IsAddressValid ( **/
BOOLEAN
IsAddressSplit (
- IN EFI_PHYSICAL_ADDRESS Address
+ IN EFI_PHYSICAL_ADDRESS Address
)
{
UINTN Index;
@@ -349,12 +362,13 @@ IsAddressSplit ( if ((mCpuHotPlugData.SmrrBase - Address) < BASE_2MB) {
return TRUE;
}
- } else if (Address > (mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize - BASE_2MB)) {
+ } else if (Address > (mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize - BASE_2MB)) {
if ((Address - (mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize - BASE_2MB)) < BASE_2MB) {
return TRUE;
}
}
}
+
//
// Return default
//
@@ -393,9 +407,9 @@ InitProtectedMemRange ( // Get MMIO ranges from GCD and add them into protected memory ranges.
//
gDS->GetMemorySpaceMap (
- &NumberOfDescriptors,
- &MemorySpaceMap
- );
+ &NumberOfDescriptors,
+ &MemorySpaceMap
+ );
for (Index = 0; Index < NumberOfDescriptors; Index++) {
if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo) {
NumberOfAddedDescriptors++;
@@ -403,8 +417,8 @@ InitProtectedMemRange ( }
if (NumberOfAddedDescriptors != 0) {
- TotalSize = NumberOfAddedDescriptors * sizeof (MEMORY_PROTECTION_RANGE) + sizeof (mProtectionMemRangeTemplate);
- mProtectionMemRange = (MEMORY_PROTECTION_RANGE *) AllocateZeroPool (TotalSize);
+ TotalSize = NumberOfAddedDescriptors * sizeof (MEMORY_PROTECTION_RANGE) + sizeof (mProtectionMemRangeTemplate);
+ mProtectionMemRange = (MEMORY_PROTECTION_RANGE *)AllocateZeroPool (TotalSize);
ASSERT (mProtectionMemRange != NULL);
mProtectionMemRangeCount = TotalSize / sizeof (MEMORY_PROTECTION_RANGE);
@@ -416,8 +430,8 @@ InitProtectedMemRange ( //
// Create split ranges which come from protected ranges.
//
- TotalSize = (TotalSize / sizeof (MEMORY_PROTECTION_RANGE)) * sizeof (MEMORY_RANGE);
- mSplitMemRange = (MEMORY_RANGE *) AllocateZeroPool (TotalSize);
+ TotalSize = (TotalSize / sizeof (MEMORY_PROTECTION_RANGE)) * sizeof (MEMORY_RANGE);
+ mSplitMemRange = (MEMORY_RANGE *)AllocateZeroPool (TotalSize);
ASSERT (mSplitMemRange != NULL);
//
@@ -425,13 +439,15 @@ InitProtectedMemRange ( //
NumberOfProtectRange = sizeof (mProtectionMemRangeTemplate) / sizeof (MEMORY_PROTECTION_RANGE);
for (Index = 0; Index < mSmmCpuSmramRangeCount; Index++) {
- if (mSmmCpuSmramRanges[Index].CpuStart >= mProtectionMemRange[0].Range.Base &&
- mSmmCpuSmramRanges[Index].CpuStart + mSmmCpuSmramRanges[Index].PhysicalSize < mProtectionMemRange[0].Range.Top) {
+ if ((mSmmCpuSmramRanges[Index].CpuStart >= mProtectionMemRange[0].Range.Base) &&
+ (mSmmCpuSmramRanges[Index].CpuStart + mSmmCpuSmramRanges[Index].PhysicalSize < mProtectionMemRange[0].Range.Top))
+ {
//
// If the address have been already covered by mCpuHotPlugData.SmrrBase/mCpuHotPlugData.SmrrSiz
//
break;
}
+
mProtectionMemRange[NumberOfProtectRange].Range.Base = mSmmCpuSmramRanges[Index].CpuStart;
mProtectionMemRange[NumberOfProtectRange].Range.Top = mSmmCpuSmramRanges[Index].CpuStart + mSmmCpuSmramRanges[Index].PhysicalSize;
mProtectionMemRange[NumberOfProtectRange].Present = TRUE;
@@ -446,6 +462,7 @@ InitProtectedMemRange ( if (MemorySpaceMap[Index].GcdMemoryType != EfiGcdMemoryTypeMemoryMappedIo) {
continue;
}
+
mProtectionMemRange[NumberOfProtectRange].Range.Base = MemorySpaceMap[Index].BaseAddress;
mProtectionMemRange[NumberOfProtectRange].Range.Top = MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length;
mProtectionMemRange[NumberOfProtectRange].Present = TRUE;
@@ -479,7 +496,8 @@ InitProtectedMemRange ( Top2MBAlignedAddress = ProtectEndAddress & ~(SIZE_2MB - 1);
Base2MBAlignedAddress = (ProtectBaseAddress + SIZE_2MB - 1) & ~(SIZE_2MB - 1);
if ((Top2MBAlignedAddress > Base2MBAlignedAddress) &&
- ((Top2MBAlignedAddress - Base2MBAlignedAddress) >= SIZE_2MB)) {
+ ((Top2MBAlignedAddress - Base2MBAlignedAddress) >= SIZE_2MB))
+ {
//
// There is an range which could be mapped by 2MB-page.
//
@@ -493,6 +511,7 @@ InitProtectedMemRange ( mSplitMemRange[NumberOfSpliteRange].Top = (ProtectEndAddress + SIZE_2MB - 1) & ~(SIZE_2MB - 1);
NumberOfSpliteRange++;
}
+
if (Low4KBPageSize != 0) {
//
// Add not 2MB-aligned range to be mapped by 4KB-page.
@@ -519,6 +538,7 @@ InitProtectedMemRange ( DEBUG ((DEBUG_INFO, "mProtectionMemRange[%d].Base = %lx\n", Index, mProtectionMemRange[Index].Range.Base));
DEBUG ((DEBUG_INFO, "mProtectionMemRange[%d].Top = %lx\n", Index, mProtectionMemRange[Index].Range.Top));
}
+
for (Index = 0; Index < mSplitMemRangeCount; Index++) {
DEBUG ((DEBUG_INFO, "mSplitMemRange[%d].Base = %lx\n", Index, mSplitMemRange[Index].Base));
DEBUG ((DEBUG_INFO, "mSplitMemRange[%d].Top = %lx\n", Index, mSplitMemRange[Index].Top));
@@ -534,64 +554,65 @@ InitPaging ( VOID
)
{
- UINT64 Pml5Entry;
- UINT64 Pml4Entry;
- UINT64 *Pml5;
- UINT64 *Pml4;
- UINT64 *Pdpt;
- UINT64 *Pd;
- UINT64 *Pt;
- UINTN Address;
- UINTN Pml5Index;
- UINTN Pml4Index;
- UINTN PdptIndex;
- UINTN PdIndex;
- UINTN PtIndex;
- UINTN NumberOfPdptEntries;
- UINTN NumberOfPml4Entries;
- UINTN NumberOfPml5Entries;
- UINTN SizeOfMemorySpace;
- BOOLEAN Nx;
- IA32_CR4 Cr4;
- BOOLEAN Enable5LevelPaging;
-
- Cr4.UintN = AsmReadCr4 ();
- Enable5LevelPaging = (BOOLEAN) (Cr4.Bits.LA57 == 1);
+ UINT64 Pml5Entry;
+ UINT64 Pml4Entry;
+ UINT64 *Pml5;
+ UINT64 *Pml4;
+ UINT64 *Pdpt;
+ UINT64 *Pd;
+ UINT64 *Pt;
+ UINTN Address;
+ UINTN Pml5Index;
+ UINTN Pml4Index;
+ UINTN PdptIndex;
+ UINTN PdIndex;
+ UINTN PtIndex;
+ UINTN NumberOfPdptEntries;
+ UINTN NumberOfPml4Entries;
+ UINTN NumberOfPml5Entries;
+ UINTN SizeOfMemorySpace;
+ BOOLEAN Nx;
+ IA32_CR4 Cr4;
+ BOOLEAN Enable5LevelPaging;
+
+ Cr4.UintN = AsmReadCr4 ();
+ Enable5LevelPaging = (BOOLEAN)(Cr4.Bits.LA57 == 1);
if (sizeof (UINTN) == sizeof (UINT64)) {
if (!Enable5LevelPaging) {
- Pml5Entry = (UINTN) mSmmProfileCr3 | IA32_PG_P;
- Pml5 = &Pml5Entry;
+ Pml5Entry = (UINTN)mSmmProfileCr3 | IA32_PG_P;
+ Pml5 = &Pml5Entry;
} else {
- Pml5 = (UINT64*) (UINTN) mSmmProfileCr3;
+ Pml5 = (UINT64 *)(UINTN)mSmmProfileCr3;
}
+
SizeOfMemorySpace = HighBitSet64 (gPhyMask) + 1;
//
// Calculate the table entries of PML4E and PDPTE.
//
NumberOfPml5Entries = 1;
if (SizeOfMemorySpace > 48) {
- NumberOfPml5Entries = (UINTN) LShiftU64 (1, SizeOfMemorySpace - 48);
- SizeOfMemorySpace = 48;
+ NumberOfPml5Entries = (UINTN)LShiftU64 (1, SizeOfMemorySpace - 48);
+ SizeOfMemorySpace = 48;
}
NumberOfPml4Entries = 1;
if (SizeOfMemorySpace > 39) {
- NumberOfPml4Entries = (UINTN) LShiftU64 (1, SizeOfMemorySpace - 39);
- SizeOfMemorySpace = 39;
+ NumberOfPml4Entries = (UINTN)LShiftU64 (1, SizeOfMemorySpace - 39);
+ SizeOfMemorySpace = 39;
}
NumberOfPdptEntries = 1;
ASSERT (SizeOfMemorySpace > 30);
- NumberOfPdptEntries = (UINTN) LShiftU64 (1, SizeOfMemorySpace - 30);
+ NumberOfPdptEntries = (UINTN)LShiftU64 (1, SizeOfMemorySpace - 30);
} else {
- Pml4Entry = (UINTN) mSmmProfileCr3 | IA32_PG_P;
- Pml4 = &Pml4Entry;
- Pml5Entry = (UINTN) Pml4 | IA32_PG_P;
- Pml5 = &Pml5Entry;
- NumberOfPml5Entries = 1;
- NumberOfPml4Entries = 1;
- NumberOfPdptEntries = 4;
+ Pml4Entry = (UINTN)mSmmProfileCr3 | IA32_PG_P;
+ Pml4 = &Pml4Entry;
+ Pml5Entry = (UINTN)Pml4 | IA32_PG_P;
+ Pml5 = &Pml5Entry;
+ NumberOfPml5Entries = 1;
+ NumberOfPml4Entries = 1;
+ NumberOfPdptEntries = 4;
}
//
@@ -604,7 +625,8 @@ InitPaging ( //
continue;
}
- Pml4 = (UINT64 *) (UINTN) (Pml5[Pml5Index] & PHYSICAL_ADDRESS_MASK);
+
+ Pml4 = (UINT64 *)(UINTN)(Pml5[Pml5Index] & PHYSICAL_ADDRESS_MASK);
for (Pml4Index = 0; Pml4Index < NumberOfPml4Entries; Pml4Index++) {
if ((Pml4[Pml4Index] & IA32_PG_P) == 0) {
//
@@ -612,6 +634,7 @@ InitPaging ( //
continue;
}
+
Pdpt = (UINT64 *)(UINTN)(Pml4[Pml4Index] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);
for (PdptIndex = 0; PdptIndex < NumberOfPdptEntries; PdptIndex++, Pdpt++) {
if ((*Pdpt & IA32_PG_P) == 0) {
@@ -620,16 +643,19 @@ InitPaging ( //
continue;
}
+
if ((*Pdpt & IA32_PG_PS) != 0) {
//
// This is 1G entry, skip it
//
continue;
}
+
Pd = (UINT64 *)(UINTN)(*Pdpt & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);
if (Pd == 0) {
continue;
}
+
for (PdIndex = 0; PdIndex < SIZE_4KB / sizeof (*Pd); PdIndex++, Pd++) {
if ((*Pd & IA32_PG_P) == 0) {
//
@@ -637,13 +663,14 @@ InitPaging ( //
continue;
}
- Address = (UINTN) LShiftU64 (
- LShiftU64 (
- LShiftU64 ((Pml5Index << 9) + Pml4Index, 9) + PdptIndex,
- 9
- ) + PdIndex,
- 21
- );
+
+ Address = (UINTN)LShiftU64 (
+ LShiftU64 (
+ LShiftU64 ((Pml5Index << 9) + Pml4Index, 9) + PdptIndex,
+ 9
+ ) + PdIndex,
+ 21
+ );
//
// If it is 2M page, check IsAddressSplit()
@@ -658,9 +685,10 @@ InitPaging ( ASSERT (Pt != NULL);
// Split it
- for (PtIndex = 0; PtIndex < SIZE_4KB / sizeof(*Pt); PtIndex++) {
+ for (PtIndex = 0; PtIndex < SIZE_4KB / sizeof (*Pt); PtIndex++) {
Pt[PtIndex] = Address + ((PtIndex << 12) | mAddressEncMask | PAGE_ATTRIBUTE_BITS);
} // end for PT
+
*Pd = (UINT64)(UINTN)Pt | mAddressEncMask | PAGE_ATTRIBUTE_BITS;
} // end if IsAddressSplit
} // end for PD
@@ -679,7 +707,8 @@ InitPaging ( //
continue;
}
- Pml4 = (UINT64 *) (UINTN) (Pml5[Pml5Index] & PHYSICAL_ADDRESS_MASK);
+
+ Pml4 = (UINT64 *)(UINTN)(Pml5[Pml5Index] & PHYSICAL_ADDRESS_MASK);
for (Pml4Index = 0; Pml4Index < NumberOfPml4Entries; Pml4Index++) {
if ((Pml4[Pml4Index] & IA32_PG_P) == 0) {
//
@@ -687,6 +716,7 @@ InitPaging ( //
continue;
}
+
Pdpt = (UINT64 *)(UINTN)(Pml4[Pml4Index] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);
for (PdptIndex = 0; PdptIndex < NumberOfPdptEntries; PdptIndex++, Pdpt++) {
if ((*Pdpt & IA32_PG_P) == 0) {
@@ -695,6 +725,7 @@ InitPaging ( //
continue;
}
+
if ((*Pdpt & IA32_PG_PS) != 0) {
//
// This is 1G entry, set NX bit and skip it
@@ -702,12 +733,15 @@ InitPaging ( if (mXdSupported) {
*Pdpt = *Pdpt | IA32_PG_NX;
}
+
continue;
}
+
Pd = (UINT64 *)(UINTN)(*Pdpt & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);
if (Pd == 0) {
continue;
}
+
for (PdIndex = 0; PdIndex < SIZE_4KB / sizeof (*Pd); PdIndex++, Pd++) {
if ((*Pd & IA32_PG_P) == 0) {
//
@@ -715,13 +749,14 @@ InitPaging ( //
continue;
}
- Address = (UINTN) LShiftU64 (
- LShiftU64 (
- LShiftU64 ((Pml5Index << 9) + Pml4Index, 9) + PdptIndex,
- 9
- ) + PdIndex,
- 21
- );
+
+ Address = (UINTN)LShiftU64 (
+ LShiftU64 (
+ LShiftU64 ((Pml5Index << 9) + Pml4Index, 9) + PdptIndex,
+ 9
+ ) + PdIndex,
+ 21
+ );
if ((*Pd & IA32_PG_PS) != 0) {
// 2MB page
@@ -732,6 +767,7 @@ InitPaging ( //
*Pd = *Pd & (INTN)(INT32)(~PAGE_ATTRIBUTE_BITS);
}
+
if (Nx && mXdSupported) {
*Pd = *Pd | IA32_PG_NX;
}
@@ -741,13 +777,16 @@ InitPaging ( if (Pt == 0) {
continue;
}
- for (PtIndex = 0; PtIndex < SIZE_4KB / sizeof(*Pt); PtIndex++, Pt++) {
+
+ for (PtIndex = 0; PtIndex < SIZE_4KB / sizeof (*Pt); PtIndex++, Pt++) {
if (!IsAddressValid (Address, &Nx)) {
*Pt = *Pt & (INTN)(INT32)(~PAGE_ATTRIBUTE_BITS);
}
+
if (Nx && mXdSupported) {
*Pt = *Pt | IA32_PG_NX;
}
+
Address += SIZE_4KB;
} // end for PT
} // end if PS
@@ -766,7 +805,7 @@ InitPaging ( //
mXdEnabled = TRUE;
- return ;
+ return;
}
/**
@@ -778,11 +817,11 @@ GetSmiCommandPort ( VOID
)
{
- EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE *Fadt;
+ EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE *Fadt;
- Fadt = (EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE *) EfiLocateFirstAcpiTable (
- EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE
- );
+ Fadt = (EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE *)EfiLocateFirstAcpiTable (
+ EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE
+ );
ASSERT (Fadt != NULL);
mSmiCommandPort = Fadt->SmiCmd;
@@ -830,7 +869,7 @@ InitSmmProfileCallBack ( SMM_PROFILE_NAME,
&gEfiCallerIdGuid,
EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
- sizeof(mSmmProfileBase),
+ sizeof (mSmmProfileBase),
&mSmmProfileBase
);
@@ -856,20 +895,22 @@ InitSmmProfileInternal ( VOID
)
{
- EFI_STATUS Status;
- EFI_PHYSICAL_ADDRESS Base;
- VOID *Registration;
- UINTN Index;
- UINTN MsrDsAreaSizePerCpu;
- UINTN TotalSize;
+ EFI_STATUS Status;
+ EFI_PHYSICAL_ADDRESS Base;
+ VOID *Registration;
+ UINTN Index;
+ UINTN MsrDsAreaSizePerCpu;
+ UINTN TotalSize;
mPFEntryCount = (UINTN *)AllocateZeroPool (sizeof (UINTN) * mMaxNumberOfCpus);
ASSERT (mPFEntryCount != NULL);
- mLastPFEntryValue = (UINT64 (*)[MAX_PF_ENTRY_COUNT])AllocateZeroPool (
- sizeof (mLastPFEntryValue[0]) * mMaxNumberOfCpus);
+ mLastPFEntryValue = (UINT64 (*)[MAX_PF_ENTRY_COUNT])AllocateZeroPool (
+ sizeof (mLastPFEntryValue[0]) * mMaxNumberOfCpus
+ );
ASSERT (mLastPFEntryValue != NULL);
mLastPFEntryPointer = (UINT64 *(*)[MAX_PF_ENTRY_COUNT])AllocateZeroPool (
- sizeof (mLastPFEntryPointer[0]) * mMaxNumberOfCpus);
+ sizeof (mLastPFEntryPointer[0]) * mMaxNumberOfCpus
+ );
ASSERT (mLastPFEntryPointer != NULL);
//
@@ -885,7 +926,7 @@ InitSmmProfileInternal ( TotalSize = mSmmProfileSize;
}
- Base = 0xFFFFFFFF;
+ Base = 0xFFFFFFFF;
Status = gBS->AllocatePages (
AllocateMaxAddress,
EfiReservedMemoryType,
@@ -900,8 +941,8 @@ InitSmmProfileInternal ( // Initialize SMM profile data header.
//
mSmmProfileBase->HeaderSize = sizeof (SMM_PROFILE_HEADER);
- mSmmProfileBase->MaxDataEntries = (UINT64)((mSmmProfileSize - sizeof(SMM_PROFILE_HEADER)) / sizeof (SMM_PROFILE_ENTRY));
- mSmmProfileBase->MaxDataSize = MultU64x64 (mSmmProfileBase->MaxDataEntries, sizeof(SMM_PROFILE_ENTRY));
+ mSmmProfileBase->MaxDataEntries = (UINT64)((mSmmProfileSize - sizeof (SMM_PROFILE_HEADER)) / sizeof (SMM_PROFILE_ENTRY));
+ mSmmProfileBase->MaxDataSize = MultU64x64 (mSmmProfileBase->MaxDataEntries, sizeof (SMM_PROFILE_ENTRY));
mSmmProfileBase->CurDataEntries = 0;
mSmmProfileBase->CurDataSize = 0;
mSmmProfileBase->TsegStart = mCpuHotPlugData.SmrrBase;
@@ -917,22 +958,22 @@ InitSmmProfileInternal ( mMsrPEBSRecord = (PEBS_RECORD **)AllocateZeroPool (sizeof (PEBS_RECORD *) * mMaxNumberOfCpus);
ASSERT (mMsrPEBSRecord != NULL);
- mMsrDsAreaBase = (MSR_DS_AREA_STRUCT *)((UINTN)Base + mSmmProfileSize);
+ mMsrDsAreaBase = (MSR_DS_AREA_STRUCT *)((UINTN)Base + mSmmProfileSize);
MsrDsAreaSizePerCpu = mMsrDsAreaSize / mMaxNumberOfCpus;
- mBTSRecordNumber = (MsrDsAreaSizePerCpu - sizeof(PEBS_RECORD) * PEBS_RECORD_NUMBER - sizeof(MSR_DS_AREA_STRUCT)) / sizeof(BRANCH_TRACE_RECORD);
+ mBTSRecordNumber = (MsrDsAreaSizePerCpu - sizeof (PEBS_RECORD) * PEBS_RECORD_NUMBER - sizeof (MSR_DS_AREA_STRUCT)) / sizeof (BRANCH_TRACE_RECORD);
for (Index = 0; Index < mMaxNumberOfCpus; Index++) {
mMsrDsArea[Index] = (MSR_DS_AREA_STRUCT *)((UINTN)mMsrDsAreaBase + MsrDsAreaSizePerCpu * Index);
- mMsrBTSRecord[Index] = (BRANCH_TRACE_RECORD *)((UINTN)mMsrDsArea[Index] + sizeof(MSR_DS_AREA_STRUCT));
- mMsrPEBSRecord[Index] = (PEBS_RECORD *)((UINTN)mMsrDsArea[Index] + MsrDsAreaSizePerCpu - sizeof(PEBS_RECORD) * PEBS_RECORD_NUMBER);
+ mMsrBTSRecord[Index] = (BRANCH_TRACE_RECORD *)((UINTN)mMsrDsArea[Index] + sizeof (MSR_DS_AREA_STRUCT));
+ mMsrPEBSRecord[Index] = (PEBS_RECORD *)((UINTN)mMsrDsArea[Index] + MsrDsAreaSizePerCpu - sizeof (PEBS_RECORD) * PEBS_RECORD_NUMBER);
- mMsrDsArea[Index]->BTSBufferBase = (UINTN)mMsrBTSRecord[Index];
- mMsrDsArea[Index]->BTSIndex = mMsrDsArea[Index]->BTSBufferBase;
- mMsrDsArea[Index]->BTSAbsoluteMaximum = mMsrDsArea[Index]->BTSBufferBase + mBTSRecordNumber * sizeof(BRANCH_TRACE_RECORD) + 1;
- mMsrDsArea[Index]->BTSInterruptThreshold = mMsrDsArea[Index]->BTSAbsoluteMaximum + 1;
+ mMsrDsArea[Index]->BTSBufferBase = (UINTN)mMsrBTSRecord[Index];
+ mMsrDsArea[Index]->BTSIndex = mMsrDsArea[Index]->BTSBufferBase;
+ mMsrDsArea[Index]->BTSAbsoluteMaximum = mMsrDsArea[Index]->BTSBufferBase + mBTSRecordNumber * sizeof (BRANCH_TRACE_RECORD) + 1;
+ mMsrDsArea[Index]->BTSInterruptThreshold = mMsrDsArea[Index]->BTSAbsoluteMaximum + 1;
mMsrDsArea[Index]->PEBSBufferBase = (UINTN)mMsrPEBSRecord[Index];
mMsrDsArea[Index]->PEBSIndex = mMsrDsArea[Index]->PEBSBufferBase;
- mMsrDsArea[Index]->PEBSAbsoluteMaximum = mMsrDsArea[Index]->PEBSBufferBase + PEBS_RECORD_NUMBER * sizeof(PEBS_RECORD) + 1;
+ mMsrDsArea[Index]->PEBSAbsoluteMaximum = mMsrDsArea[Index]->PEBSBufferBase + PEBS_RECORD_NUMBER * sizeof (PEBS_RECORD) + 1;
mMsrDsArea[Index]->PEBSInterruptThreshold = mMsrDsArea[Index]->PEBSAbsoluteMaximum + 1;
}
}
@@ -967,7 +1008,7 @@ InitSmmProfileInternal ( );
ASSERT_EFI_ERROR (Status);
- return ;
+ return;
}
/**
@@ -1056,12 +1097,13 @@ ActivateSingleStepDB ( VOID
)
{
- UINTN Dr6;
+ UINTN Dr6;
Dr6 = AsmReadDr6 ();
if ((Dr6 & DR6_SINGLE_STEP) != 0) {
return;
}
+
Dr6 |= DR6_SINGLE_STEP;
AsmWriteDr6 (Dr6);
}
@@ -1079,8 +1121,9 @@ ActivateLBR ( DebugCtl = AsmReadMsr64 (MSR_DEBUG_CTL);
if ((DebugCtl & MSR_DEBUG_CTL_LBR) != 0) {
- return ;
+ return;
}
+
DebugCtl |= MSR_DEBUG_CTL_LBR;
AsmWriteMsr64 (MSR_DEBUG_CTL, DebugCtl);
}
@@ -1093,14 +1136,14 @@ ActivateLBR ( **/
VOID
ActivateBTS (
- IN UINTN CpuIndex
+ IN UINTN CpuIndex
)
{
UINT64 DebugCtl;
DebugCtl = AsmReadMsr64 (MSR_DEBUG_CTL);
if ((DebugCtl & MSR_DEBUG_CTL_BTS) != 0) {
- return ;
+ return;
}
AsmWriteMsr64 (MSR_DS_AREA, (UINT64)(UINTN)mMsrDsArea[CpuIndex]);
@@ -1131,7 +1174,7 @@ SmmProfileRecordSmiNum ( **/
VOID
ActivateSmmProfile (
- IN UINTN CpuIndex
+ IN UINTN CpuIndex
)
{
//
@@ -1173,7 +1216,8 @@ InitSmmProfile ( //
if (!FeaturePcdGet (PcdCpuSmmProfileEnable) &&
!HEAP_GUARD_NONSTOP_MODE &&
- !NULL_DETECTION_NONSTOP_MODE) {
+ !NULL_DETECTION_NONSTOP_MODE)
+ {
return;
}
@@ -1206,19 +1250,19 @@ InitSmmProfile ( **/
VOID
RestorePageTableBelow4G (
- UINT64 *PageTable,
- UINT64 PFAddress,
- UINTN CpuIndex,
- UINTN ErrorCode
+ UINT64 *PageTable,
+ UINT64 PFAddress,
+ UINTN CpuIndex,
+ UINTN ErrorCode
)
{
- UINTN PTIndex;
- UINTN PFIndex;
- IA32_CR4 Cr4;
- BOOLEAN Enable5LevelPaging;
+ UINTN PTIndex;
+ UINTN PFIndex;
+ IA32_CR4 Cr4;
+ BOOLEAN Enable5LevelPaging;
- Cr4.UintN = AsmReadCr4 ();
- Enable5LevelPaging = (BOOLEAN) (Cr4.Bits.LA57 == 1);
+ Cr4.UintN = AsmReadCr4 ();
+ Enable5LevelPaging = (BOOLEAN)(Cr4.Bits.LA57 == 1);
//
// PML5
@@ -1226,16 +1270,16 @@ RestorePageTableBelow4G ( if (Enable5LevelPaging) {
PTIndex = (UINTN)BitFieldRead64 (PFAddress, 48, 56);
ASSERT (PageTable[PTIndex] != 0);
- PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & PHYSICAL_ADDRESS_MASK);
+ PageTable = (UINT64 *)(UINTN)(PageTable[PTIndex] & PHYSICAL_ADDRESS_MASK);
}
//
// PML4
//
- if (sizeof(UINT64) == sizeof(UINTN)) {
+ if (sizeof (UINT64) == sizeof (UINTN)) {
PTIndex = (UINTN)BitFieldRead64 (PFAddress, 39, 47);
ASSERT (PageTable[PTIndex] != 0);
- PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & PHYSICAL_ADDRESS_MASK);
+ PageTable = (UINT64 *)(UINTN)(PageTable[PTIndex] & PHYSICAL_ADDRESS_MASK);
}
//
@@ -1243,7 +1287,7 @@ RestorePageTableBelow4G ( //
PTIndex = (UINTN)BitFieldRead64 (PFAddress, 30, 38);
ASSERT (PageTable[PTIndex] != 0);
- PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & PHYSICAL_ADDRESS_MASK);
+ PageTable = (UINT64 *)(UINTN)(PageTable[PTIndex] & PHYSICAL_ADDRESS_MASK);
//
// PD
@@ -1261,7 +1305,7 @@ RestorePageTableBelow4G ( //
ASSERT (mPFEntryCount[CpuIndex] < MAX_PF_ENTRY_COUNT);
if (mPFEntryCount[CpuIndex] < MAX_PF_ENTRY_COUNT) {
- PFIndex = mPFEntryCount[CpuIndex];
+ PFIndex = mPFEntryCount[CpuIndex];
mLastPFEntryValue[CpuIndex][PFIndex] = PageTable[PTIndex];
mLastPFEntryPointer[CpuIndex][PFIndex] = &PageTable[PTIndex];
mPFEntryCount[CpuIndex]++;
@@ -1270,7 +1314,7 @@ RestorePageTableBelow4G ( //
// Set new entry
//
- PageTable[PTIndex] = (PFAddress & ~((1ull << 21) - 1));
+ PageTable[PTIndex] = (PFAddress & ~((1ull << 21) - 1));
PageTable[PTIndex] |= (UINT64)IA32_PG_PS;
PageTable[PTIndex] |= (UINT64)PAGE_ATTRIBUTE_BITS;
if ((ErrorCode & IA32_PF_EC_ID) != 0) {
@@ -1281,7 +1325,7 @@ RestorePageTableBelow4G ( // Small page
//
ASSERT (PageTable[PTIndex] != 0);
- PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & PHYSICAL_ADDRESS_MASK);
+ PageTable = (UINT64 *)(UINTN)(PageTable[PTIndex] & PHYSICAL_ADDRESS_MASK);
//
// 4K PTE
@@ -1295,7 +1339,7 @@ RestorePageTableBelow4G ( //
ASSERT (mPFEntryCount[CpuIndex] < MAX_PF_ENTRY_COUNT);
if (mPFEntryCount[CpuIndex] < MAX_PF_ENTRY_COUNT) {
- PFIndex = mPFEntryCount[CpuIndex];
+ PFIndex = mPFEntryCount[CpuIndex];
mLastPFEntryValue[CpuIndex][PFIndex] = PageTable[PTIndex];
mLastPFEntryPointer[CpuIndex][PFIndex] = &PageTable[PTIndex];
mPFEntryCount[CpuIndex]++;
@@ -1304,7 +1348,7 @@ RestorePageTableBelow4G ( //
// Set new entry
//
- PageTable[PTIndex] = (PFAddress & ~((1ull << 12) - 1));
+ PageTable[PTIndex] = (PFAddress & ~((1ull << 12) - 1));
PageTable[PTIndex] |= (UINT64)PAGE_ATTRIBUTE_BITS;
if ((ErrorCode & IA32_PF_EC_ID) != 0) {
PageTable[PTIndex] &= ~IA32_PG_NX;
@@ -1320,18 +1364,18 @@ RestorePageTableBelow4G ( **/
VOID
GuardPagePFHandler (
- UINTN ErrorCode
+ UINTN ErrorCode
)
{
- UINT64 *PageTable;
- UINT64 PFAddress;
- UINT64 RestoreAddress;
- UINTN RestorePageNumber;
- UINTN CpuIndex;
+ UINT64 *PageTable;
+ UINT64 PFAddress;
+ UINT64 RestoreAddress;
+ UINTN RestorePageNumber;
+ UINTN CpuIndex;
- PageTable = (UINT64 *)AsmReadCr3 ();
- PFAddress = AsmReadCr2 ();
- CpuIndex = GetCpuIndex ();
+ PageTable = (UINT64 *)AsmReadCr3 ();
+ PFAddress = AsmReadCr2 ();
+ CpuIndex = GetCpuIndex ();
//
// Memory operation cross pages, like "rep mov" instruction, will cause
@@ -1339,7 +1383,7 @@ GuardPagePFHandler ( // that current page and the page followed are both in PRESENT state.
//
RestorePageNumber = 2;
- RestoreAddress = PFAddress;
+ RestoreAddress = PFAddress;
while (RestorePageNumber > 0) {
RestorePageTableBelow4G (PageTable, RestoreAddress, CpuIndex, ErrorCode);
RestoreAddress += EFI_PAGE_SIZE;
@@ -1361,25 +1405,25 @@ GuardPagePFHandler ( **/
VOID
SmmProfilePFHandler (
- UINTN Rip,
- UINTN ErrorCode
+ UINTN Rip,
+ UINTN ErrorCode
)
{
- UINT64 *PageTable;
- UINT64 PFAddress;
- UINT64 RestoreAddress;
- UINTN RestorePageNumber;
- UINTN CpuIndex;
- UINTN Index;
- UINT64 InstructionAddress;
- UINTN MaxEntryNumber;
- UINTN CurrentEntryNumber;
- BOOLEAN IsValidPFAddress;
- SMM_PROFILE_ENTRY *SmmProfileEntry;
- UINT64 SmiCommand;
- EFI_STATUS Status;
- UINT8 SoftSmiValue;
- EFI_SMM_SAVE_STATE_IO_INFO IoInfo;
+ UINT64 *PageTable;
+ UINT64 PFAddress;
+ UINT64 RestoreAddress;
+ UINTN RestorePageNumber;
+ UINTN CpuIndex;
+ UINTN Index;
+ UINT64 InstructionAddress;
+ UINTN MaxEntryNumber;
+ UINTN CurrentEntryNumber;
+ BOOLEAN IsValidPFAddress;
+ SMM_PROFILE_ENTRY *SmmProfileEntry;
+ UINT64 SmiCommand;
+ EFI_STATUS Status;
+ UINT8 SoftSmiValue;
+ EFI_SMM_SAVE_STATE_IO_INFO IoInfo;
if (!mSmmProfileStart) {
//
@@ -1393,10 +1437,10 @@ SmmProfilePFHandler ( DisableBTS ();
}
- IsValidPFAddress = FALSE;
- PageTable = (UINT64 *)AsmReadCr3 ();
- PFAddress = AsmReadCr2 ();
- CpuIndex = GetCpuIndex ();
+ IsValidPFAddress = FALSE;
+ PageTable = (UINT64 *)AsmReadCr3 ();
+ PFAddress = AsmReadCr2 ();
+ CpuIndex = GetCpuIndex ();
//
// Memory operation cross pages, like "rep mov" instruction, will cause
@@ -1404,20 +1448,21 @@ SmmProfilePFHandler ( // that current page and the page followed are both in PRESENT state.
//
RestorePageNumber = 2;
- RestoreAddress = PFAddress;
+ RestoreAddress = PFAddress;
while (RestorePageNumber > 0) {
if (RestoreAddress <= 0xFFFFFFFF) {
RestorePageTableBelow4G (PageTable, RestoreAddress, CpuIndex, ErrorCode);
} else {
RestorePageTableAbove4G (PageTable, RestoreAddress, CpuIndex, ErrorCode, &IsValidPFAddress);
}
+
RestoreAddress += EFI_PAGE_SIZE;
RestorePageNumber--;
}
if (!IsValidPFAddress) {
InstructionAddress = Rip;
- if ((ErrorCode & IA32_PF_EC_ID) != 0 && (mBtsSupported)) {
+ if (((ErrorCode & IA32_PF_EC_ID) != 0) && (mBtsSupported)) {
//
// If it is instruction fetch failure, get the correct IP from BTS.
//
@@ -1434,18 +1479,19 @@ SmmProfilePFHandler ( //
// Indicate it is not software SMI
//
- SmiCommand = 0xFFFFFFFFFFFFFFFFULL;
+ SmiCommand = 0xFFFFFFFFFFFFFFFFULL;
for (Index = 0; Index < gSmst->NumberOfCpus; Index++) {
- Status = SmmReadSaveState(&mSmmCpu, sizeof(IoInfo), EFI_SMM_SAVE_STATE_REGISTER_IO, Index, &IoInfo);
+ Status = SmmReadSaveState (&mSmmCpu, sizeof (IoInfo), EFI_SMM_SAVE_STATE_REGISTER_IO, Index, &IoInfo);
if (EFI_ERROR (Status)) {
continue;
}
+
if (IoInfo.IoPort == mSmiCommandPort) {
//
// A software SMI triggered by SMI command port has been found, get SmiCommand from SMI command port.
//
SoftSmiValue = IoRead8 (mSmiCommandPort);
- SmiCommand = (UINT64)SoftSmiValue;
+ SmiCommand = (UINT64)SoftSmiValue;
break;
}
}
@@ -1454,24 +1500,27 @@ SmmProfilePFHandler ( //
// Check if there is already a same entry in profile data.
//
- for (Index = 0; Index < (UINTN) mSmmProfileBase->CurDataEntries; Index++) {
+ for (Index = 0; Index < (UINTN)mSmmProfileBase->CurDataEntries; Index++) {
if ((SmmProfileEntry[Index].ErrorCode == (UINT64)ErrorCode) &&
(SmmProfileEntry[Index].Address == PFAddress) &&
(SmmProfileEntry[Index].CpuNum == (UINT64)CpuIndex) &&
(SmmProfileEntry[Index].Instruction == InstructionAddress) &&
- (SmmProfileEntry[Index].SmiCmd == SmiCommand)) {
+ (SmmProfileEntry[Index].SmiCmd == SmiCommand))
+ {
//
// Same record exist, need not save again.
//
break;
}
}
+
if (Index == mSmmProfileBase->CurDataEntries) {
- CurrentEntryNumber = (UINTN) mSmmProfileBase->CurDataEntries;
- MaxEntryNumber = (UINTN) mSmmProfileBase->MaxDataEntries;
+ CurrentEntryNumber = (UINTN)mSmmProfileBase->CurDataEntries;
+ MaxEntryNumber = (UINTN)mSmmProfileBase->MaxDataEntries;
if (FeaturePcdGet (PcdCpuSmmProfileRingBuffer)) {
CurrentEntryNumber = CurrentEntryNumber % MaxEntryNumber;
}
+
if (CurrentEntryNumber < MaxEntryNumber) {
//
// Log the new entry
@@ -1491,6 +1540,7 @@ SmmProfilePFHandler ( }
}
}
+
//
// Flush TLB
//
@@ -1511,7 +1561,7 @@ InitIdtr ( VOID
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
Status = SmmRegisterExceptionHandler (&mSmmCpuService, EXCEPT_IA32_DEBUG, DebugExceptionHandler);
ASSERT_EFI_ERROR (Status);
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.h b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.h index 484d81eb00..1a82ac05ce 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.h +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.h @@ -23,7 +23,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/
VOID
ActivateSmmProfile (
- IN UINTN CpuIndex
+ IN UINTN CpuIndex
);
/**
@@ -55,8 +55,8 @@ SmmProfileRecordSmiNum ( **/
VOID
SmmProfilePFHandler (
- UINTN Rip,
- UINTN ErrorCode
+ UINTN Rip,
+ UINTN ErrorCode
);
/**
@@ -80,7 +80,6 @@ PageFaultIdtHandlerSmmProfile ( VOID
);
-
/**
Check if feature is supported by a processor.
@@ -116,20 +115,20 @@ GetCpuIndex ( **/
VOID
GuardPagePFHandler (
- UINTN ErrorCode
+ UINTN ErrorCode
);
//
// The flag indicates if execute-disable is supported by processor.
//
-extern BOOLEAN mXdSupported;
+extern BOOLEAN mXdSupported;
//
// The flag indicates if execute-disable is enabled on processor.
//
-extern BOOLEAN mXdEnabled;
+extern BOOLEAN mXdEnabled;
//
// The flag indicates if #DB will be setup in #PF handler.
//
-extern BOOLEAN mSetupDebugTrap;
+extern BOOLEAN mSetupDebugTrap;
#endif // _SMM_PROFILE_H_
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h index 993360a8a8..0e60509e20 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h @@ -22,41 +22,41 @@ SPDX-License-Identifier: BSD-2-Clause-Patent //
// Configure the SMM_PROFILE DTS region size
//
-#define SMM_PROFILE_DTS_SIZE (4 * 1024 * 1024) // 4M
+#define SMM_PROFILE_DTS_SIZE (4 * 1024 * 1024) // 4M
-#define MAX_PF_PAGE_COUNT 0x2
+#define MAX_PF_PAGE_COUNT 0x2
-#define PEBS_RECORD_NUMBER 0x2
+#define PEBS_RECORD_NUMBER 0x2
-#define MAX_PF_ENTRY_COUNT 10
+#define MAX_PF_ENTRY_COUNT 10
//
// This MACRO just enable unit test for the profile
// Please disable it.
//
-#define IA32_PF_EC_ID (1u << 4)
+#define IA32_PF_EC_ID (1u << 4)
-#define SMM_PROFILE_NAME L"SmmProfileData"
+#define SMM_PROFILE_NAME L"SmmProfileData"
//
// CPU generic definition
//
-#define CPUID1_EDX_XD_SUPPORT 0x100000
-#define MSR_EFER 0xc0000080
-#define MSR_EFER_XD 0x800
+#define CPUID1_EDX_XD_SUPPORT 0x100000
+#define MSR_EFER 0xc0000080
+#define MSR_EFER_XD 0x800
-#define CPUID1_EDX_BTS_AVAILABLE 0x200000
+#define CPUID1_EDX_BTS_AVAILABLE 0x200000
-#define DR6_SINGLE_STEP 0x4000
-#define RFLAG_TF 0x100
+#define DR6_SINGLE_STEP 0x4000
+#define RFLAG_TF 0x100
-#define MSR_DEBUG_CTL 0x1D9
-#define MSR_DEBUG_CTL_LBR 0x1
-#define MSR_DEBUG_CTL_TR 0x40
-#define MSR_DEBUG_CTL_BTS 0x80
-#define MSR_DEBUG_CTL_BTINT 0x100
-#define MSR_DS_AREA 0x600
+#define MSR_DEBUG_CTL 0x1D9
+#define MSR_DEBUG_CTL_LBR 0x1
+#define MSR_DEBUG_CTL_TR 0x40
+#define MSR_DEBUG_CTL_BTS 0x80
+#define MSR_DEBUG_CTL_BTINT 0x100
+#define MSR_DS_AREA 0x600
#define HEAP_GUARD_NONSTOP_MODE \
((PcdGet8 (PcdHeapGuardPropertyMask) & (BIT6|BIT3|BIT2)) > BIT6)
@@ -65,45 +65,45 @@ SPDX-License-Identifier: BSD-2-Clause-Patent ((PcdGet8 (PcdNullPointerDetectionPropertyMask) & (BIT6|BIT1)) > BIT6)
typedef struct {
- EFI_PHYSICAL_ADDRESS Base;
- EFI_PHYSICAL_ADDRESS Top;
+ EFI_PHYSICAL_ADDRESS Base;
+ EFI_PHYSICAL_ADDRESS Top;
} MEMORY_RANGE;
typedef struct {
- MEMORY_RANGE Range;
- BOOLEAN Present;
- BOOLEAN Nx;
+ MEMORY_RANGE Range;
+ BOOLEAN Present;
+ BOOLEAN Nx;
} MEMORY_PROTECTION_RANGE;
typedef struct {
- UINT64 HeaderSize;
- UINT64 MaxDataEntries;
- UINT64 MaxDataSize;
- UINT64 CurDataEntries;
- UINT64 CurDataSize;
- UINT64 TsegStart;
- UINT64 TsegSize;
- UINT64 NumSmis;
- UINT64 NumCpus;
+ UINT64 HeaderSize;
+ UINT64 MaxDataEntries;
+ UINT64 MaxDataSize;
+ UINT64 CurDataEntries;
+ UINT64 CurDataSize;
+ UINT64 TsegStart;
+ UINT64 TsegSize;
+ UINT64 NumSmis;
+ UINT64 NumCpus;
} SMM_PROFILE_HEADER;
typedef struct {
- UINT64 SmiNum;
- UINT64 CpuNum;
- UINT64 ApicId;
- UINT64 ErrorCode;
- UINT64 Instruction;
- UINT64 Address;
- UINT64 SmiCmd;
+ UINT64 SmiNum;
+ UINT64 CpuNum;
+ UINT64 ApicId;
+ UINT64 ErrorCode;
+ UINT64 Instruction;
+ UINT64 Address;
+ UINT64 SmiCmd;
} SMM_PROFILE_ENTRY;
-extern SMM_S3_RESUME_STATE *mSmmS3ResumeState;
-extern UINTN gSmiExceptionHandlers[];
-extern BOOLEAN mXdSupported;
-X86_ASSEMBLY_PATCH_LABEL gPatchXdSupported;
-X86_ASSEMBLY_PATCH_LABEL gPatchMsrIa32MiscEnableSupported;
-extern UINTN *mPFEntryCount;
-extern UINT64 (*mLastPFEntryValue)[MAX_PF_ENTRY_COUNT];
+extern SMM_S3_RESUME_STATE *mSmmS3ResumeState;
+extern UINTN gSmiExceptionHandlers[];
+extern BOOLEAN mXdSupported;
+X86_ASSEMBLY_PATCH_LABEL gPatchXdSupported;
+X86_ASSEMBLY_PATCH_LABEL gPatchMsrIa32MiscEnableSupported;
+extern UINTN *mPFEntryCount;
+extern UINT64 (*mLastPFEntryValue)[MAX_PF_ENTRY_COUNT];
extern UINT64 *(*mLastPFEntryPointer)[MAX_PF_ENTRY_COUNT];
//
@@ -127,7 +127,7 @@ InitIdtr ( **/
BOOLEAN
IsAddressSplit (
- IN EFI_PHYSICAL_ADDRESS Address
+ IN EFI_PHYSICAL_ADDRESS Address
);
/**
@@ -139,8 +139,8 @@ IsAddressSplit ( **/
BOOLEAN
IsAddressValid (
- IN EFI_PHYSICAL_ADDRESS Address,
- IN BOOLEAN *Nx
+ IN EFI_PHYSICAL_ADDRESS Address,
+ IN BOOLEAN *Nx
);
/**
@@ -161,7 +161,7 @@ SmiDefaultPFHandler ( **/
VOID
ClearTrapFlag (
- IN OUT EFI_SYSTEM_CONTEXT SystemContext
+ IN OUT EFI_SYSTEM_CONTEXT SystemContext
);
#endif // _SMM_PROFILE_H_
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c b/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c index 518978c1d9..c8ddc6083d 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c @@ -18,53 +18,53 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include "PiSmmCpuDxeSmm.h"
typedef struct {
- UINT64 Signature; // Offset 0x00
- UINT16 Reserved1; // Offset 0x08
- UINT16 Reserved2; // Offset 0x0A
- UINT16 Reserved3; // Offset 0x0C
- UINT16 SmmCs; // Offset 0x0E
- UINT16 SmmDs; // Offset 0x10
- UINT16 SmmSs; // Offset 0x12
- UINT16 SmmOtherSegment; // Offset 0x14
- UINT16 Reserved4; // Offset 0x16
- UINT64 Reserved5; // Offset 0x18
- UINT64 Reserved6; // Offset 0x20
- UINT64 Reserved7; // Offset 0x28
- UINT64 SmmGdtPtr; // Offset 0x30
- UINT32 SmmGdtSize; // Offset 0x38
- UINT32 Reserved8; // Offset 0x3C
- UINT64 Reserved9; // Offset 0x40
- UINT64 Reserved10; // Offset 0x48
- UINT16 Reserved11; // Offset 0x50
- UINT16 Reserved12; // Offset 0x52
- UINT32 Reserved13; // Offset 0x54
- UINT64 Reserved14; // Offset 0x58
+ UINT64 Signature; // Offset 0x00
+ UINT16 Reserved1; // Offset 0x08
+ UINT16 Reserved2; // Offset 0x0A
+ UINT16 Reserved3; // Offset 0x0C
+ UINT16 SmmCs; // Offset 0x0E
+ UINT16 SmmDs; // Offset 0x10
+ UINT16 SmmSs; // Offset 0x12
+ UINT16 SmmOtherSegment; // Offset 0x14
+ UINT16 Reserved4; // Offset 0x16
+ UINT64 Reserved5; // Offset 0x18
+ UINT64 Reserved6; // Offset 0x20
+ UINT64 Reserved7; // Offset 0x28
+ UINT64 SmmGdtPtr; // Offset 0x30
+ UINT32 SmmGdtSize; // Offset 0x38
+ UINT32 Reserved8; // Offset 0x3C
+ UINT64 Reserved9; // Offset 0x40
+ UINT64 Reserved10; // Offset 0x48
+ UINT16 Reserved11; // Offset 0x50
+ UINT16 Reserved12; // Offset 0x52
+ UINT32 Reserved13; // Offset 0x54
+ UINT64 Reserved14; // Offset 0x58
} PROCESSOR_SMM_DESCRIPTOR;
-extern CONST PROCESSOR_SMM_DESCRIPTOR gcPsd;
+extern CONST PROCESSOR_SMM_DESCRIPTOR gcPsd;
//
// EFER register LMA bit
//
-#define LMA BIT10
+#define LMA BIT10
///
/// Macro used to simplify the lookup table entries of type CPU_SMM_SAVE_STATE_LOOKUP_ENTRY
///
-#define SMM_CPU_OFFSET(Field) OFFSET_OF (SMRAM_SAVE_STATE_MAP, Field)
+#define SMM_CPU_OFFSET(Field) OFFSET_OF (SMRAM_SAVE_STATE_MAP, Field)
///
/// Macro used to simplify the lookup table entries of type CPU_SMM_SAVE_STATE_REGISTER_RANGE
///
-#define SMM_REGISTER_RANGE(Start, End) { Start, End, End - Start + 1 }
+#define SMM_REGISTER_RANGE(Start, End) { Start, End, End - Start + 1 }
///
/// Structure used to describe a range of registers
///
typedef struct {
- EFI_SMM_SAVE_STATE_REGISTER Start;
- EFI_SMM_SAVE_STATE_REGISTER End;
- UINTN Length;
+ EFI_SMM_SAVE_STATE_REGISTER Start;
+ EFI_SMM_SAVE_STATE_REGISTER End;
+ UINTN Length;
} CPU_SMM_SAVE_STATE_REGISTER_RANGE;
///
@@ -72,36 +72,36 @@ typedef struct { /// associated with each supported EFI_SMM_SAVE_STATE_REGISTER value
///
-#define SMM_SAVE_STATE_REGISTER_SMMREVID_INDEX 1
-#define SMM_SAVE_STATE_REGISTER_IOMISC_INDEX 2
-#define SMM_SAVE_STATE_REGISTER_IOMEMADDR_INDEX 3
-#define SMM_SAVE_STATE_REGISTER_MAX_INDEX 4
+#define SMM_SAVE_STATE_REGISTER_SMMREVID_INDEX 1
+#define SMM_SAVE_STATE_REGISTER_IOMISC_INDEX 2
+#define SMM_SAVE_STATE_REGISTER_IOMEMADDR_INDEX 3
+#define SMM_SAVE_STATE_REGISTER_MAX_INDEX 4
typedef struct {
- UINT8 Width32;
- UINT8 Width64;
- UINT16 Offset32;
- UINT16 Offset64Lo;
- UINT16 Offset64Hi;
- BOOLEAN Writeable;
+ UINT8 Width32;
+ UINT8 Width64;
+ UINT16 Offset32;
+ UINT16 Offset64Lo;
+ UINT16 Offset64Hi;
+ BOOLEAN Writeable;
} CPU_SMM_SAVE_STATE_LOOKUP_ENTRY;
///
/// Structure used to build a lookup table for the IOMisc width information
///
typedef struct {
- UINT8 Width;
- EFI_SMM_SAVE_STATE_IO_WIDTH IoWidth;
+ UINT8 Width;
+ EFI_SMM_SAVE_STATE_IO_WIDTH IoWidth;
} CPU_SMM_SAVE_STATE_IO_WIDTH;
///
/// Variables from SMI Handler
///
-X86_ASSEMBLY_PATCH_LABEL gPatchSmbase;
-X86_ASSEMBLY_PATCH_LABEL gPatchSmiStack;
-X86_ASSEMBLY_PATCH_LABEL gPatchSmiCr3;
-extern volatile UINT8 gcSmiHandlerTemplate[];
-extern CONST UINT16 gcSmiHandlerSize;
+X86_ASSEMBLY_PATCH_LABEL gPatchSmbase;
+X86_ASSEMBLY_PATCH_LABEL gPatchSmiStack;
+X86_ASSEMBLY_PATCH_LABEL gPatchSmiCr3;
+extern volatile UINT8 gcSmiHandlerTemplate[];
+extern CONST UINT16 gcSmiHandlerSize;
//
// Variables used by SMI Handler
@@ -112,76 +112,76 @@ IA32_DESCRIPTOR gSmiHandlerIdtr; /// Table used by GetRegisterIndex() to convert an EFI_SMM_SAVE_STATE_REGISTER
/// value to an index into a table of type CPU_SMM_SAVE_STATE_LOOKUP_ENTRY
///
-CONST CPU_SMM_SAVE_STATE_REGISTER_RANGE mSmmCpuRegisterRanges[] = {
+CONST CPU_SMM_SAVE_STATE_REGISTER_RANGE mSmmCpuRegisterRanges[] = {
SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_GDTBASE, EFI_SMM_SAVE_STATE_REGISTER_LDTINFO),
SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_ES, EFI_SMM_SAVE_STATE_REGISTER_RIP),
SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_RFLAGS, EFI_SMM_SAVE_STATE_REGISTER_CR4),
- { (EFI_SMM_SAVE_STATE_REGISTER)0, (EFI_SMM_SAVE_STATE_REGISTER)0, 0 }
+ { (EFI_SMM_SAVE_STATE_REGISTER)0, (EFI_SMM_SAVE_STATE_REGISTER)0, 0}
};
///
/// Lookup table used to retrieve the widths and offsets associated with each
/// supported EFI_SMM_SAVE_STATE_REGISTER value
///
-CONST CPU_SMM_SAVE_STATE_LOOKUP_ENTRY mSmmCpuWidthOffset[] = {
- {0, 0, 0, 0, 0, FALSE}, // Reserved
+CONST CPU_SMM_SAVE_STATE_LOOKUP_ENTRY mSmmCpuWidthOffset[] = {
+ { 0, 0, 0, 0, 0, FALSE }, // Reserved
//
// Internally defined CPU Save State Registers. Not defined in PI SMM CPU Protocol.
//
- {4, 4, SMM_CPU_OFFSET (x86.SMMRevId) , SMM_CPU_OFFSET (x64.SMMRevId) , 0 , FALSE}, // SMM_SAVE_STATE_REGISTER_SMMREVID_INDEX = 1
- {4, 4, SMM_CPU_OFFSET (x86.IOMisc) , SMM_CPU_OFFSET (x64.IOMisc) , 0 , FALSE}, // SMM_SAVE_STATE_REGISTER_IOMISC_INDEX = 2
- {4, 8, SMM_CPU_OFFSET (x86.IOMemAddr) , SMM_CPU_OFFSET (x64.IOMemAddr) , SMM_CPU_OFFSET (x64.IOMemAddr) + 4, FALSE}, // SMM_SAVE_STATE_REGISTER_IOMEMADDR_INDEX = 3
+ { 4, 4, SMM_CPU_OFFSET (x86.SMMRevId), SMM_CPU_OFFSET (x64.SMMRevId), 0, FALSE }, // SMM_SAVE_STATE_REGISTER_SMMREVID_INDEX = 1
+ { 4, 4, SMM_CPU_OFFSET (x86.IOMisc), SMM_CPU_OFFSET (x64.IOMisc), 0, FALSE }, // SMM_SAVE_STATE_REGISTER_IOMISC_INDEX = 2
+ { 4, 8, SMM_CPU_OFFSET (x86.IOMemAddr), SMM_CPU_OFFSET (x64.IOMemAddr), SMM_CPU_OFFSET (x64.IOMemAddr) + 4, FALSE }, // SMM_SAVE_STATE_REGISTER_IOMEMADDR_INDEX = 3
//
// CPU Save State registers defined in PI SMM CPU Protocol.
//
- {0, 8, 0 , SMM_CPU_OFFSET (x64.GdtBaseLoDword) , SMM_CPU_OFFSET (x64.GdtBaseHiDword), FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_GDTBASE = 4
- {0, 8, 0 , SMM_CPU_OFFSET (x64.IdtBaseLoDword) , SMM_CPU_OFFSET (x64.IdtBaseHiDword), FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_IDTBASE = 5
- {0, 8, 0 , SMM_CPU_OFFSET (x64.LdtBaseLoDword) , SMM_CPU_OFFSET (x64.LdtBaseHiDword), FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_LDTBASE = 6
- {0, 0, 0 , 0 , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_GDTLIMIT = 7
- {0, 0, 0 , 0 , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_IDTLIMIT = 8
- {0, 0, 0 , 0 , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_LDTLIMIT = 9
- {0, 0, 0 , 0 , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_LDTINFO = 10
-
- {4, 4, SMM_CPU_OFFSET (x86._ES) , SMM_CPU_OFFSET (x64._ES) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_ES = 20
- {4, 4, SMM_CPU_OFFSET (x86._CS) , SMM_CPU_OFFSET (x64._CS) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CS = 21
- {4, 4, SMM_CPU_OFFSET (x86._SS) , SMM_CPU_OFFSET (x64._SS) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_SS = 22
- {4, 4, SMM_CPU_OFFSET (x86._DS) , SMM_CPU_OFFSET (x64._DS) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_DS = 23
- {4, 4, SMM_CPU_OFFSET (x86._FS) , SMM_CPU_OFFSET (x64._FS) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_FS = 24
- {4, 4, SMM_CPU_OFFSET (x86._GS) , SMM_CPU_OFFSET (x64._GS) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_GS = 25
- {0, 4, 0 , SMM_CPU_OFFSET (x64._LDTR) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_LDTR_SEL = 26
- {4, 4, SMM_CPU_OFFSET (x86._TR) , SMM_CPU_OFFSET (x64._TR) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_TR_SEL = 27
- {4, 8, SMM_CPU_OFFSET (x86._DR7) , SMM_CPU_OFFSET (x64._DR7) , SMM_CPU_OFFSET (x64._DR7) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_DR7 = 28
- {4, 8, SMM_CPU_OFFSET (x86._DR6) , SMM_CPU_OFFSET (x64._DR6) , SMM_CPU_OFFSET (x64._DR6) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_DR6 = 29
- {0, 8, 0 , SMM_CPU_OFFSET (x64._R8) , SMM_CPU_OFFSET (x64._R8) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R8 = 30
- {0, 8, 0 , SMM_CPU_OFFSET (x64._R9) , SMM_CPU_OFFSET (x64._R9) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R9 = 31
- {0, 8, 0 , SMM_CPU_OFFSET (x64._R10) , SMM_CPU_OFFSET (x64._R10) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R10 = 32
- {0, 8, 0 , SMM_CPU_OFFSET (x64._R11) , SMM_CPU_OFFSET (x64._R11) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R11 = 33
- {0, 8, 0 , SMM_CPU_OFFSET (x64._R12) , SMM_CPU_OFFSET (x64._R12) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R12 = 34
- {0, 8, 0 , SMM_CPU_OFFSET (x64._R13) , SMM_CPU_OFFSET (x64._R13) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R13 = 35
- {0, 8, 0 , SMM_CPU_OFFSET (x64._R14) , SMM_CPU_OFFSET (x64._R14) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R14 = 36
- {0, 8, 0 , SMM_CPU_OFFSET (x64._R15) , SMM_CPU_OFFSET (x64._R15) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R15 = 37
- {4, 8, SMM_CPU_OFFSET (x86._EAX) , SMM_CPU_OFFSET (x64._RAX) , SMM_CPU_OFFSET (x64._RAX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RAX = 38
- {4, 8, SMM_CPU_OFFSET (x86._EBX) , SMM_CPU_OFFSET (x64._RBX) , SMM_CPU_OFFSET (x64._RBX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RBX = 39
- {4, 8, SMM_CPU_OFFSET (x86._ECX) , SMM_CPU_OFFSET (x64._RCX) , SMM_CPU_OFFSET (x64._RCX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RCX = 40
- {4, 8, SMM_CPU_OFFSET (x86._EDX) , SMM_CPU_OFFSET (x64._RDX) , SMM_CPU_OFFSET (x64._RDX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RDX = 41
- {4, 8, SMM_CPU_OFFSET (x86._ESP) , SMM_CPU_OFFSET (x64._RSP) , SMM_CPU_OFFSET (x64._RSP) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RSP = 42
- {4, 8, SMM_CPU_OFFSET (x86._EBP) , SMM_CPU_OFFSET (x64._RBP) , SMM_CPU_OFFSET (x64._RBP) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RBP = 43
- {4, 8, SMM_CPU_OFFSET (x86._ESI) , SMM_CPU_OFFSET (x64._RSI) , SMM_CPU_OFFSET (x64._RSI) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RSI = 44
- {4, 8, SMM_CPU_OFFSET (x86._EDI) , SMM_CPU_OFFSET (x64._RDI) , SMM_CPU_OFFSET (x64._RDI) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RDI = 45
- {4, 8, SMM_CPU_OFFSET (x86._EIP) , SMM_CPU_OFFSET (x64._RIP) , SMM_CPU_OFFSET (x64._RIP) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RIP = 46
-
- {4, 8, SMM_CPU_OFFSET (x86._EFLAGS) , SMM_CPU_OFFSET (x64._RFLAGS) , SMM_CPU_OFFSET (x64._RFLAGS) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RFLAGS = 51
- {4, 8, SMM_CPU_OFFSET (x86._CR0) , SMM_CPU_OFFSET (x64._CR0) , SMM_CPU_OFFSET (x64._CR0) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CR0 = 52
- {4, 8, SMM_CPU_OFFSET (x86._CR3) , SMM_CPU_OFFSET (x64._CR3) , SMM_CPU_OFFSET (x64._CR3) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CR3 = 53
- {0, 4, 0 , SMM_CPU_OFFSET (x64._CR4) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CR4 = 54
+ { 0, 8, 0, SMM_CPU_OFFSET (x64.GdtBaseLoDword), SMM_CPU_OFFSET (x64.GdtBaseHiDword), FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_GDTBASE = 4
+ { 0, 8, 0, SMM_CPU_OFFSET (x64.IdtBaseLoDword), SMM_CPU_OFFSET (x64.IdtBaseHiDword), FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_IDTBASE = 5
+ { 0, 8, 0, SMM_CPU_OFFSET (x64.LdtBaseLoDword), SMM_CPU_OFFSET (x64.LdtBaseHiDword), FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_LDTBASE = 6
+ { 0, 0, 0, 0, 0, FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_GDTLIMIT = 7
+ { 0, 0, 0, 0, 0, FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_IDTLIMIT = 8
+ { 0, 0, 0, 0, 0, FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_LDTLIMIT = 9
+ { 0, 0, 0, 0, 0, FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_LDTINFO = 10
+
+ { 4, 4, SMM_CPU_OFFSET (x86._ES), SMM_CPU_OFFSET (x64._ES), 0, FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_ES = 20
+ { 4, 4, SMM_CPU_OFFSET (x86._CS), SMM_CPU_OFFSET (x64._CS), 0, FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_CS = 21
+ { 4, 4, SMM_CPU_OFFSET (x86._SS), SMM_CPU_OFFSET (x64._SS), 0, FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_SS = 22
+ { 4, 4, SMM_CPU_OFFSET (x86._DS), SMM_CPU_OFFSET (x64._DS), 0, FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_DS = 23
+ { 4, 4, SMM_CPU_OFFSET (x86._FS), SMM_CPU_OFFSET (x64._FS), 0, FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_FS = 24
+ { 4, 4, SMM_CPU_OFFSET (x86._GS), SMM_CPU_OFFSET (x64._GS), 0, FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_GS = 25
+ { 0, 4, 0, SMM_CPU_OFFSET (x64._LDTR), 0, FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_LDTR_SEL = 26
+ { 4, 4, SMM_CPU_OFFSET (x86._TR), SMM_CPU_OFFSET (x64._TR), 0, FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_TR_SEL = 27
+ { 4, 8, SMM_CPU_OFFSET (x86._DR7), SMM_CPU_OFFSET (x64._DR7), SMM_CPU_OFFSET (x64._DR7) + 4, FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_DR7 = 28
+ { 4, 8, SMM_CPU_OFFSET (x86._DR6), SMM_CPU_OFFSET (x64._DR6), SMM_CPU_OFFSET (x64._DR6) + 4, FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_DR6 = 29
+ { 0, 8, 0, SMM_CPU_OFFSET (x64._R8), SMM_CPU_OFFSET (x64._R8) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R8 = 30
+ { 0, 8, 0, SMM_CPU_OFFSET (x64._R9), SMM_CPU_OFFSET (x64._R9) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R9 = 31
+ { 0, 8, 0, SMM_CPU_OFFSET (x64._R10), SMM_CPU_OFFSET (x64._R10) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R10 = 32
+ { 0, 8, 0, SMM_CPU_OFFSET (x64._R11), SMM_CPU_OFFSET (x64._R11) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R11 = 33
+ { 0, 8, 0, SMM_CPU_OFFSET (x64._R12), SMM_CPU_OFFSET (x64._R12) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R12 = 34
+ { 0, 8, 0, SMM_CPU_OFFSET (x64._R13), SMM_CPU_OFFSET (x64._R13) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R13 = 35
+ { 0, 8, 0, SMM_CPU_OFFSET (x64._R14), SMM_CPU_OFFSET (x64._R14) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R14 = 36
+ { 0, 8, 0, SMM_CPU_OFFSET (x64._R15), SMM_CPU_OFFSET (x64._R15) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R15 = 37
+ { 4, 8, SMM_CPU_OFFSET (x86._EAX), SMM_CPU_OFFSET (x64._RAX), SMM_CPU_OFFSET (x64._RAX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RAX = 38
+ { 4, 8, SMM_CPU_OFFSET (x86._EBX), SMM_CPU_OFFSET (x64._RBX), SMM_CPU_OFFSET (x64._RBX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RBX = 39
+ { 4, 8, SMM_CPU_OFFSET (x86._ECX), SMM_CPU_OFFSET (x64._RCX), SMM_CPU_OFFSET (x64._RCX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RCX = 40
+ { 4, 8, SMM_CPU_OFFSET (x86._EDX), SMM_CPU_OFFSET (x64._RDX), SMM_CPU_OFFSET (x64._RDX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RDX = 41
+ { 4, 8, SMM_CPU_OFFSET (x86._ESP), SMM_CPU_OFFSET (x64._RSP), SMM_CPU_OFFSET (x64._RSP) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RSP = 42
+ { 4, 8, SMM_CPU_OFFSET (x86._EBP), SMM_CPU_OFFSET (x64._RBP), SMM_CPU_OFFSET (x64._RBP) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RBP = 43
+ { 4, 8, SMM_CPU_OFFSET (x86._ESI), SMM_CPU_OFFSET (x64._RSI), SMM_CPU_OFFSET (x64._RSI) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RSI = 44
+ { 4, 8, SMM_CPU_OFFSET (x86._EDI), SMM_CPU_OFFSET (x64._RDI), SMM_CPU_OFFSET (x64._RDI) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RDI = 45
+ { 4, 8, SMM_CPU_OFFSET (x86._EIP), SMM_CPU_OFFSET (x64._RIP), SMM_CPU_OFFSET (x64._RIP) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RIP = 46
+
+ { 4, 8, SMM_CPU_OFFSET (x86._EFLAGS), SMM_CPU_OFFSET (x64._RFLAGS), SMM_CPU_OFFSET (x64._RFLAGS) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RFLAGS = 51
+ { 4, 8, SMM_CPU_OFFSET (x86._CR0), SMM_CPU_OFFSET (x64._CR0), SMM_CPU_OFFSET (x64._CR0) + 4, FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_CR0 = 52
+ { 4, 8, SMM_CPU_OFFSET (x86._CR3), SMM_CPU_OFFSET (x64._CR3), SMM_CPU_OFFSET (x64._CR3) + 4, FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_CR3 = 53
+ { 0, 4, 0, SMM_CPU_OFFSET (x64._CR4), 0, FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_CR4 = 54
};
///
/// Lookup table for the IOMisc width information
///
-CONST CPU_SMM_SAVE_STATE_IO_WIDTH mSmmCpuIoWidth[] = {
+CONST CPU_SMM_SAVE_STATE_IO_WIDTH mSmmCpuIoWidth[] = {
{ 0, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8 }, // Undefined = 0
{ 1, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8 }, // SMM_IO_LENGTH_BYTE = 1
{ 2, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT16 }, // SMM_IO_LENGTH_WORD = 2
@@ -195,7 +195,7 @@ CONST CPU_SMM_SAVE_STATE_IO_WIDTH mSmmCpuIoWidth[] = { ///
/// Lookup table for the IOMisc type information
///
-CONST EFI_SMM_SAVE_STATE_IO_TYPE mSmmCpuIoType[] = {
+CONST EFI_SMM_SAVE_STATE_IO_TYPE mSmmCpuIoType[] = {
EFI_SMM_SAVE_STATE_IO_TYPE_OUTPUT, // SMM_IO_TYPE_OUT_DX = 0
EFI_SMM_SAVE_STATE_IO_TYPE_INPUT, // SMM_IO_TYPE_IN_DX = 1
EFI_SMM_SAVE_STATE_IO_TYPE_STRING, // SMM_IO_TYPE_OUTS = 2
@@ -237,11 +237,13 @@ GetRegisterIndex ( UINTN Offset;
for (Index = 0, Offset = SMM_SAVE_STATE_REGISTER_MAX_INDEX; mSmmCpuRegisterRanges[Index].Length != 0; Index++) {
- if (Register >= mSmmCpuRegisterRanges[Index].Start && Register <= mSmmCpuRegisterRanges[Index].End) {
+ if ((Register >= mSmmCpuRegisterRanges[Index].Start) && (Register <= mSmmCpuRegisterRanges[Index].End)) {
return Register - mSmmCpuRegisterRanges[Index].Start + Offset;
}
+
Offset += mSmmCpuRegisterRanges[Index].Length;
}
+
return 0;
}
@@ -265,10 +267,10 @@ GetRegisterIndex ( **/
EFI_STATUS
ReadSaveStateRegisterByIndex (
- IN UINTN CpuIndex,
- IN UINTN RegisterIndex,
- IN UINTN Width,
- OUT VOID *Buffer
+ IN UINTN CpuIndex,
+ IN UINTN RegisterIndex,
+ IN UINTN Width,
+ OUT VOID *Buffer
)
{
SMRAM_SAVE_STATE_MAP *CpuSaveState;
@@ -297,8 +299,8 @@ ReadSaveStateRegisterByIndex ( //
// Write return buffer
//
- ASSERT(CpuSaveState != NULL);
- CopyMem(Buffer, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32, Width);
+ ASSERT (CpuSaveState != NULL);
+ CopyMem (Buffer, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32, Width);
} else {
//
// If 64-bit mode width is zero, then the specified register can not be accessed
@@ -317,14 +319,15 @@ ReadSaveStateRegisterByIndex ( //
// Write at most 4 of the lower bytes of the return buffer
//
- CopyMem(Buffer, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo, MIN(4, Width));
+ CopyMem (Buffer, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo, MIN (4, Width));
if (Width > 4) {
//
// Write at most 4 of the upper bytes of the return buffer
//
- CopyMem((UINT8 *)Buffer + 4, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi, Width - 4);
+ CopyMem ((UINT8 *)Buffer + 4, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi, Width - 4);
}
}
+
return EFI_SUCCESS;
}
@@ -382,7 +385,7 @@ ReadSaveStateRegister ( //
// Get SMM Revision ID
//
- ReadSaveStateRegisterByIndex (CpuIndex, SMM_SAVE_STATE_REGISTER_SMMREVID_INDEX, sizeof(SmmRevId), &SmmRevId);
+ ReadSaveStateRegisterByIndex (CpuIndex, SMM_SAVE_STATE_REGISTER_SMMREVID_INDEX, sizeof (SmmRevId), &SmmRevId);
//
// See if the CPU supports the IOMisc register in the save state
@@ -394,7 +397,7 @@ ReadSaveStateRegister ( //
// Get the IOMisc register value
//
- ReadSaveStateRegisterByIndex (CpuIndex, SMM_SAVE_STATE_REGISTER_IOMISC_INDEX, sizeof(IoMisc.Uint32), &IoMisc.Uint32);
+ ReadSaveStateRegisterByIndex (CpuIndex, SMM_SAVE_STATE_REGISTER_IOMISC_INDEX, sizeof (IoMisc.Uint32), &IoMisc.Uint32);
//
// Check for the SMI_FLAG in IOMisc
@@ -407,14 +410,15 @@ ReadSaveStateRegister ( // Only support IN/OUT, but not INS/OUTS/REP INS/REP OUTS.
//
if ((mSmmCpuIoType[IoMisc.Bits.Type] != EFI_SMM_SAVE_STATE_IO_TYPE_INPUT) &&
- (mSmmCpuIoType[IoMisc.Bits.Type] != EFI_SMM_SAVE_STATE_IO_TYPE_OUTPUT)) {
+ (mSmmCpuIoType[IoMisc.Bits.Type] != EFI_SMM_SAVE_STATE_IO_TYPE_OUTPUT))
+ {
return EFI_NOT_FOUND;
}
//
// Compute index for the I/O Length and I/O Type lookup tables
//
- if (mSmmCpuIoWidth[IoMisc.Bits.Length].Width == 0 || mSmmCpuIoType[IoMisc.Bits.Type] == 0) {
+ if ((mSmmCpuIoWidth[IoMisc.Bits.Length].Width == 0) || (mSmmCpuIoType[IoMisc.Bits.Type] == 0)) {
return EFI_NOT_FOUND;
}
@@ -429,14 +433,14 @@ ReadSaveStateRegister ( // Zero the IoInfo structure that will be returned in Buffer
//
IoInfo = (EFI_SMM_SAVE_STATE_IO_INFO *)Buffer;
- ZeroMem (IoInfo, sizeof(EFI_SMM_SAVE_STATE_IO_INFO));
+ ZeroMem (IoInfo, sizeof (EFI_SMM_SAVE_STATE_IO_INFO));
//
// Use lookup tables to help fill in all the fields of the IoInfo structure
//
- IoInfo->IoPort = (UINT16)IoMisc.Bits.Port;
+ IoInfo->IoPort = (UINT16)IoMisc.Bits.Port;
IoInfo->IoWidth = mSmmCpuIoWidth[IoMisc.Bits.Length].IoWidth;
- IoInfo->IoType = mSmmCpuIoType[IoMisc.Bits.Type];
+ IoInfo->IoType = mSmmCpuIoType[IoMisc.Bits.Type];
ReadSaveStateRegister (CpuIndex, EFI_SMM_SAVE_STATE_REGISTER_RAX, mSmmCpuIoWidth[IoMisc.Bits.Length].Width, &IoInfo->IoData);
return EFI_SUCCESS;
}
@@ -525,11 +529,12 @@ WriteSaveStateRegister ( if (Width > mSmmCpuWidthOffset[RegisterIndex].Width32) {
return EFI_INVALID_PARAMETER;
}
+
//
// Write SMM State register
//
ASSERT (CpuSaveState != NULL);
- CopyMem((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32, Buffer, Width);
+ CopyMem ((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32, Buffer, Width);
} else {
//
// If 64-bit mode width is zero, then the specified register can not be accessed
@@ -548,14 +553,15 @@ WriteSaveStateRegister ( //
// Write at most 4 of the lower bytes of SMM State register
//
- CopyMem((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo, Buffer, MIN (4, Width));
+ CopyMem ((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo, Buffer, MIN (4, Width));
if (Width > 4) {
//
// Write at most 4 of the upper bytes of SMM State register
//
- CopyMem((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi, (UINT8 *)Buffer + 4, Width - 4);
+ CopyMem ((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi, (UINT8 *)Buffer + 4, Width - 4);
}
}
+
return EFI_SUCCESS;
}
@@ -600,7 +606,7 @@ HookReturnFromSmm ( if (mSmmSaveStateRegisterLma == EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT) {
OriginalInstructionPointer = (UINT64)CpuState->x86._EIP;
- CpuState->x86._EIP = (UINT32)NewInstructionPointer;
+ CpuState->x86._EIP = (UINT32)NewInstructionPointer;
//
// Clear the auto HALT restart flag so the RSM instruction returns
// program control to the instruction following the HLT instruction.
@@ -615,6 +621,7 @@ HookReturnFromSmm ( } else {
CpuState->x64._RIP = (UINT32)NewInstructionPointer;
}
+
//
// Clear the auto HALT restart flag so the RSM instruction returns
// program control to the instruction following the HLT instruction.
@@ -623,6 +630,7 @@ HookReturnFromSmm ( CpuState->x64.AutoHALTRestart &= ~BIT0;
}
}
+
return OriginalInstructionPointer;
}
@@ -644,6 +652,7 @@ GetSmiHandlerSize ( if (Size != 0) {
return Size;
}
+
return gcSmiHandlerSize;
}
@@ -693,7 +702,7 @@ InstallSmiHandler ( //
Psd = (PROCESSOR_SMM_DESCRIPTOR *)(VOID *)((UINTN)SmBase + SMM_PSD_OFFSET);
CopyMem (Psd, &gcPsd, sizeof (gcPsd));
- Psd->SmmGdtPtr = (UINT64)GdtBase;
+ Psd->SmmGdtPtr = (UINT64)GdtBase;
Psd->SmmGdtSize = (UINT32)GdtSize;
if (SmmCpuFeaturesGetSmiHandlerSize () != 0) {
@@ -729,14 +738,14 @@ InstallSmiHandler ( //
// Set the value at the top of the CPU stack to the CPU Index
//
- *(UINTN*)(UINTN)CpuSmiStack = CpuIndex;
+ *(UINTN *)(UINTN)CpuSmiStack = CpuIndex;
//
// Copy template to CPU specific SMI handler location
//
CopyMem (
- (VOID*)((UINTN)SmBase + SMM_HANDLER_OFFSET),
- (VOID*)gcSmiHandlerTemplate,
+ (VOID *)((UINTN)SmBase + SMM_HANDLER_OFFSET),
+ (VOID *)gcSmiHandlerTemplate,
gcSmiHandlerSize
);
}
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SyncTimer.c b/UefiCpuPkg/PiSmmCpuDxeSmm/SyncTimer.c index 096ab323bb..0c070c5736 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SyncTimer.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SyncTimer.c @@ -8,11 +8,11 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include "PiSmmCpuDxeSmm.h"
-UINT64 mTimeoutTicker = 0;
+UINT64 mTimeoutTicker = 0;
//
// Number of counts in a roll-over cycle of the performance counter.
//
-UINT64 mCycle = 0;
+UINT64 mCycle = 0;
//
// Flag to indicate the performance counter is count-up or count-down.
//
@@ -33,15 +33,15 @@ InitializeSmmTimer ( TimerFrequency = GetPerformanceCounterProperties (&Start, &End);
mTimeoutTicker = DivU64x32 (
- MultU64x64(TimerFrequency, PcdGet64 (PcdCpuSmmApSyncTimeout)),
+ MultU64x64 (TimerFrequency, PcdGet64 (PcdCpuSmmApSyncTimeout)),
1000 * 1000
);
if (End < Start) {
mCountDown = TRUE;
- mCycle = Start - End;
+ mCycle = Start - End;
} else {
mCountDown = FALSE;
- mCycle = End - Start;
+ mCycle = End - Start;
}
}
@@ -58,7 +58,6 @@ StartSyncTimer ( return GetPerformanceCounter ();
}
-
/**
Check if the SMM AP Sync timer is timeout.
@@ -68,7 +67,7 @@ StartSyncTimer ( BOOLEAN
EFIAPI
IsSyncTimerTimeout (
- IN UINT64 Timer
+ IN UINT64 Timer
)
{
UINT64 CurrentTimer;
@@ -106,5 +105,5 @@ IsSyncTimerTimeout ( }
}
- return (BOOLEAN) (Delta >= mTimeoutTicker);
+ return (BOOLEAN)(Delta >= mTimeoutTicker);
}
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c index 211a78b1c4..538394f239 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c @@ -10,16 +10,16 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include "PiSmmCpuDxeSmm.h"
-#define PAGE_TABLE_PAGES 8
-#define ACC_MAX_BIT BIT3
+#define PAGE_TABLE_PAGES 8
+#define ACC_MAX_BIT BIT3
-extern UINTN mSmmShadowStackSize;
+extern UINTN mSmmShadowStackSize;
-LIST_ENTRY mPagePool = INITIALIZE_LIST_HEAD_VARIABLE (mPagePool);
-BOOLEAN m1GPageTableSupport = FALSE;
-BOOLEAN mCpuSmmRestrictedMemoryAccess;
-BOOLEAN m5LevelPagingNeeded;
-X86_ASSEMBLY_PATCH_LABEL gPatch5LevelPagingNeeded;
+LIST_ENTRY mPagePool = INITIALIZE_LIST_HEAD_VARIABLE (mPagePool);
+BOOLEAN m1GPageTableSupport = FALSE;
+BOOLEAN mCpuSmmRestrictedMemoryAccess;
+BOOLEAN m5LevelPagingNeeded;
+X86_ASSEMBLY_PATCH_LABEL gPatch5LevelPagingNeeded;
/**
Disable CET.
@@ -51,8 +51,8 @@ Is1GPageSupport ( VOID
)
{
- UINT32 RegEax;
- UINT32 RegEdx;
+ UINT32 RegEax;
+ UINT32 RegEdx;
AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
if (RegEax >= 0x80000001) {
@@ -61,6 +61,7 @@ Is1GPageSupport ( return TRUE;
}
}
+
return FALSE;
}
@@ -78,9 +79,9 @@ Is5LevelPagingNeeded ( VOID
)
{
- CPUID_VIR_PHY_ADDRESS_SIZE_EAX VirPhyAddressSize;
- CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX ExtFeatureEcx;
- UINT32 MaxExtendedFunctionId;
+ CPUID_VIR_PHY_ADDRESS_SIZE_EAX VirPhyAddressSize;
+ CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX ExtFeatureEcx;
+ UINT32 MaxExtendedFunctionId;
AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedFunctionId, NULL, NULL, NULL);
if (MaxExtendedFunctionId >= CPUID_VIR_PHY_ADDRESS_SIZE) {
@@ -88,14 +89,20 @@ Is5LevelPagingNeeded ( } else {
VirPhyAddressSize.Bits.PhysicalAddressBits = 36;
}
+
AsmCpuidEx (
CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,
CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO,
- NULL, NULL, &ExtFeatureEcx.Uint32, NULL
+ NULL,
+ NULL,
+ &ExtFeatureEcx.Uint32,
+ NULL
);
DEBUG ((
- DEBUG_INFO, "PhysicalAddressBits = %d, 5LPageTable = %d.\n",
- VirPhyAddressSize.Bits.PhysicalAddressBits, ExtFeatureEcx.Bits.FiveLevelPage
+ DEBUG_INFO,
+ "PhysicalAddressBits = %d, 5LPageTable = %d.\n",
+ VirPhyAddressSize.Bits.PhysicalAddressBits,
+ ExtFeatureEcx.Bits.FiveLevelPage
));
if (VirPhyAddressSize.Bits.PhysicalAddressBits > 4 * 9 + 12) {
@@ -114,18 +121,19 @@ Is5LevelPagingNeeded ( **/
VOID
GetPageTable (
- OUT UINTN *Base,
- OUT BOOLEAN *FiveLevels OPTIONAL
+ OUT UINTN *Base,
+ OUT BOOLEAN *FiveLevels OPTIONAL
)
{
- IA32_CR4 Cr4;
+ IA32_CR4 Cr4;
if (mInternalCr3 == 0) {
*Base = AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64;
if (FiveLevels != NULL) {
- Cr4.UintN = AsmReadCr4 ();
+ Cr4.UintN = AsmReadCr4 ();
*FiveLevels = (BOOLEAN)(Cr4.Bits.LA57 == 1);
}
+
return;
}
@@ -146,8 +154,8 @@ GetPageTable ( **/
VOID
SetSubEntriesNum (
- IN OUT UINT64 *Entry,
- IN UINT64 SubEntryNum
+ IN OUT UINT64 *Entry,
+ IN UINT64 SubEntryNum
)
{
//
@@ -167,7 +175,7 @@ SetSubEntriesNum ( **/
UINT64
GetSubEntriesNum (
- IN UINT64 *Entry
+ IN UINT64 *Entry
)
{
//
@@ -186,25 +194,26 @@ CalculateMaximumSupportAddress ( VOID
)
{
- UINT32 RegEax;
- UINT8 PhysicalAddressBits;
- VOID *Hob;
+ UINT32 RegEax;
+ UINT8 PhysicalAddressBits;
+ VOID *Hob;
//
// Get physical address bits supported.
//
Hob = GetFirstHob (EFI_HOB_TYPE_CPU);
if (Hob != NULL) {
- PhysicalAddressBits = ((EFI_HOB_CPU *) Hob)->SizeOfMemorySpace;
+ PhysicalAddressBits = ((EFI_HOB_CPU *)Hob)->SizeOfMemorySpace;
} else {
AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
if (RegEax >= 0x80000008) {
AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);
- PhysicalAddressBits = (UINT8) RegEax;
+ PhysicalAddressBits = (UINT8)RegEax;
} else {
PhysicalAddressBits = 36;
}
}
+
return PhysicalAddressBits;
}
@@ -216,54 +225,54 @@ CalculateMaximumSupportAddress ( **/
VOID
SetStaticPageTable (
- IN UINTN PageTable,
- IN UINT8 PhysicalAddressBits
+ IN UINTN PageTable,
+ IN UINT8 PhysicalAddressBits
)
{
- UINT64 PageAddress;
- UINTN NumberOfPml5EntriesNeeded;
- UINTN NumberOfPml4EntriesNeeded;
- UINTN NumberOfPdpEntriesNeeded;
- UINTN IndexOfPml5Entries;
- UINTN IndexOfPml4Entries;
- UINTN IndexOfPdpEntries;
- UINTN IndexOfPageDirectoryEntries;
- UINT64 *PageMapLevel5Entry;
- UINT64 *PageMapLevel4Entry;
- UINT64 *PageMap;
- UINT64 *PageDirectoryPointerEntry;
- UINT64 *PageDirectory1GEntry;
- UINT64 *PageDirectoryEntry;
+ UINT64 PageAddress;
+ UINTN NumberOfPml5EntriesNeeded;
+ UINTN NumberOfPml4EntriesNeeded;
+ UINTN NumberOfPdpEntriesNeeded;
+ UINTN IndexOfPml5Entries;
+ UINTN IndexOfPml4Entries;
+ UINTN IndexOfPdpEntries;
+ UINTN IndexOfPageDirectoryEntries;
+ UINT64 *PageMapLevel5Entry;
+ UINT64 *PageMapLevel4Entry;
+ UINT64 *PageMap;
+ UINT64 *PageDirectoryPointerEntry;
+ UINT64 *PageDirectory1GEntry;
+ UINT64 *PageDirectoryEntry;
//
// IA-32e paging translates 48-bit linear addresses to 52-bit physical addresses
// when 5-Level Paging is disabled.
//
ASSERT (PhysicalAddressBits <= 52);
- if (!m5LevelPagingNeeded && PhysicalAddressBits > 48) {
+ if (!m5LevelPagingNeeded && (PhysicalAddressBits > 48)) {
PhysicalAddressBits = 48;
}
NumberOfPml5EntriesNeeded = 1;
if (PhysicalAddressBits > 48) {
- NumberOfPml5EntriesNeeded = (UINTN) LShiftU64 (1, PhysicalAddressBits - 48);
- PhysicalAddressBits = 48;
+ NumberOfPml5EntriesNeeded = (UINTN)LShiftU64 (1, PhysicalAddressBits - 48);
+ PhysicalAddressBits = 48;
}
NumberOfPml4EntriesNeeded = 1;
if (PhysicalAddressBits > 39) {
- NumberOfPml4EntriesNeeded = (UINTN) LShiftU64 (1, PhysicalAddressBits - 39);
- PhysicalAddressBits = 39;
+ NumberOfPml4EntriesNeeded = (UINTN)LShiftU64 (1, PhysicalAddressBits - 39);
+ PhysicalAddressBits = 39;
}
NumberOfPdpEntriesNeeded = 1;
ASSERT (PhysicalAddressBits > 30);
- NumberOfPdpEntriesNeeded = (UINTN) LShiftU64 (1, PhysicalAddressBits - 30);
+ NumberOfPdpEntriesNeeded = (UINTN)LShiftU64 (1, PhysicalAddressBits - 30);
//
// By architecture only one PageMapLevel4 exists - so lets allocate storage for it.
//
- PageMap = (VOID *) PageTable;
+ PageMap = (VOID *)PageTable;
PageMapLevel4Entry = PageMap;
PageMapLevel5Entry = NULL;
@@ -273,22 +282,24 @@ SetStaticPageTable ( //
PageMapLevel5Entry = PageMap;
}
- PageAddress = 0;
+
+ PageAddress = 0;
for ( IndexOfPml5Entries = 0
- ; IndexOfPml5Entries < NumberOfPml5EntriesNeeded
- ; IndexOfPml5Entries++, PageMapLevel5Entry++) {
+ ; IndexOfPml5Entries < NumberOfPml5EntriesNeeded
+ ; IndexOfPml5Entries++, PageMapLevel5Entry++)
+ {
//
// Each PML5 entry points to a page of PML4 entires.
// So lets allocate space for them and fill them in in the IndexOfPml4Entries loop.
// When 5-Level Paging is disabled, below allocation happens only once.
//
if (m5LevelPagingNeeded) {
- PageMapLevel4Entry = (UINT64 *) ((*PageMapLevel5Entry) & ~mAddressEncMask & gPhyMask);
+ PageMapLevel4Entry = (UINT64 *)((*PageMapLevel5Entry) & ~mAddressEncMask & gPhyMask);
if (PageMapLevel4Entry == NULL) {
PageMapLevel4Entry = AllocatePageTableMemory (1);
- ASSERT(PageMapLevel4Entry != NULL);
- ZeroMem (PageMapLevel4Entry, EFI_PAGES_TO_SIZE(1));
+ ASSERT (PageMapLevel4Entry != NULL);
+ ZeroMem (PageMapLevel4Entry, EFI_PAGES_TO_SIZE (1));
*PageMapLevel5Entry = (UINT64)(UINTN)PageMapLevel4Entry | mAddressEncMask | PAGE_ATTRIBUTE_BITS;
}
@@ -298,11 +309,11 @@ SetStaticPageTable ( //
// Each PML4 entry points to a page of Page Directory Pointer entries.
//
- PageDirectoryPointerEntry = (UINT64 *) ((*PageMapLevel4Entry) & ~mAddressEncMask & gPhyMask);
+ PageDirectoryPointerEntry = (UINT64 *)((*PageMapLevel4Entry) & ~mAddressEncMask & gPhyMask);
if (PageDirectoryPointerEntry == NULL) {
PageDirectoryPointerEntry = AllocatePageTableMemory (1);
- ASSERT(PageDirectoryPointerEntry != NULL);
- ZeroMem (PageDirectoryPointerEntry, EFI_PAGES_TO_SIZE(1));
+ ASSERT (PageDirectoryPointerEntry != NULL);
+ ZeroMem (PageDirectoryPointerEntry, EFI_PAGES_TO_SIZE (1));
*PageMapLevel4Entry = (UINT64)(UINTN)PageDirectoryPointerEntry | mAddressEncMask | PAGE_ATTRIBUTE_BITS;
}
@@ -310,12 +321,13 @@ SetStaticPageTable ( if (m1GPageTableSupport) {
PageDirectory1GEntry = PageDirectoryPointerEntry;
for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectory1GEntry++, PageAddress += SIZE_1GB) {
- if (IndexOfPml4Entries == 0 && IndexOfPageDirectoryEntries < 4) {
+ if ((IndexOfPml4Entries == 0) && (IndexOfPageDirectoryEntries < 4)) {
//
// Skip the < 4G entries
//
continue;
}
+
//
// Fill in the Page Directory entries
//
@@ -324,21 +336,22 @@ SetStaticPageTable ( } else {
PageAddress = BASE_4GB;
for (IndexOfPdpEntries = 0; IndexOfPdpEntries < (NumberOfPml4EntriesNeeded == 1 ? NumberOfPdpEntriesNeeded : 512); IndexOfPdpEntries++, PageDirectoryPointerEntry++) {
- if (IndexOfPml4Entries == 0 && IndexOfPdpEntries < 4) {
+ if ((IndexOfPml4Entries == 0) && (IndexOfPdpEntries < 4)) {
//
// Skip the < 4G entries
//
continue;
}
+
//
// Each Directory Pointer entries points to a page of Page Directory entires.
// So allocate space for them and fill them in in the IndexOfPageDirectoryEntries loop.
//
- PageDirectoryEntry = (UINT64 *) ((*PageDirectoryPointerEntry) & ~mAddressEncMask & gPhyMask);
+ PageDirectoryEntry = (UINT64 *)((*PageDirectoryPointerEntry) & ~mAddressEncMask & gPhyMask);
if (PageDirectoryEntry == NULL) {
PageDirectoryEntry = AllocatePageTableMemory (1);
- ASSERT(PageDirectoryEntry != NULL);
- ZeroMem (PageDirectoryEntry, EFI_PAGES_TO_SIZE(1));
+ ASSERT (PageDirectoryEntry != NULL);
+ ZeroMem (PageDirectoryEntry, EFI_PAGES_TO_SIZE (1));
//
// Fill in a Page Directory Pointer Entries
@@ -369,15 +382,15 @@ SmmInitPageTable ( VOID
)
{
- EFI_PHYSICAL_ADDRESS Pages;
- UINT64 *PTEntry;
- LIST_ENTRY *FreePage;
- UINTN Index;
- UINTN PageFaultHandlerHookAddress;
- IA32_IDT_GATE_DESCRIPTOR *IdtEntry;
- EFI_STATUS Status;
- UINT64 *Pml4Entry;
- UINT64 *Pml5Entry;
+ EFI_PHYSICAL_ADDRESS Pages;
+ UINT64 *PTEntry;
+ LIST_ENTRY *FreePage;
+ UINTN Index;
+ UINTN PageFaultHandlerHookAddress;
+ IA32_IDT_GATE_DESCRIPTOR *IdtEntry;
+ EFI_STATUS Status;
+ UINT64 *Pml4Entry;
+ UINT64 *Pml5Entry;
//
// Initialize spin lock
@@ -401,7 +414,7 @@ SmmInitPageTable ( //
// Set IA32_PG_PMNT bit to mask this entry
//
- PTEntry = (UINT64*)(UINTN)Pages;
+ PTEntry = (UINT64 *)(UINTN)Pages;
for (Index = 0; Index < 4; Index++) {
PTEntry[Index] |= IA32_PG_PMNT;
}
@@ -409,7 +422,7 @@ SmmInitPageTable ( //
// Fill Page-Table-Level4 (PML4) entry
//
- Pml4Entry = (UINT64*)AllocatePageTableMemory (1);
+ Pml4Entry = (UINT64 *)AllocatePageTableMemory (1);
ASSERT (Pml4Entry != NULL);
*Pml4Entry = Pages | mAddressEncMask | PAGE_ATTRIBUTE_BITS;
ZeroMem (Pml4Entry + 1, EFI_PAGE_SIZE - sizeof (*Pml4Entry));
@@ -424,9 +437,9 @@ SmmInitPageTable ( //
// Fill PML5 entry
//
- Pml5Entry = (UINT64*)AllocatePageTableMemory (1);
+ Pml5Entry = (UINT64 *)AllocatePageTableMemory (1);
ASSERT (Pml5Entry != NULL);
- *Pml5Entry = (UINTN) Pml4Entry | mAddressEncMask | PAGE_ATTRIBUTE_BITS;
+ *Pml5Entry = (UINTN)Pml4Entry | mAddressEncMask | PAGE_ATTRIBUTE_BITS;
ZeroMem (Pml5Entry + 1, EFI_PAGE_SIZE - sizeof (*Pml5Entry));
//
// Set sub-entries number
@@ -445,7 +458,7 @@ SmmInitPageTable ( //
// Add pages to page pool
//
- FreePage = (LIST_ENTRY*)AllocatePageTableMemory (PAGE_TABLE_PAGES);
+ FreePage = (LIST_ENTRY *)AllocatePageTableMemory (PAGE_TABLE_PAGES);
ASSERT (FreePage != NULL);
for (Index = 0; Index < PAGE_TABLE_PAGES; Index++) {
InsertTailList (&mPagePool, FreePage);
@@ -455,20 +468,21 @@ SmmInitPageTable ( if (FeaturePcdGet (PcdCpuSmmProfileEnable) ||
HEAP_GUARD_NONSTOP_MODE ||
- NULL_DETECTION_NONSTOP_MODE) {
+ NULL_DETECTION_NONSTOP_MODE)
+ {
//
// Set own Page Fault entry instead of the default one, because SMM Profile
// feature depends on IRET instruction to do Single Step
//
PageFaultHandlerHookAddress = (UINTN)PageFaultIdtHandlerSmmProfile;
- IdtEntry = (IA32_IDT_GATE_DESCRIPTOR *) gcSmiIdtr.Base;
- IdtEntry += EXCEPT_IA32_PAGE_FAULT;
- IdtEntry->Bits.OffsetLow = (UINT16)PageFaultHandlerHookAddress;
- IdtEntry->Bits.Reserved_0 = 0;
- IdtEntry->Bits.GateType = IA32_IDT_GATE_TYPE_INTERRUPT_32;
- IdtEntry->Bits.OffsetHigh = (UINT16)(PageFaultHandlerHookAddress >> 16);
- IdtEntry->Bits.OffsetUpper = (UINT32)(PageFaultHandlerHookAddress >> 32);
- IdtEntry->Bits.Reserved_1 = 0;
+ IdtEntry = (IA32_IDT_GATE_DESCRIPTOR *)gcSmiIdtr.Base;
+ IdtEntry += EXCEPT_IA32_PAGE_FAULT;
+ IdtEntry->Bits.OffsetLow = (UINT16)PageFaultHandlerHookAddress;
+ IdtEntry->Bits.Reserved_0 = 0;
+ IdtEntry->Bits.GateType = IA32_IDT_GATE_TYPE_INTERRUPT_32;
+ IdtEntry->Bits.OffsetHigh = (UINT16)(PageFaultHandlerHookAddress >> 16);
+ IdtEntry->Bits.OffsetUpper = (UINT32)(PageFaultHandlerHookAddress >> 32);
+ IdtEntry->Bits.Reserved_1 = 0;
} else {
//
// Register Smm Page Fault Handler
@@ -509,8 +523,8 @@ SmmInitPageTable ( **/
VOID
SetAccNum (
- IN OUT UINT64 *Entry,
- IN UINT64 Acc
+ IN OUT UINT64 *Entry,
+ IN UINT64 Acc
)
{
//
@@ -529,7 +543,7 @@ SetAccNum ( **/
UINT64
GetAccNum (
- IN UINT64 *Entry
+ IN UINT64 *Entry
)
{
//
@@ -548,10 +562,10 @@ GetAccNum ( **/
UINT64
GetAndUpdateAccNum (
- IN OUT UINT64 *Entry
+ IN OUT UINT64 *Entry
)
{
- UINT64 Acc;
+ UINT64 Acc;
Acc = GetAccNum (Entry);
if ((*Entry & IA32_PG_A) != 0) {
@@ -570,6 +584,7 @@ GetAndUpdateAccNum ( SetAccNum (Entry, Acc - 1);
}
}
+
return Acc;
}
@@ -587,84 +602,86 @@ ReclaimPages ( VOID
)
{
- UINT64 Pml5Entry;
- UINT64 *Pml5;
- UINT64 *Pml4;
- UINT64 *Pdpt;
- UINT64 *Pdt;
- UINTN Pml5Index;
- UINTN Pml4Index;
- UINTN PdptIndex;
- UINTN PdtIndex;
- UINTN MinPml5;
- UINTN MinPml4;
- UINTN MinPdpt;
- UINTN MinPdt;
- UINT64 MinAcc;
- UINT64 Acc;
- UINT64 SubEntriesNum;
- BOOLEAN PML4EIgnore;
- BOOLEAN PDPTEIgnore;
- UINT64 *ReleasePageAddress;
- IA32_CR4 Cr4;
- BOOLEAN Enable5LevelPaging;
- UINT64 PFAddress;
- UINT64 PFAddressPml5Index;
- UINT64 PFAddressPml4Index;
- UINT64 PFAddressPdptIndex;
- UINT64 PFAddressPdtIndex;
-
- Pml4 = NULL;
- Pdpt = NULL;
- Pdt = NULL;
- MinAcc = (UINT64)-1;
- MinPml4 = (UINTN)-1;
- MinPml5 = (UINTN)-1;
- MinPdpt = (UINTN)-1;
- MinPdt = (UINTN)-1;
- Acc = 0;
+ UINT64 Pml5Entry;
+ UINT64 *Pml5;
+ UINT64 *Pml4;
+ UINT64 *Pdpt;
+ UINT64 *Pdt;
+ UINTN Pml5Index;
+ UINTN Pml4Index;
+ UINTN PdptIndex;
+ UINTN PdtIndex;
+ UINTN MinPml5;
+ UINTN MinPml4;
+ UINTN MinPdpt;
+ UINTN MinPdt;
+ UINT64 MinAcc;
+ UINT64 Acc;
+ UINT64 SubEntriesNum;
+ BOOLEAN PML4EIgnore;
+ BOOLEAN PDPTEIgnore;
+ UINT64 *ReleasePageAddress;
+ IA32_CR4 Cr4;
+ BOOLEAN Enable5LevelPaging;
+ UINT64 PFAddress;
+ UINT64 PFAddressPml5Index;
+ UINT64 PFAddressPml4Index;
+ UINT64 PFAddressPdptIndex;
+ UINT64 PFAddressPdtIndex;
+
+ Pml4 = NULL;
+ Pdpt = NULL;
+ Pdt = NULL;
+ MinAcc = (UINT64)-1;
+ MinPml4 = (UINTN)-1;
+ MinPml5 = (UINTN)-1;
+ MinPdpt = (UINTN)-1;
+ MinPdt = (UINTN)-1;
+ Acc = 0;
ReleasePageAddress = 0;
- PFAddress = AsmReadCr2 ();
+ PFAddress = AsmReadCr2 ();
PFAddressPml5Index = BitFieldRead64 (PFAddress, 48, 48 + 8);
PFAddressPml4Index = BitFieldRead64 (PFAddress, 39, 39 + 8);
PFAddressPdptIndex = BitFieldRead64 (PFAddress, 30, 30 + 8);
- PFAddressPdtIndex = BitFieldRead64 (PFAddress, 21, 21 + 8);
+ PFAddressPdtIndex = BitFieldRead64 (PFAddress, 21, 21 + 8);
- Cr4.UintN = AsmReadCr4 ();
- Enable5LevelPaging = (BOOLEAN) (Cr4.Bits.LA57 == 1);
- Pml5 = (UINT64*)(UINTN)(AsmReadCr3 () & gPhyMask);
+ Cr4.UintN = AsmReadCr4 ();
+ Enable5LevelPaging = (BOOLEAN)(Cr4.Bits.LA57 == 1);
+ Pml5 = (UINT64 *)(UINTN)(AsmReadCr3 () & gPhyMask);
if (!Enable5LevelPaging) {
//
// Create one fake PML5 entry for 4-Level Paging
// so that the page table parsing logic only handles 5-Level page structure.
//
- Pml5Entry = (UINTN) Pml5 | IA32_PG_P;
- Pml5 = &Pml5Entry;
+ Pml5Entry = (UINTN)Pml5 | IA32_PG_P;
+ Pml5 = &Pml5Entry;
}
//
// First, find the leaf entry has the smallest access record value
//
for (Pml5Index = 0; Pml5Index < (Enable5LevelPaging ? (EFI_PAGE_SIZE / sizeof (*Pml4)) : 1); Pml5Index++) {
- if ((Pml5[Pml5Index] & IA32_PG_P) == 0 || (Pml5[Pml5Index] & IA32_PG_PMNT) != 0) {
+ if (((Pml5[Pml5Index] & IA32_PG_P) == 0) || ((Pml5[Pml5Index] & IA32_PG_PMNT) != 0)) {
//
// If the PML5 entry is not present or is masked, skip it
//
continue;
}
- Pml4 = (UINT64*)(UINTN)(Pml5[Pml5Index] & gPhyMask);
+
+ Pml4 = (UINT64 *)(UINTN)(Pml5[Pml5Index] & gPhyMask);
for (Pml4Index = 0; Pml4Index < EFI_PAGE_SIZE / sizeof (*Pml4); Pml4Index++) {
- if ((Pml4[Pml4Index] & IA32_PG_P) == 0 || (Pml4[Pml4Index] & IA32_PG_PMNT) != 0) {
+ if (((Pml4[Pml4Index] & IA32_PG_P) == 0) || ((Pml4[Pml4Index] & IA32_PG_PMNT) != 0)) {
//
// If the PML4 entry is not present or is masked, skip it
//
continue;
}
- Pdpt = (UINT64*)(UINTN)(Pml4[Pml4Index] & ~mAddressEncMask & gPhyMask);
+
+ Pdpt = (UINT64 *)(UINTN)(Pml4[Pml4Index] & ~mAddressEncMask & gPhyMask);
PML4EIgnore = FALSE;
for (PdptIndex = 0; PdptIndex < EFI_PAGE_SIZE / sizeof (*Pdpt); PdptIndex++) {
- if ((Pdpt[PdptIndex] & IA32_PG_P) == 0 || (Pdpt[PdptIndex] & IA32_PG_PMNT) != 0) {
+ if (((Pdpt[PdptIndex] & IA32_PG_P) == 0) || ((Pdpt[PdptIndex] & IA32_PG_PMNT) != 0)) {
//
// If the PDPT entry is not present or is masked, skip it
//
@@ -674,18 +691,20 @@ ReclaimPages ( //
PML4EIgnore = TRUE;
}
+
continue;
}
+
if ((Pdpt[PdptIndex] & IA32_PG_PS) == 0) {
//
// It's not 1-GByte pages entry, it should be a PDPT entry,
// we will not check PML4 entry more
//
PML4EIgnore = TRUE;
- Pdt = (UINT64*)(UINTN)(Pdpt[PdptIndex] & ~mAddressEncMask & gPhyMask);
+ Pdt = (UINT64 *)(UINTN)(Pdpt[PdptIndex] & ~mAddressEncMask & gPhyMask);
PDPTEIgnore = FALSE;
- for (PdtIndex = 0; PdtIndex < EFI_PAGE_SIZE / sizeof(*Pdt); PdtIndex++) {
- if ((Pdt[PdtIndex] & IA32_PG_P) == 0 || (Pdt[PdtIndex] & IA32_PG_PMNT) != 0) {
+ for (PdtIndex = 0; PdtIndex < EFI_PAGE_SIZE / sizeof (*Pdt); PdtIndex++) {
+ if (((Pdt[PdtIndex] & IA32_PG_P) == 0) || ((Pdt[PdtIndex] & IA32_PG_PMNT) != 0)) {
//
// If the PD entry is not present or is masked, skip it
//
@@ -695,79 +714,86 @@ ReclaimPages ( //
PDPTEIgnore = TRUE;
}
+
continue;
}
+
if ((Pdt[PdtIndex] & IA32_PG_PS) == 0) {
//
// It's not 2 MByte page table entry, it should be PD entry
// we will find the entry has the smallest access record value
//
PDPTEIgnore = TRUE;
- if (PdtIndex != PFAddressPdtIndex || PdptIndex != PFAddressPdptIndex ||
- Pml4Index != PFAddressPml4Index || Pml5Index != PFAddressPml5Index) {
+ if ((PdtIndex != PFAddressPdtIndex) || (PdptIndex != PFAddressPdptIndex) ||
+ (Pml4Index != PFAddressPml4Index) || (Pml5Index != PFAddressPml5Index))
+ {
Acc = GetAndUpdateAccNum (Pdt + PdtIndex);
if (Acc < MinAcc) {
//
// If the PD entry has the smallest access record value,
// save the Page address to be released
//
- MinAcc = Acc;
- MinPml5 = Pml5Index;
- MinPml4 = Pml4Index;
- MinPdpt = PdptIndex;
- MinPdt = PdtIndex;
+ MinAcc = Acc;
+ MinPml5 = Pml5Index;
+ MinPml4 = Pml4Index;
+ MinPdpt = PdptIndex;
+ MinPdt = PdtIndex;
ReleasePageAddress = Pdt + PdtIndex;
}
}
}
}
+
if (!PDPTEIgnore) {
//
// If this PDPT entry has no PDT entries pointer to 4 KByte pages,
// it should only has the entries point to 2 MByte Pages
//
- if (PdptIndex != PFAddressPdptIndex || Pml4Index != PFAddressPml4Index ||
- Pml5Index != PFAddressPml5Index) {
+ if ((PdptIndex != PFAddressPdptIndex) || (Pml4Index != PFAddressPml4Index) ||
+ (Pml5Index != PFAddressPml5Index))
+ {
Acc = GetAndUpdateAccNum (Pdpt + PdptIndex);
if (Acc < MinAcc) {
//
// If the PDPT entry has the smallest access record value,
// save the Page address to be released
//
- MinAcc = Acc;
- MinPml5 = Pml5Index;
- MinPml4 = Pml4Index;
- MinPdpt = PdptIndex;
- MinPdt = (UINTN)-1;
+ MinAcc = Acc;
+ MinPml5 = Pml5Index;
+ MinPml4 = Pml4Index;
+ MinPdpt = PdptIndex;
+ MinPdt = (UINTN)-1;
ReleasePageAddress = Pdpt + PdptIndex;
}
}
}
}
}
+
if (!PML4EIgnore) {
//
// If PML4 entry has no the PDPT entry pointer to 2 MByte pages,
// it should only has the entries point to 1 GByte Pages
//
- if (Pml4Index != PFAddressPml4Index || Pml5Index != PFAddressPml5Index) {
+ if ((Pml4Index != PFAddressPml4Index) || (Pml5Index != PFAddressPml5Index)) {
Acc = GetAndUpdateAccNum (Pml4 + Pml4Index);
if (Acc < MinAcc) {
//
// If the PML4 entry has the smallest access record value,
// save the Page address to be released
//
- MinAcc = Acc;
- MinPml5 = Pml5Index;
- MinPml4 = Pml4Index;
- MinPdpt = (UINTN)-1;
- MinPdt = (UINTN)-1;
+ MinAcc = Acc;
+ MinPml5 = Pml5Index;
+ MinPml4 = Pml4Index;
+ MinPdpt = (UINTN)-1;
+ MinPdt = (UINTN)-1;
ReleasePageAddress = Pml4 + Pml4Index;
}
}
}
}
}
+
//
// Make sure one PML4/PDPT/PD entry is selected
//
@@ -776,7 +802,7 @@ ReclaimPages ( //
// Secondly, insert the page pointed by this entry into page pool and clear this entry
//
- InsertTailList (&mPagePool, (LIST_ENTRY*)(UINTN)(*ReleasePageAddress & ~mAddressEncMask & gPhyMask));
+ InsertTailList (&mPagePool, (LIST_ENTRY *)(UINTN)(*ReleasePageAddress & ~mAddressEncMask & gPhyMask));
*ReleasePageAddress = 0;
//
@@ -788,16 +814,17 @@ ReclaimPages ( //
// If 4 KByte Page Table is released, check the PDPT entry
//
- Pml4 = (UINT64 *) (UINTN) (Pml5[MinPml5] & gPhyMask);
- Pdpt = (UINT64*)(UINTN)(Pml4[MinPml4] & ~mAddressEncMask & gPhyMask);
- SubEntriesNum = GetSubEntriesNum(Pdpt + MinPdpt);
- if (SubEntriesNum == 0 &&
- (MinPdpt != PFAddressPdptIndex || MinPml4 != PFAddressPml4Index || MinPml5 != PFAddressPml5Index)) {
+ Pml4 = (UINT64 *)(UINTN)(Pml5[MinPml5] & gPhyMask);
+ Pdpt = (UINT64 *)(UINTN)(Pml4[MinPml4] & ~mAddressEncMask & gPhyMask);
+ SubEntriesNum = GetSubEntriesNum (Pdpt + MinPdpt);
+ if ((SubEntriesNum == 0) &&
+ ((MinPdpt != PFAddressPdptIndex) || (MinPml4 != PFAddressPml4Index) || (MinPml5 != PFAddressPml5Index)))
+ {
//
// Release the empty Page Directory table if there was no more 4 KByte Page Table entry
// clear the Page directory entry
//
- InsertTailList (&mPagePool, (LIST_ENTRY*)(UINTN)(Pdpt[MinPdpt] & ~mAddressEncMask & gPhyMask));
+ InsertTailList (&mPagePool, (LIST_ENTRY *)(UINTN)(Pdpt[MinPdpt] & ~mAddressEncMask & gPhyMask));
Pdpt[MinPdpt] = 0;
//
// Go on checking the PML4 table
@@ -805,33 +832,37 @@ ReclaimPages ( MinPdt = (UINTN)-1;
continue;
}
+
//
// Update the sub-entries filed in PDPT entry and exit
//
SetSubEntriesNum (Pdpt + MinPdpt, (SubEntriesNum - 1) & 0x1FF);
break;
}
+
if (MinPdpt != (UINTN)-1) {
//
// One 2MB Page Table is released or Page Directory table is released, check the PML4 entry
//
SubEntriesNum = GetSubEntriesNum (Pml4 + MinPml4);
- if (SubEntriesNum == 0 && (MinPml4 != PFAddressPml4Index || MinPml5 != PFAddressPml5Index)) {
+ if ((SubEntriesNum == 0) && ((MinPml4 != PFAddressPml4Index) || (MinPml5 != PFAddressPml5Index))) {
//
// Release the empty PML4 table if there was no more 1G KByte Page Table entry
// clear the Page directory entry
//
- InsertTailList (&mPagePool, (LIST_ENTRY*)(UINTN)(Pml4[MinPml4] & ~mAddressEncMask & gPhyMask));
+ InsertTailList (&mPagePool, (LIST_ENTRY *)(UINTN)(Pml4[MinPml4] & ~mAddressEncMask & gPhyMask));
Pml4[MinPml4] = 0;
- MinPdpt = (UINTN)-1;
+ MinPdpt = (UINTN)-1;
continue;
}
+
//
// Update the sub-entries filed in PML4 entry and exit
//
SetSubEntriesNum (Pml4 + MinPml4, (SubEntriesNum - 1) & 0x1FF);
break;
}
+
//
// PLM4 table has been released before, exit it
//
@@ -850,7 +881,7 @@ AllocPage ( VOID
)
{
- UINT64 RetVal;
+ UINT64 RetVal;
if (IsListEmpty (&mPagePool)) {
//
@@ -867,7 +898,7 @@ AllocPage ( //
// Clean this page and return
//
- ZeroMem ((VOID*)(UINTN)RetVal, EFI_PAGE_SIZE);
+ ZeroMem ((VOID *)(UINTN)RetVal, EFI_PAGE_SIZE);
return RetVal;
}
@@ -880,78 +911,81 @@ SmiDefaultPFHandler ( VOID
)
{
- UINT64 *PageTable;
- UINT64 *PageTableTop;
- UINT64 PFAddress;
- UINTN StartBit;
- UINTN EndBit;
- UINT64 PTIndex;
- UINTN Index;
- SMM_PAGE_SIZE_TYPE PageSize;
- UINTN NumOfPages;
- UINTN PageAttribute;
- EFI_STATUS Status;
- UINT64 *UpperEntry;
- BOOLEAN Enable5LevelPaging;
- IA32_CR4 Cr4;
+ UINT64 *PageTable;
+ UINT64 *PageTableTop;
+ UINT64 PFAddress;
+ UINTN StartBit;
+ UINTN EndBit;
+ UINT64 PTIndex;
+ UINTN Index;
+ SMM_PAGE_SIZE_TYPE PageSize;
+ UINTN NumOfPages;
+ UINTN PageAttribute;
+ EFI_STATUS Status;
+ UINT64 *UpperEntry;
+ BOOLEAN Enable5LevelPaging;
+ IA32_CR4 Cr4;
//
// Set default SMM page attribute
//
- PageSize = SmmPageSize2M;
- NumOfPages = 1;
+ PageSize = SmmPageSize2M;
+ NumOfPages = 1;
PageAttribute = 0;
- EndBit = 0;
- PageTableTop = (UINT64*)(AsmReadCr3 () & gPhyMask);
- PFAddress = AsmReadCr2 ();
+ EndBit = 0;
+ PageTableTop = (UINT64 *)(AsmReadCr3 () & gPhyMask);
+ PFAddress = AsmReadCr2 ();
- Cr4.UintN = AsmReadCr4 ();
- Enable5LevelPaging = (BOOLEAN) (Cr4.Bits.LA57 != 0);
+ Cr4.UintN = AsmReadCr4 ();
+ Enable5LevelPaging = (BOOLEAN)(Cr4.Bits.LA57 != 0);
Status = GetPlatformPageTableAttribute (PFAddress, &PageSize, &NumOfPages, &PageAttribute);
//
// If platform not support page table attribute, set default SMM page attribute
//
if (Status != EFI_SUCCESS) {
- PageSize = SmmPageSize2M;
- NumOfPages = 1;
+ PageSize = SmmPageSize2M;
+ NumOfPages = 1;
PageAttribute = 0;
}
+
if (PageSize >= MaxSmmPageSizeType) {
PageSize = SmmPageSize2M;
}
+
if (NumOfPages > 512) {
NumOfPages = 512;
}
switch (PageSize) {
- case SmmPageSize4K:
- //
- // BIT12 to BIT20 is Page Table index
- //
- EndBit = 12;
- break;
- case SmmPageSize2M:
- //
- // BIT21 to BIT29 is Page Directory index
- //
- EndBit = 21;
- PageAttribute |= (UINTN)IA32_PG_PS;
- break;
- case SmmPageSize1G:
- if (!m1GPageTableSupport) {
- DEBUG ((DEBUG_ERROR, "1-GByte pages is not supported!"));
+ case SmmPageSize4K:
+ //
+ // BIT12 to BIT20 is Page Table index
+ //
+ EndBit = 12;
+ break;
+ case SmmPageSize2M:
+ //
+ // BIT21 to BIT29 is Page Directory index
+ //
+ EndBit = 21;
+ PageAttribute |= (UINTN)IA32_PG_PS;
+ break;
+ case SmmPageSize1G:
+ if (!m1GPageTableSupport) {
+ DEBUG ((DEBUG_ERROR, "1-GByte pages is not supported!"));
+ ASSERT (FALSE);
+ }
+
+ //
+ // BIT30 to BIT38 is Page Directory Pointer Table index
+ //
+ EndBit = 30;
+ PageAttribute |= (UINTN)IA32_PG_PS;
+ break;
+ default:
ASSERT (FALSE);
- }
- //
- // BIT30 to BIT38 is Page Directory Pointer Table index
- //
- EndBit = 30;
- PageAttribute |= (UINTN)IA32_PG_PS;
- break;
- default:
- ASSERT (FALSE);
}
//
@@ -977,13 +1011,14 @@ SmiDefaultPFHandler ( //
UpperEntry = PageTable + PTIndex;
}
+
//
// BIT9 to BIT11 of entry is used to save access record,
// initialize value is 7
//
PageTable[PTIndex] |= (UINT64)IA32_PG_A;
SetAccNum (PageTable + PTIndex, 7);
- PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & gPhyMask);
+ PageTable = (UINT64 *)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & gPhyMask);
}
PTIndex = BitFieldRead64 (PFAddress, StartBit, StartBit + 8);
@@ -996,6 +1031,7 @@ SmiDefaultPFHandler ( DEBUG ((DEBUG_ERROR, "New page table overlapped with old page table!\n"));
ASSERT (FALSE);
}
+
//
// Fill the new entry
//
@@ -1004,6 +1040,7 @@ SmiDefaultPFHandler ( if (UpperEntry != NULL) {
SetSubEntriesNum (UpperEntry, (GetSubEntriesNum (UpperEntry) + 1) & 0x1FF);
}
+
//
// Get the next page address if we need to create more page tables
//
@@ -1022,14 +1059,14 @@ SmiDefaultPFHandler ( VOID
EFIAPI
SmiPFHandler (
- IN EFI_EXCEPTION_TYPE InterruptType,
- IN EFI_SYSTEM_CONTEXT SystemContext
+ IN EFI_EXCEPTION_TYPE InterruptType,
+ IN EFI_SYSTEM_CONTEXT SystemContext
)
{
- UINTN PFAddress;
- UINTN GuardPageAddress;
- UINTN ShadowStackGuardPageAddress;
- UINTN CpuIndex;
+ UINTN PFAddress;
+ UINTN GuardPageAddress;
+ UINTN ShadowStackGuardPageAddress;
+ UINTN CpuIndex;
ASSERT (InterruptType == EXCEPT_IA32_PAGE_FAULT);
@@ -1049,31 +1086,34 @@ SmiPFHandler ( // or SMM page protection violation.
//
if ((PFAddress >= mCpuHotPlugData.SmrrBase) &&
- (PFAddress < (mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize))) {
+ (PFAddress < (mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize)))
+ {
DumpCpuContext (InterruptType, SystemContext);
- CpuIndex = GetCpuIndex ();
- GuardPageAddress = (mSmmStackArrayBase + EFI_PAGE_SIZE + CpuIndex * (mSmmStackSize + mSmmShadowStackSize));
+ CpuIndex = GetCpuIndex ();
+ GuardPageAddress = (mSmmStackArrayBase + EFI_PAGE_SIZE + CpuIndex * (mSmmStackSize + mSmmShadowStackSize));
ShadowStackGuardPageAddress = (mSmmStackArrayBase + mSmmStackSize + EFI_PAGE_SIZE + CpuIndex * (mSmmStackSize + mSmmShadowStackSize));
if ((FeaturePcdGet (PcdCpuSmmStackGuard)) &&
(PFAddress >= GuardPageAddress) &&
- (PFAddress < (GuardPageAddress + EFI_PAGE_SIZE))) {
+ (PFAddress < (GuardPageAddress + EFI_PAGE_SIZE)))
+ {
DEBUG ((DEBUG_ERROR, "SMM stack overflow!\n"));
} else if ((FeaturePcdGet (PcdCpuSmmStackGuard)) &&
- (mSmmShadowStackSize > 0) &&
- (PFAddress >= ShadowStackGuardPageAddress) &&
- (PFAddress < (ShadowStackGuardPageAddress + EFI_PAGE_SIZE))) {
+ (mSmmShadowStackSize > 0) &&
+ (PFAddress >= ShadowStackGuardPageAddress) &&
+ (PFAddress < (ShadowStackGuardPageAddress + EFI_PAGE_SIZE)))
+ {
DEBUG ((DEBUG_ERROR, "SMM shadow stack overflow!\n"));
} else {
if ((SystemContext.SystemContextX64->ExceptionData & IA32_PF_EC_ID) != 0) {
DEBUG ((DEBUG_ERROR, "SMM exception at execution (0x%lx)\n", PFAddress));
DEBUG_CODE (
DumpModuleInfoByIp (*(UINTN *)(UINTN)SystemContext.SystemContextX64->Rsp);
- );
+ );
} else {
DEBUG ((DEBUG_ERROR, "SMM exception at access (0x%lx)\n", PFAddress));
DEBUG_CODE (
DumpModuleInfoByIp ((UINTN)SystemContext.SystemContextX64->Rip);
- );
+ );
}
if (HEAP_GUARD_NONSTOP_MODE) {
@@ -1081,6 +1121,7 @@ SmiPFHandler ( goto Exit;
}
}
+
CpuDeadLoop ();
goto Exit;
}
@@ -1089,13 +1130,14 @@ SmiPFHandler ( // If a page fault occurs in non-SMRAM range.
//
if ((PFAddress < mCpuHotPlugData.SmrrBase) ||
- (PFAddress >= mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize)) {
+ (PFAddress >= mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize))
+ {
if ((SystemContext.SystemContextX64->ExceptionData & IA32_PF_EC_ID) != 0) {
DumpCpuContext (InterruptType, SystemContext);
DEBUG ((DEBUG_ERROR, "Code executed on IP(0x%lx) out of SMM range after SMM is locked!\n", PFAddress));
DEBUG_CODE (
DumpModuleInfoByIp (*(UINTN *)(UINTN)SystemContext.SystemContextX64->Rsp);
- );
+ );
CpuDeadLoop ();
goto Exit;
}
@@ -1103,13 +1145,14 @@ SmiPFHandler ( //
// If NULL pointer was just accessed
//
- if ((PcdGet8 (PcdNullPointerDetectionPropertyMask) & BIT1) != 0 &&
- (PFAddress < EFI_PAGE_SIZE)) {
+ if (((PcdGet8 (PcdNullPointerDetectionPropertyMask) & BIT1) != 0) &&
+ (PFAddress < EFI_PAGE_SIZE))
+ {
DumpCpuContext (InterruptType, SystemContext);
DEBUG ((DEBUG_ERROR, "!!! NULL pointer access !!!\n"));
DEBUG_CODE (
DumpModuleInfoByIp ((UINTN)SystemContext.SystemContextX64->Rip);
- );
+ );
if (NULL_DETECTION_NONSTOP_MODE) {
GuardPagePFHandler (SystemContext.SystemContextX64->ExceptionData);
@@ -1125,7 +1168,7 @@ SmiPFHandler ( DEBUG ((DEBUG_ERROR, "Access SMM communication forbidden address (0x%lx)!\n", PFAddress));
DEBUG_CODE (
DumpModuleInfoByIp ((UINTN)SystemContext.SystemContextX64->Rip);
- );
+ );
CpuDeadLoop ();
goto Exit;
}
@@ -1152,20 +1195,20 @@ SetPageTableAttributes ( VOID
)
{
- UINTN Index2;
- UINTN Index3;
- UINTN Index4;
- UINTN Index5;
- UINT64 *L1PageTable;
- UINT64 *L2PageTable;
- UINT64 *L3PageTable;
- UINT64 *L4PageTable;
- UINT64 *L5PageTable;
- UINTN PageTableBase;
- BOOLEAN IsSplitted;
- BOOLEAN PageTableSplitted;
- BOOLEAN CetEnabled;
- BOOLEAN Enable5LevelPaging;
+ UINTN Index2;
+ UINTN Index3;
+ UINTN Index4;
+ UINTN Index5;
+ UINT64 *L1PageTable;
+ UINT64 *L2PageTable;
+ UINT64 *L3PageTable;
+ UINT64 *L4PageTable;
+ UINT64 *L5PageTable;
+ UINTN PageTableBase;
+ BOOLEAN IsSplitted;
+ BOOLEAN PageTableSplitted;
+ BOOLEAN CetEnabled;
+ BOOLEAN Enable5LevelPaging;
//
// Don't mark page table memory as read-only if
@@ -1177,18 +1220,21 @@ SetPageTableAttributes ( //
if (!mCpuSmmRestrictedMemoryAccess ||
((PcdGet8 (PcdHeapGuardPropertyMask) & (BIT3 | BIT2)) != 0) ||
- FeaturePcdGet (PcdCpuSmmProfileEnable)) {
+ FeaturePcdGet (PcdCpuSmmProfileEnable))
+ {
//
// Restriction on access to non-SMRAM memory and heap guard could not be enabled at the same time.
//
- ASSERT (!(mCpuSmmRestrictedMemoryAccess &&
- (PcdGet8 (PcdHeapGuardPropertyMask) & (BIT3 | BIT2)) != 0));
+ ASSERT (
+ !(mCpuSmmRestrictedMemoryAccess &&
+ (PcdGet8 (PcdHeapGuardPropertyMask) & (BIT3 | BIT2)) != 0)
+ );
//
// Restriction on access to non-SMRAM memory and SMM profile could not be enabled at the same time.
//
ASSERT (!(mCpuSmmRestrictedMemoryAccess && FeaturePcdGet (PcdCpuSmmProfileEnable)));
- return ;
+ return;
}
DEBUG ((DEBUG_INFO, "SetPageTableAttributes\n"));
@@ -1197,19 +1243,20 @@ SetPageTableAttributes ( // Disable write protection, because we need mark page table to be write protected.
// We need *write* page table memory, to mark itself to be *read only*.
//
- CetEnabled = ((AsmReadCr4() & CR4_CET_ENABLE) != 0) ? TRUE : FALSE;
+ CetEnabled = ((AsmReadCr4 () & CR4_CET_ENABLE) != 0) ? TRUE : FALSE;
if (CetEnabled) {
//
// CET must be disabled if WP is disabled.
//
- DisableCet();
+ DisableCet ();
}
- AsmWriteCr0 (AsmReadCr0() & ~CR0_WP);
+
+ AsmWriteCr0 (AsmReadCr0 () & ~CR0_WP);
do {
DEBUG ((DEBUG_INFO, "Start...\n"));
PageTableSplitted = FALSE;
- L5PageTable = NULL;
+ L5PageTable = NULL;
GetPageTable (&PageTableBase, &Enable5LevelPaging);
@@ -1219,7 +1266,7 @@ SetPageTableAttributes ( PageTableSplitted = (PageTableSplitted || IsSplitted);
}
- for (Index5 = 0; Index5 < (Enable5LevelPaging ? SIZE_4KB/sizeof(UINT64) : 1); Index5++) {
+ for (Index5 = 0; Index5 < (Enable5LevelPaging ? SIZE_4KB/sizeof (UINT64) : 1); Index5++) {
if (Enable5LevelPaging) {
L4PageTable = (UINT64 *)(UINTN)(L5PageTable[Index5] & ~mAddressEncMask & PAGING_4K_ADDRESS_MASK_64);
if (L4PageTable == NULL) {
@@ -1228,10 +1275,11 @@ SetPageTableAttributes ( } else {
L4PageTable = (UINT64 *)PageTableBase;
}
+
SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)(UINTN)L4PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted);
PageTableSplitted = (PageTableSplitted || IsSplitted);
- for (Index4 = 0; Index4 < SIZE_4KB/sizeof(UINT64); Index4++) {
+ for (Index4 = 0; Index4 < SIZE_4KB/sizeof (UINT64); Index4++) {
L3PageTable = (UINT64 *)(UINTN)(L4PageTable[Index4] & ~mAddressEncMask & PAGING_4K_ADDRESS_MASK_64);
if (L3PageTable == NULL) {
continue;
@@ -1240,11 +1288,12 @@ SetPageTableAttributes ( SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)(UINTN)L3PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted);
PageTableSplitted = (PageTableSplitted || IsSplitted);
- for (Index3 = 0; Index3 < SIZE_4KB/sizeof(UINT64); Index3++) {
+ for (Index3 = 0; Index3 < SIZE_4KB/sizeof (UINT64); Index3++) {
if ((L3PageTable[Index3] & IA32_PG_PS) != 0) {
// 1G
continue;
}
+
L2PageTable = (UINT64 *)(UINTN)(L3PageTable[Index3] & ~mAddressEncMask & PAGING_4K_ADDRESS_MASK_64);
if (L2PageTable == NULL) {
continue;
@@ -1253,15 +1302,17 @@ SetPageTableAttributes ( SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)(UINTN)L2PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted);
PageTableSplitted = (PageTableSplitted || IsSplitted);
- for (Index2 = 0; Index2 < SIZE_4KB/sizeof(UINT64); Index2++) {
+ for (Index2 = 0; Index2 < SIZE_4KB/sizeof (UINT64); Index2++) {
if ((L2PageTable[Index2] & IA32_PG_PS) != 0) {
// 2M
continue;
}
+
L1PageTable = (UINT64 *)(UINTN)(L2PageTable[Index2] & ~mAddressEncMask & PAGING_4K_ADDRESS_MASK_64);
if (L1PageTable == NULL) {
continue;
}
+
SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)(UINTN)L1PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted);
PageTableSplitted = (PageTableSplitted || IsSplitted);
}
@@ -1273,15 +1324,15 @@ SetPageTableAttributes ( //
// Enable write protection, after page table updated.
//
- AsmWriteCr0 (AsmReadCr0() | CR0_WP);
+ AsmWriteCr0 (AsmReadCr0 () | CR0_WP);
if (CetEnabled) {
//
// re-enable CET.
//
- EnableCet();
+ EnableCet ();
}
- return ;
+ return;
}
/**
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Semaphore.c b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Semaphore.c index 8c9de1fdae..dafbc3390e 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Semaphore.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Semaphore.c @@ -9,8 +9,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include "PiSmmCpuDxeSmm.h"
-X86_ASSEMBLY_PATCH_LABEL gPatchSmmRelocationOriginalAddressPtr32;
-X86_ASSEMBLY_PATCH_LABEL gPatchRebasedFlagAddr32;
+X86_ASSEMBLY_PATCH_LABEL gPatchSmmRelocationOriginalAddressPtr32;
+X86_ASSEMBLY_PATCH_LABEL gPatchRebasedFlagAddr32;
UINTN mSmmRelocationOriginalAddress;
volatile BOOLEAN *mRebasedFlag;
@@ -42,14 +42,14 @@ SemaphoreHook ( SMRAM_SAVE_STATE_MAP *CpuState;
UINTN TempValue;
- mRebasedFlag = RebasedFlag;
+ mRebasedFlag = RebasedFlag;
PatchInstructionX86 (
gPatchRebasedFlagAddr32,
(UINT32)(UINTN)mRebasedFlag,
4
);
- CpuState = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET);
+ CpuState = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET);
mSmmRelocationOriginalAddress = HookReturnFromSmm (
CpuIndex,
CpuState,
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c index ce7afce6d4..00a284c369 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c @@ -8,18 +8,18 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include "PiSmmCpuDxeSmm.h"
-EFI_PHYSICAL_ADDRESS mGdtBuffer;
-UINTN mGdtBufferSize;
+EFI_PHYSICAL_ADDRESS mGdtBuffer;
+UINTN mGdtBufferSize;
-extern BOOLEAN mCetSupported;
-extern UINTN mSmmShadowStackSize;
+extern BOOLEAN mCetSupported;
+extern UINTN mSmmShadowStackSize;
-X86_ASSEMBLY_PATCH_LABEL mPatchCetPl0Ssp;
-X86_ASSEMBLY_PATCH_LABEL mPatchCetInterruptSsp;
-X86_ASSEMBLY_PATCH_LABEL mPatchCetInterruptSspTable;
-UINT32 mCetPl0Ssp;
-UINT32 mCetInterruptSsp;
-UINT32 mCetInterruptSspTable;
+X86_ASSEMBLY_PATCH_LABEL mPatchCetPl0Ssp;
+X86_ASSEMBLY_PATCH_LABEL mPatchCetInterruptSsp;
+X86_ASSEMBLY_PATCH_LABEL mPatchCetInterruptSspTable;
+UINT32 mCetPl0Ssp;
+UINT32 mCetInterruptSsp;
+UINT32 mCetInterruptSspTable;
UINTN mSmmInterruptSspTables;
@@ -33,14 +33,14 @@ UINTN mSmmInterruptSspTables; VOID
EFIAPI
InitializeIdtIst (
- IN EFI_EXCEPTION_TYPE ExceptionType,
- IN UINT8 Ist
+ IN EFI_EXCEPTION_TYPE ExceptionType,
+ IN UINT8 Ist
)
{
IA32_IDT_GATE_DESCRIPTOR *IdtGate;
- IdtGate = (IA32_IDT_GATE_DESCRIPTOR *)gcSmiIdtr.Base;
- IdtGate += ExceptionType;
+ IdtGate = (IA32_IDT_GATE_DESCRIPTOR *)gcSmiIdtr.Base;
+ IdtGate += ExceptionType;
IdtGate->Bits.Reserved_0 = Ist;
}
@@ -59,34 +59,34 @@ InitGdt ( OUT UINTN *GdtStepSize
)
{
- UINTN Index;
- IA32_SEGMENT_DESCRIPTOR *GdtDescriptor;
- UINTN TssBase;
- UINTN GdtTssTableSize;
- UINT8 *GdtTssTables;
- UINTN GdtTableStepSize;
+ UINTN Index;
+ IA32_SEGMENT_DESCRIPTOR *GdtDescriptor;
+ UINTN TssBase;
+ UINTN GdtTssTableSize;
+ UINT8 *GdtTssTables;
+ UINTN GdtTableStepSize;
//
// For X64 SMM, we allocate separate GDT/TSS for each CPUs to avoid TSS load contention
// on each SMI entry.
//
GdtTssTableSize = (gcSmiGdtr.Limit + 1 + TSS_SIZE + 7) & ~7; // 8 bytes aligned
- mGdtBufferSize = GdtTssTableSize * gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus;
- GdtTssTables = (UINT8*)AllocateCodePages (EFI_SIZE_TO_PAGES (mGdtBufferSize));
+ mGdtBufferSize = GdtTssTableSize * gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus;
+ GdtTssTables = (UINT8 *)AllocateCodePages (EFI_SIZE_TO_PAGES (mGdtBufferSize));
ASSERT (GdtTssTables != NULL);
- mGdtBuffer = (UINTN)GdtTssTables;
+ mGdtBuffer = (UINTN)GdtTssTables;
GdtTableStepSize = GdtTssTableSize;
for (Index = 0; Index < gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus; Index++) {
- CopyMem (GdtTssTables + GdtTableStepSize * Index, (VOID*)(UINTN)gcSmiGdtr.Base, gcSmiGdtr.Limit + 1 + TSS_SIZE);
+ CopyMem (GdtTssTables + GdtTableStepSize * Index, (VOID *)(UINTN)gcSmiGdtr.Base, gcSmiGdtr.Limit + 1 + TSS_SIZE);
//
// Fixup TSS descriptors
//
- TssBase = (UINTN)(GdtTssTables + GdtTableStepSize * Index + gcSmiGdtr.Limit + 1);
- GdtDescriptor = (IA32_SEGMENT_DESCRIPTOR *)(TssBase) - 2;
- GdtDescriptor->Bits.BaseLow = (UINT16)(UINTN)TssBase;
- GdtDescriptor->Bits.BaseMid = (UINT8)((UINTN)TssBase >> 16);
+ TssBase = (UINTN)(GdtTssTables + GdtTableStepSize * Index + gcSmiGdtr.Limit + 1);
+ GdtDescriptor = (IA32_SEGMENT_DESCRIPTOR *)(TssBase) - 2;
+ GdtDescriptor->Bits.BaseLow = (UINT16)(UINTN)TssBase;
+ GdtDescriptor->Bits.BaseMid = (UINT8)((UINTN)TssBase >> 16);
GdtDescriptor->Bits.BaseHigh = (UINT8)((UINTN)TssBase >> 24);
if ((FeaturePcdGet (PcdCpuSmmStackGuard)) || ((PcdGet32 (PcdControlFlowEnforcementPropertyMask) != 0) && mCetSupported)) {
@@ -118,15 +118,17 @@ GetProtectedModeCS ( AsmReadGdtr (&GdtrDesc);
GdtEntryCount = (GdtrDesc.Limit + 1) / sizeof (IA32_SEGMENT_DESCRIPTOR);
- GdtEntry = (IA32_SEGMENT_DESCRIPTOR *) GdtrDesc.Base;
+ GdtEntry = (IA32_SEGMENT_DESCRIPTOR *)GdtrDesc.Base;
for (Index = 0; Index < GdtEntryCount; Index++) {
if (GdtEntry->Bits.L == 0) {
- if (GdtEntry->Bits.Type > 8 && GdtEntry->Bits.DB == 1) {
+ if ((GdtEntry->Bits.Type > 8) && (GdtEntry->Bits.DB == 1)) {
break;
}
}
+
GdtEntry++;
}
+
ASSERT (Index != GdtEntryCount);
return Index * 8;
}
@@ -171,9 +173,9 @@ InitShadowStack ( IN VOID *ShadowStack
)
{
- UINTN SmmShadowStackSize;
- UINT64 *InterruptSspTable;
- UINT32 InterruptSsp;
+ UINTN SmmShadowStackSize;
+ UINT64 *InterruptSspTable;
+ UINT32 InterruptSsp;
if ((PcdGet32 (PcdControlFlowEnforcementPropertyMask) != 0) && mCetSupported) {
SmmShadowStackSize = EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuSmmShadowStackSize)));
@@ -188,14 +190,15 @@ InitShadowStack ( //
SmmShadowStackSize += EFI_PAGES_TO_SIZE (1);
}
- mCetPl0Ssp = (UINT32)((UINTN)ShadowStack + SmmShadowStackSize - sizeof(UINT64));
+
+ mCetPl0Ssp = (UINT32)((UINTN)ShadowStack + SmmShadowStackSize - sizeof (UINT64));
PatchInstructionX86 (mPatchCetPl0Ssp, mCetPl0Ssp, 4);
DEBUG ((DEBUG_INFO, "mCetPl0Ssp - 0x%x\n", mCetPl0Ssp));
DEBUG ((DEBUG_INFO, "ShadowStack - 0x%x\n", ShadowStack));
DEBUG ((DEBUG_INFO, " SmmShadowStackSize - 0x%x\n", SmmShadowStackSize));
if (mSmmInterruptSspTables == 0) {
- mSmmInterruptSspTables = (UINTN)AllocateZeroPool(sizeof(UINT64) * 8 * gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus);
+ mSmmInterruptSspTables = (UINTN)AllocateZeroPool (sizeof (UINT64) * 8 * gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus);
ASSERT (mSmmInterruptSspTables != 0);
DEBUG ((DEBUG_INFO, "mSmmInterruptSspTables - 0x%x\n", mSmmInterruptSspTables));
}
@@ -209,17 +212,16 @@ InitShadowStack ( // Please refer to UefiCpuPkg/Library/CpuExceptionHandlerLib/X64 for the full stack frame at runtime.
// According to SDM (ver. 075 June 2021), shadow stack should be 32 bytes aligned.
//
- InterruptSsp = (UINT32)(((UINTN)ShadowStack + EFI_PAGES_TO_SIZE(1) - (sizeof(UINT64) * 4)) & ~0x1f);
- *(UINT64 *)(UINTN)InterruptSsp = (InterruptSsp - sizeof(UINT64) * 4) | 0x2;
- mCetInterruptSsp = InterruptSsp - sizeof(UINT64);
+ InterruptSsp = (UINT32)(((UINTN)ShadowStack + EFI_PAGES_TO_SIZE (1) - (sizeof (UINT64) * 4)) & ~0x1f);
+ *(UINT64 *)(UINTN)InterruptSsp = (InterruptSsp - sizeof (UINT64) * 4) | 0x2;
+ mCetInterruptSsp = InterruptSsp - sizeof (UINT64);
- mCetInterruptSspTable = (UINT32)(UINTN)(mSmmInterruptSspTables + sizeof(UINT64) * 8 * CpuIndex);
- InterruptSspTable = (UINT64 *)(UINTN)mCetInterruptSspTable;
- InterruptSspTable[1] = mCetInterruptSsp;
+ mCetInterruptSspTable = (UINT32)(UINTN)(mSmmInterruptSspTables + sizeof (UINT64) * 8 * CpuIndex);
+ InterruptSspTable = (UINT64 *)(UINTN)mCetInterruptSspTable;
+ InterruptSspTable[1] = mCetInterruptSsp;
PatchInstructionX86 (mPatchCetInterruptSsp, mCetInterruptSsp, 4);
PatchInstructionX86 (mPatchCetInterruptSspTable, mCetInterruptSspTable, 4);
DEBUG ((DEBUG_INFO, "mCetInterruptSsp - 0x%x\n", mCetInterruptSsp));
DEBUG ((DEBUG_INFO, "mCetInterruptSspTable - 0x%x\n", mCetInterruptSspTable));
}
}
-
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.c b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.c index 63bae5a913..cb7a691745 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.c @@ -14,17 +14,17 @@ SPDX-License-Identifier: BSD-2-Clause-Patent //
// Current page index.
//
-UINTN mPFPageIndex;
+UINTN mPFPageIndex;
//
// Pool for dynamically creating page table in page fault handler.
//
-UINT64 mPFPageBuffer;
+UINT64 mPFPageBuffer;
//
// Store the uplink information for each page being used.
//
-UINT64 *mPFPageUplink[MAX_PF_PAGE_COUNT];
+UINT64 *mPFPageUplink[MAX_PF_PAGE_COUNT];
/**
Create SMM page table for S3 path.
@@ -35,8 +35,8 @@ InitSmmS3Cr3 ( VOID
)
{
- EFI_PHYSICAL_ADDRESS Pages;
- UINT64 *PTEntry;
+ EFI_PHYSICAL_ADDRESS Pages;
+ UINT64 *PTEntry;
//
// Generate PAE page table for the first 4GB memory space
@@ -46,7 +46,7 @@ InitSmmS3Cr3 ( //
// Fill Page-Table-Level4 (PML4) entry
//
- PTEntry = (UINT64*)AllocatePageTableMemory (1);
+ PTEntry = (UINT64 *)AllocatePageTableMemory (1);
ASSERT (PTEntry != NULL);
*PTEntry = Pages | mAddressEncMask | PAGE_ATTRIBUTE_BITS;
ZeroMem (PTEntry + 1, EFI_PAGE_SIZE - sizeof (*PTEntry));
@@ -56,7 +56,7 @@ InitSmmS3Cr3 ( //
mSmmS3ResumeState->SmmS3Cr3 = (UINT32)(UINTN)PTEntry;
- return ;
+ return;
}
/**
@@ -68,7 +68,7 @@ InitPagesForPFHandler ( VOID
)
{
- VOID *Address;
+ VOID *Address;
//
// Pre-Allocate memory for page fault handler
@@ -77,9 +77,9 @@ InitPagesForPFHandler ( Address = AllocatePages (MAX_PF_PAGE_COUNT);
ASSERT (Address != NULL);
- mPFPageBuffer = (UINT64)(UINTN) Address;
- mPFPageIndex = 0;
- ZeroMem ((VOID *) (UINTN) mPFPageBuffer, EFI_PAGE_SIZE * MAX_PF_PAGE_COUNT);
+ mPFPageBuffer = (UINT64)(UINTN)Address;
+ mPFPageIndex = 0;
+ ZeroMem ((VOID *)(UINTN)mPFPageBuffer, EFI_PAGE_SIZE * MAX_PF_PAGE_COUNT);
ZeroMem (mPFPageUplink, sizeof (mPFPageUplink));
return;
@@ -93,16 +93,16 @@ InitPagesForPFHandler ( **/
VOID
AcquirePage (
- UINT64 *Uplink
+ UINT64 *Uplink
)
{
- UINT64 Address;
+ UINT64 Address;
//
// Get the buffer
//
Address = mPFPageBuffer + EFI_PAGES_TO_SIZE (mPFPageIndex);
- ZeroMem ((VOID *) (UINTN) Address, EFI_PAGE_SIZE);
+ ZeroMem ((VOID *)(UINTN)Address, EFI_PAGE_SIZE);
//
// Cut the previous uplink if it exists and wasn't overwritten
@@ -114,7 +114,7 @@ AcquirePage ( //
// Link & Record the current uplink
//
- *Uplink = Address | mAddressEncMask | PAGE_ATTRIBUTE_BITS;
+ *Uplink = Address | mAddressEncMask | PAGE_ATTRIBUTE_BITS;
mPFPageUplink[mPFPageIndex] = Uplink;
mPFPageIndex = (mPFPageIndex + 1) % MAX_PF_PAGE_COUNT;
@@ -134,26 +134,26 @@ AcquirePage ( **/
VOID
RestorePageTableAbove4G (
- UINT64 *PageTable,
- UINT64 PFAddress,
- UINTN CpuIndex,
- UINTN ErrorCode,
- BOOLEAN *IsValidPFAddress
+ UINT64 *PageTable,
+ UINT64 PFAddress,
+ UINTN CpuIndex,
+ UINTN ErrorCode,
+ BOOLEAN *IsValidPFAddress
)
{
- UINTN PTIndex;
- UINT64 Address;
- BOOLEAN Nx;
- BOOLEAN Existed;
- UINTN Index;
- UINTN PFIndex;
- IA32_CR4 Cr4;
- BOOLEAN Enable5LevelPaging;
+ UINTN PTIndex;
+ UINT64 Address;
+ BOOLEAN Nx;
+ BOOLEAN Existed;
+ UINTN Index;
+ UINTN PFIndex;
+ IA32_CR4 Cr4;
+ BOOLEAN Enable5LevelPaging;
ASSERT ((PageTable != NULL) && (IsValidPFAddress != NULL));
- Cr4.UintN = AsmReadCr4 ();
- Enable5LevelPaging = (BOOLEAN) (Cr4.Bits.LA57 == 1);
+ Cr4.UintN = AsmReadCr4 ();
+ Enable5LevelPaging = (BOOLEAN)(Cr4.Bits.LA57 == 1);
//
// If page fault address is 4GB above.
@@ -164,26 +164,28 @@ RestorePageTableAbove4G ( // If it exists in page table but page fault is generated,
// there are 2 possible reasons: 1. present flag is set to 0; 2. instruction fetch in protected memory range.
//
- Existed = FALSE;
- PageTable = (UINT64*)(AsmReadCr3 () & PHYSICAL_ADDRESS_MASK);
- PTIndex = 0;
+ Existed = FALSE;
+ PageTable = (UINT64 *)(AsmReadCr3 () & PHYSICAL_ADDRESS_MASK);
+ PTIndex = 0;
if (Enable5LevelPaging) {
PTIndex = BitFieldRead64 (PFAddress, 48, 56);
}
+
if ((!Enable5LevelPaging) || ((PageTable[PTIndex] & IA32_PG_P) != 0)) {
// PML5E
if (Enable5LevelPaging) {
- PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);
+ PageTable = (UINT64 *)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);
}
+
PTIndex = BitFieldRead64 (PFAddress, 39, 47);
if ((PageTable[PTIndex] & IA32_PG_P) != 0) {
// PML4E
- PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);
- PTIndex = BitFieldRead64 (PFAddress, 30, 38);
+ PageTable = (UINT64 *)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);
+ PTIndex = BitFieldRead64 (PFAddress, 30, 38);
if ((PageTable[PTIndex] & IA32_PG_P) != 0) {
// PDPTE
- PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);
- PTIndex = BitFieldRead64 (PFAddress, 21, 29);
+ PageTable = (UINT64 *)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);
+ PTIndex = BitFieldRead64 (PFAddress, 21, 29);
// PD
if ((PageTable[PTIndex] & IA32_PG_PS) != 0) {
//
@@ -197,7 +199,7 @@ RestorePageTableAbove4G ( //
// 4KB page
//
- PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask& PHYSICAL_ADDRESS_MASK);
+ PageTable = (UINT64 *)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask& PHYSICAL_ADDRESS_MASK);
if (PageTable != 0) {
//
// When there is a valid entry to map to 4KB page, need not create a new entry to map 2MB.
@@ -217,7 +219,6 @@ RestorePageTableAbove4G ( // If page entry does not existed in page table at all, create a new entry.
//
if (!Existed) {
-
if (IsAddressValid (PFAddress, &Nx)) {
//
// If page fault address above 4GB is in protected range but it causes a page fault exception,
@@ -234,19 +235,20 @@ RestorePageTableAbove4G ( //
// Find the page table entry created just now.
//
- PageTable = (UINT64*)(AsmReadCr3 () & PHYSICAL_ADDRESS_MASK);
+ PageTable = (UINT64 *)(AsmReadCr3 () & PHYSICAL_ADDRESS_MASK);
PFAddress = AsmReadCr2 ();
// PML5E
if (Enable5LevelPaging) {
- PTIndex = BitFieldRead64 (PFAddress, 48, 56);
- PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);
+ PTIndex = BitFieldRead64 (PFAddress, 48, 56);
+ PageTable = (UINT64 *)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);
}
+
// PML4E
- PTIndex = BitFieldRead64 (PFAddress, 39, 47);
- PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);
+ PTIndex = BitFieldRead64 (PFAddress, 39, 47);
+ PageTable = (UINT64 *)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);
// PDPTE
- PTIndex = BitFieldRead64 (PFAddress, 30, 38);
- PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);
+ PTIndex = BitFieldRead64 (PFAddress, 30, 38);
+ PageTable = (UINT64 *)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);
// PD
PTIndex = BitFieldRead64 (PFAddress, 21, 29);
Address = PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK;
@@ -257,18 +259,21 @@ RestorePageTableAbove4G ( AcquirePage (&PageTable[PTIndex]);
// PTE
- PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);
+ PageTable = (UINT64 *)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);
for (Index = 0; Index < 512; Index++) {
PageTable[Index] = Address | mAddressEncMask | PAGE_ATTRIBUTE_BITS;
if (!IsAddressValid (Address, &Nx)) {
PageTable[Index] = PageTable[Index] & (INTN)(INT32)(~PAGE_ATTRIBUTE_BITS);
}
+
if (Nx && mXdSupported) {
PageTable[Index] = PageTable[Index] | IA32_PG_NX;
}
+
if (Address == (PFAddress & PHYSICAL_ADDRESS_MASK & ~((1ull << 12) - 1))) {
PTIndex = Index;
}
+
Address += SIZE_4KB;
} // end for PT
} else {
@@ -281,6 +286,7 @@ RestorePageTableAbove4G ( //
PageTable[PTIndex] = PageTable[PTIndex] & (INTN)(INT32)(~PAGE_ATTRIBUTE_BITS);
}
+
//
// Set XD bit to 1
//
@@ -297,7 +303,7 @@ RestorePageTableAbove4G ( //
ASSERT (mPFEntryCount[CpuIndex] < MAX_PF_ENTRY_COUNT);
if (mPFEntryCount[CpuIndex] < MAX_PF_ENTRY_COUNT) {
- PFIndex = mPFEntryCount[CpuIndex];
+ PFIndex = mPFEntryCount[CpuIndex];
mLastPFEntryValue[CpuIndex][PFIndex] = PageTable[PTIndex];
mLastPFEntryPointer[CpuIndex][PFIndex] = &PageTable[PTIndex];
mPFEntryCount[CpuIndex]++;
@@ -326,7 +332,7 @@ RestorePageTableAbove4G ( **/
VOID
ClearTrapFlag (
- IN OUT EFI_SYSTEM_CONTEXT SystemContext
+ IN OUT EFI_SYSTEM_CONTEXT SystemContext
)
{
SystemContext.SystemContextX64->Rflags &= (UINTN) ~BIT8;
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.h b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.h index a857f587eb..80205c9b3e 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.h +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.h @@ -12,50 +12,50 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #pragma pack (1)
typedef struct _MSR_DS_AREA_STRUCT {
- UINT64 BTSBufferBase;
- UINT64 BTSIndex;
- UINT64 BTSAbsoluteMaximum;
- UINT64 BTSInterruptThreshold;
- UINT64 PEBSBufferBase;
- UINT64 PEBSIndex;
- UINT64 PEBSAbsoluteMaximum;
- UINT64 PEBSInterruptThreshold;
- UINT64 PEBSCounterReset[2];
- UINT64 Reserved;
+ UINT64 BTSBufferBase;
+ UINT64 BTSIndex;
+ UINT64 BTSAbsoluteMaximum;
+ UINT64 BTSInterruptThreshold;
+ UINT64 PEBSBufferBase;
+ UINT64 PEBSIndex;
+ UINT64 PEBSAbsoluteMaximum;
+ UINT64 PEBSInterruptThreshold;
+ UINT64 PEBSCounterReset[2];
+ UINT64 Reserved;
} MSR_DS_AREA_STRUCT;
typedef struct _BRANCH_TRACE_RECORD {
- UINT64 LastBranchFrom;
- UINT64 LastBranchTo;
- UINT64 Rsvd0 : 4;
- UINT64 BranchPredicted : 1;
- UINT64 Rsvd1 : 59;
+ UINT64 LastBranchFrom;
+ UINT64 LastBranchTo;
+ UINT64 Rsvd0 : 4;
+ UINT64 BranchPredicted : 1;
+ UINT64 Rsvd1 : 59;
} BRANCH_TRACE_RECORD;
typedef struct _PEBS_RECORD {
- UINT64 Rflags;
- UINT64 LinearIP;
- UINT64 Rax;
- UINT64 Rbx;
- UINT64 Rcx;
- UINT64 Rdx;
- UINT64 Rsi;
- UINT64 Rdi;
- UINT64 Rbp;
- UINT64 Rsp;
- UINT64 R8;
- UINT64 R9;
- UINT64 R10;
- UINT64 R11;
- UINT64 R12;
- UINT64 R13;
- UINT64 R14;
- UINT64 R15;
+ UINT64 Rflags;
+ UINT64 LinearIP;
+ UINT64 Rax;
+ UINT64 Rbx;
+ UINT64 Rcx;
+ UINT64 Rdx;
+ UINT64 Rsi;
+ UINT64 Rdi;
+ UINT64 Rbp;
+ UINT64 Rsp;
+ UINT64 R8;
+ UINT64 R9;
+ UINT64 R10;
+ UINT64 R11;
+ UINT64 R12;
+ UINT64 R13;
+ UINT64 R14;
+ UINT64 R15;
} PEBS_RECORD;
#pragma pack ()
-#define PHYSICAL_ADDRESS_MASK ((1ull << 52) - SIZE_4KB)
+#define PHYSICAL_ADDRESS_MASK ((1ull << 52) - SIZE_4KB)
/**
Update page table to map the memory correctly in order to make the instruction
@@ -71,11 +71,11 @@ typedef struct _PEBS_RECORD { **/
VOID
RestorePageTableAbove4G (
- UINT64 *PageTable,
- UINT64 PFAddress,
- UINTN CpuIndex,
- UINTN ErrorCode,
- BOOLEAN *IsValidPFAddress
+ UINT64 *PageTable,
+ UINT64 PFAddress,
+ UINTN CpuIndex,
+ UINTN ErrorCode,
+ BOOLEAN *IsValidPFAddress
);
/**
|