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author | Wu, Jiaxin <jiaxin.wu@intel.com> | 2023-02-16 14:16:28 +0800 |
---|---|---|
committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2023-03-06 06:07:48 +0000 |
commit | cb4820b6c148e62f9317799610b6e8dcd346c936 (patch) | |
tree | 087a0748b9aca4d653ca13ff3487734fd478f1c1 /UefiCpuPkg/PiSmmCpuDxeSmm | |
parent | 5a0932b7d480c05761a3ba9b5cf1d2fbb470c615 (diff) | |
download | edk2-cb4820b6c148e62f9317799610b6e8dcd346c936.tar.gz edk2-cb4820b6c148e62f9317799610b6e8dcd346c936.tar.bz2 edk2-cb4820b6c148e62f9317799610b6e8dcd346c936.zip |
UefiCpuPkg/PiSmmCpuDxeSmm: Fix invalid InitializeMpSyncData call
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4338
No need call InitializeMpSyncData during normal boot SMI init,
because mSmmMpSyncData is NULL at that time. mSmmMpSyncData is
allocated in InitializeMpServiceData, which is invoked after
normal boot SMI init (SmmRelocateBases).
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Zeng Star <star.zeng@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Ray Ni <ray.ni@Intel.com>
Diffstat (limited to 'UefiCpuPkg/PiSmmCpuDxeSmm')
-rw-r--r-- | UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c index 655175a2c6..2ac655d032 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c @@ -1,7 +1,7 @@ /** @file
Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU.
-Copyright (c) 2009 - 2019, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2009 - 2023, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -371,9 +371,7 @@ SmmInitHandler ( // Check XD and BTS features on each processor on normal boot
//
CheckFeatureSupported ();
- }
-
- if (mIsBsp) {
+ } else if (mIsBsp) {
//
// BSP rebase is already done above.
// Initialize private data during S3 resume
|