diff options
author | Jeff Fan <jeff.fan@intel.com> | 2017-03-07 14:32:28 +0800 |
---|---|---|
committer | Jeff Fan <jeff.fan@intel.com> | 2017-03-22 10:11:21 +0800 |
commit | 9cc45009ba7736eff2a61c7e7130d4d3c5d89f5b (patch) | |
tree | e291474362e46437d5bfca0cbf6fecc36e8b2521 /UefiCpuPkg/PiSmmCpuDxeSmm | |
parent | 5920a9d16b1ab887c2858224316a98e961d71b05 (diff) | |
download | edk2-9cc45009ba7736eff2a61c7e7130d4d3c5d89f5b.tar.gz edk2-9cc45009ba7736eff2a61c7e7130d4d3c5d89f5b.tar.bz2 edk2-9cc45009ba7736eff2a61c7e7130d4d3c5d89f5b.zip |
UefiCpuPkg/AcpiCpuData: Update RegisterTableEntry type
Current RegisterTableEntry filed in CPU_REGISTER_TABLE is one pointer to
CPU_REGISTER_TABLE_ENTRY. If CPU register table wants to be passed from 32bit
PEI to x64 DXE/SMM, x64 DXE/SMM cannot get the correct RegisterTableEntry.
This update is to update RegisterTableEntry type to EFI_PHYSICAL_ADDRESS and
make RegisterTableEntry is fixed length.
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
Diffstat (limited to 'UefiCpuPkg/PiSmmCpuDxeSmm')
-rw-r--r-- | UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c index 532b7c44bd..12efc1f90e 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c @@ -1,7 +1,7 @@ /** @file
Code for Processor S3 restoration
-Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -826,13 +826,12 @@ CopyRegisterTable ( CopyMem (DestinationRegisterTableList, SourceRegisterTableList, NumberOfCpus * sizeof (CPU_REGISTER_TABLE));
for (Index = 0; Index < NumberOfCpus; Index++) {
- DestinationRegisterTableList[Index].RegisterTableEntry = AllocatePool (DestinationRegisterTableList[Index].AllocatedSize);
- ASSERT (DestinationRegisterTableList[Index].RegisterTableEntry != NULL);
- CopyMem (DestinationRegisterTableList[Index].RegisterTableEntry, SourceRegisterTableList[Index].RegisterTableEntry, DestinationRegisterTableList[Index].AllocatedSize);
+ RegisterTableEntry = AllocatePool (DestinationRegisterTableList[Index].AllocatedSize);
+ ASSERT (RegisterTableEntry != NULL);
+ CopyMem (RegisterTableEntry, (VOID *)(UINTN)SourceRegisterTableList[Index].RegisterTableEntry, DestinationRegisterTableList[Index].AllocatedSize);
//
// Go though all MSRs in register table to initialize MSR spin lock
//
- RegisterTableEntry = DestinationRegisterTableList[Index].RegisterTableEntry;
for (Index1 = 0; Index1 < DestinationRegisterTableList[Index].TableLength; Index1++, RegisterTableEntry++) {
if ((RegisterTableEntry->RegisterType == Msr) && (RegisterTableEntry->ValidBitLength < 64)) {
//
@@ -841,6 +840,7 @@ CopyRegisterTable ( InitMsrSpinLockByIndex (RegisterTableEntry->Index);
}
}
+ DestinationRegisterTableList[Index].RegisterTableEntry = (EFI_PHYSICAL_ADDRESS)(UINTN)RegisterTableEntry;
}
}
|