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| author | Jiaxin Wu <jiaxin.wu@intel.com> | 2023-04-06 20:29:24 +0800 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2023-05-31 04:48:36 +0000 |
| commit | b4d3b7797347c37b68bd9b9b6de0e75d9f447b14 (patch) | |
| tree | fcf91649f375834f4129d9e851af5bb757839075 /UefiCpuPkg/SecCore/SecCore.inf | |
| parent | 0f9283429dd487deeeb264ee5670551d596fc208 (diff) | |
| download | edk2-b4d3b7797347c37b68bd9b9b6de0e75d9f447b14.tar.gz edk2-b4d3b7797347c37b68bd9b9b6de0e75d9f447b14.tar.bz2 edk2-b4d3b7797347c37b68bd9b9b6de0e75d9f447b14.zip | |
UefiCpuPkg/SecCore: Migrate page table to permanent memory
Background:
For arch X64, system will enable the page table in SPI to cover 0-512G
range via CR4.PAE & MSR.LME & CR0.PG & CR3 setting (see ResetVector code).
Existing code doesn't cover the higher address access above 512G before
memory-discovered callback. That will be potential problem if system
access the higher address after the transition from temporary RAM to
permanent MEM RAM.
Solution:
This patch is to migrate page table to permanent memory to map entire physical
address space if CR0.PG is set during temporary RAM Done.
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Zeng Star <star.zeng@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Diffstat (limited to 'UefiCpuPkg/SecCore/SecCore.inf')
| -rw-r--r-- | UefiCpuPkg/SecCore/SecCore.inf | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/UefiCpuPkg/SecCore/SecCore.inf b/UefiCpuPkg/SecCore/SecCore.inf index 3758aded3b..cab69b8b97 100644 --- a/UefiCpuPkg/SecCore/SecCore.inf +++ b/UefiCpuPkg/SecCore/SecCore.inf @@ -55,6 +55,7 @@ PeiServicesLib
PeiServicesTablePointerLib
HobLib
+ CpuPageTableLib
[Ppis]
## SOMETIMES_CONSUMES
|