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| author | Jian J Wang <jian.j.wang@intel.com> | 2017-12-27 17:06:18 +0800 |
|---|---|---|
| committer | Liming Gao <liming.gao@intel.com> | 2017-12-27 17:42:52 +0800 |
| commit | d69ba6a729996b288b4fb2b033969ab15cbf5d59 (patch) | |
| tree | 5d6edd499f1528251450229e5ff3aeb4cd1e0014 /UefiCpuPkg | |
| parent | 3ab032fc0f5460bce73c876db7b253a072750953 (diff) | |
| download | edk2-d69ba6a729996b288b4fb2b033969ab15cbf5d59.tar.gz edk2-d69ba6a729996b288b4fb2b033969ab15cbf5d59.tar.bz2 edk2-d69ba6a729996b288b4fb2b033969ab15cbf5d59.zip | |
UefiCpuPkg: Rollback field name changes
Roll back commit 56649f43013703e95f54c293d708152b765cc49b.
The original names follows the spec definition.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jian J Wang <jian.j.wang@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Diffstat (limited to 'UefiCpuPkg')
3 files changed, 16 insertions, 16 deletions
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c index 4e89b0470f..6ac8549839 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c @@ -216,7 +216,7 @@ ArchSetupExcpetionStack ( TssDesc->Bits.BaseLow = (UINT16)TssBase;
TssDesc->Bits.BaseMid = (UINT8)(TssBase >> 16);
TssDesc->Bits.Type = IA32_GDT_TYPE_TSS;
- TssDesc->Bits.Present = 1;
+ TssDesc->Bits.P = 1;
TssDesc->Bits.LimitHigh = 0;
TssDesc->Bits.BaseHigh = (UINT8)(TssBase >> 24);
@@ -240,7 +240,7 @@ ArchSetupExcpetionStack ( TssDesc->Bits.BaseLow = (UINT16)TssBase;
TssDesc->Bits.BaseMid = (UINT8)(TssBase >> 16);
TssDesc->Bits.Type = IA32_GDT_TYPE_TSS;
- TssDesc->Bits.Present = 1;
+ TssDesc->Bits.P = 1;
TssDesc->Bits.LimitHigh = 0;
TssDesc->Bits.BaseHigh = (UINT8)(TssBase >> 24);
@@ -253,17 +253,17 @@ ArchSetupExcpetionStack ( continue;
}
- Tss->Eip = (UINT32)(TemplateMap.ExceptionStart
+ Tss->EIP = (UINT32)(TemplateMap.ExceptionStart
+ Vector * TemplateMap.ExceptionStubHeaderSize);
- Tss->Eflags = 0x2;
- Tss->Esp = StackTop;
- Tss->Cr3 = AsmReadCr3 ();
- Tss->Es = AsmReadEs ();
- Tss->Cs = AsmReadCs ();
- Tss->Ss = AsmReadSs ();
- Tss->Ds = AsmReadDs ();
- Tss->Fs = AsmReadFs ();
- Tss->Gs = AsmReadGs ();
+ Tss->EFLAGS = 0x2;
+ Tss->ESP = StackTop;
+ Tss->CR3 = AsmReadCr3 ();
+ Tss->ES = AsmReadEs ();
+ Tss->CS = AsmReadCs ();
+ Tss->SS = AsmReadSs ();
+ Tss->DS = AsmReadDs ();
+ Tss->FS = AsmReadFs ();
+ Tss->GS = AsmReadGs ();
StackTop -= StackSwitchData->Ia32.KnownGoodStackSize;
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c index 4d52b4eb0e..1dcf4277de 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c @@ -186,7 +186,7 @@ ArchSetupExcpetionStack ( //
TssDesc = StackSwitchData->X64.ExceptionTssDesc;
Tss = StackSwitchData->X64.ExceptionTss;
- if (StackSwitchData->X64.StackSwitchExceptionNumber > ARRAY_SIZE (Tss->Ist)) {
+ if (StackSwitchData->X64.StackSwitchExceptionNumber > ARRAY_SIZE (Tss->IST)) {
return EFI_INVALID_PARAMETER;
}
@@ -221,7 +221,7 @@ ArchSetupExcpetionStack ( TssDesc->Bits.BaseLow = (UINT16)TssBase;
TssDesc->Bits.BaseMidl = (UINT8)(TssBase >> 16);
TssDesc->Bits.Type = IA32_GDT_TYPE_TSS;
- TssDesc->Bits.Present = 1;
+ TssDesc->Bits.P = 1;
TssDesc->Bits.LimitHigh = 0;
TssDesc->Bits.BaseMidh = (UINT8)(TssBase >> 24);
TssDesc->Bits.BaseHigh = (UINT32)(TssBase >> 32);
@@ -236,7 +236,7 @@ ArchSetupExcpetionStack ( //
// Fixup IST
//
- Tss->Ist[Index] = StackTop;
+ Tss->IST[Index] = StackTop;
StackTop -= StackSwitchData->X64.KnownGoodStackSize;
//
diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpInitLib/MpLib.c index da1a43c430..0c2058a7b0 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c @@ -243,7 +243,7 @@ RestoreVolatileRegisters ( VolatileRegisters->Tr < VolatileRegisters->Gdtr.Limit) {
Tss = (IA32_TSS_DESCRIPTOR *)(VolatileRegisters->Gdtr.Base +
VolatileRegisters->Tr);
- if (Tss->Bits.Present == 1) {
+ if (Tss->Bits.P == 1) {
Tss->Bits.Type &= 0xD; // 1101 - Clear busy bit just in case
AsmWriteTr (VolatileRegisters->Tr);
}
|