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| author | Ray Ni <ray.ni@intel.com> | 2021-05-12 00:34:49 +0800 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2021-05-18 08:07:57 +0000 |
| commit | 29e300ff815283259e81822ed3cb926bb9ad6460 (patch) | |
| tree | bd85d65ec27d47299402155d96098662a8abc4f4 /UefiCpuPkg | |
| parent | 1fbf5e30ae8eb725f4e10984f7b0a208f78abbd0 (diff) | |
| download | edk2-29e300ff815283259e81822ed3cb926bb9ad6460.tar.gz edk2-29e300ff815283259e81822ed3cb926bb9ad6460.tar.bz2 edk2-29e300ff815283259e81822ed3cb926bb9ad6460.zip | |
UefiCpuPkg/PiSmmCpu: Remove hardcode 48 address size limitation
5-level paging can be enabled on CPU which supports up to 52 physical
address size. But when the feature was enabled, the 48 address size
limit was not removed and the 5-level paging testing didn't access
address >= 2^48. So the issue wasn't detected until recently an
address >= 2^48 is accessed.
Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Diffstat (limited to 'UefiCpuPkg')
| -rw-r--r-- | UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 26 |
1 files changed, 18 insertions, 8 deletions
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c index fd6583f9d1..89143810b6 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c @@ -1887,11 +1887,13 @@ InitializeMpServiceData ( IN UINTN ShadowStackSize
)
{
- UINT32 Cr3;
- UINTN Index;
- UINT8 *GdtTssTables;
- UINTN GdtTableStepSize;
- CPUID_VERSION_INFO_EDX RegEdx;
+ UINT32 Cr3;
+ UINTN Index;
+ UINT8 *GdtTssTables;
+ UINTN GdtTableStepSize;
+ CPUID_VERSION_INFO_EDX RegEdx;
+ UINT32 MaxExtendedFunction;
+ CPUID_VIR_PHY_ADDRESS_SIZE_EAX VirPhyAddressSize;
//
// Determine if this CPU supports machine check
@@ -1918,9 +1920,17 @@ InitializeMpServiceData ( // Initialize physical address mask
// NOTE: Physical memory above virtual address limit is not supported !!!
//
- AsmCpuid (0x80000008, (UINT32*)&Index, NULL, NULL, NULL);
- gPhyMask = LShiftU64 (1, (UINT8)Index) - 1;
- gPhyMask &= (1ull << 48) - EFI_PAGE_SIZE;
+ AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedFunction, NULL, NULL, NULL);
+ if (MaxExtendedFunction >= CPUID_VIR_PHY_ADDRESS_SIZE) {
+ AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &VirPhyAddressSize.Uint32, NULL, NULL, NULL);
+ } else {
+ VirPhyAddressSize.Bits.PhysicalAddressBits = 36;
+ }
+ gPhyMask = LShiftU64 (1, VirPhyAddressSize.Bits.PhysicalAddressBits) - 1;
+ //
+ // Clear the low 12 bits
+ //
+ gPhyMask &= 0xfffffffffffff000ULL;
//
// Create page tables
|