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authorLiu, Zhiguang <Zhiguang.Liu@intel.com>2022-08-25 10:55:04 +0800
committermergify[bot] <37929162+mergify[bot]@users.noreply.github.com>2022-08-31 04:23:55 +0000
commit367604b2f49f1b7517756a4ecab426f5308ba7fb (patch)
tree1ea8fbf028e80c9ce87aee5fdb15f983612d828e /UefiCpuPkg
parent3c06953fd76ca2d1372ce5b0df14608de53cd148 (diff)
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UefiCpuPkg/MpInitLib: Fix potential issue when IDT table is at above 4G
Currently, when waking up AP, IDT table of AP will be set in 16 bit code, and assume the IDT table base is 32 bit. However, the IDT table is created by BSP. Issue will happen if the BSP allocates memory above 4G for BSP's IDT table. Moreover, even the IDT table location is below 4G, the handler function inside the IDT table is 64 bit, and it won't take effect until CPU transfers to 64 bit long mode. There is no benefit to set IDT table in such an early phase. To avoid such issue, this patch moves the LIDT instruction into 64 bit code. Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
Diffstat (limited to 'UefiCpuPkg')
-rw-r--r--UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm8
1 files changed, 5 insertions, 3 deletions
diff --git a/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm b/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm
index 1daaa72b1e..cd95b03da8 100644
--- a/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm
+++ b/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm
@@ -64,9 +64,6 @@ BITS 16
mov si, MP_CPU_EXCHANGE_INFO_FIELD (GdtrProfile)
o32 lgdt [cs:si]
- mov si, MP_CPU_EXCHANGE_INFO_FIELD (IdtrProfile)
-o32 lidt [cs:si]
-
;
; Switch to protected mode
;
@@ -154,6 +151,11 @@ BITS 64
LongModeStart:
mov esi, ebx
+
+ ; Set IDT table at the start of 64 bit code
+ lea edi, [esi + MP_CPU_EXCHANGE_INFO_FIELD (IdtrProfile)]
+ lidt [edi]
+
lea edi, [esi + MP_CPU_EXCHANGE_INFO_FIELD (InitFlag)]
cmp qword [edi], 1 ; ApInitConfig
jnz GetApicId