UefiCpuPkg/ResetVector: Rename macros about page table.

This patch only renames macro, with no code logic impacted.
Two purpose to rename macro:
1. Align some macro name in PageTables1G.asm and PageTables2M.asm, so
that these two files can be easily combined later.
2. Some Macro names such as PDP are not accurate, since 4 level page
entry also uses this macro. PAGE_NLE (no leaf entry) is better

Cc: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Tested-by: Gerd Hoffmann <kraxel@redhat.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Cc: Debkumar De <debkumar.de@intel.com>
Cc: Catharine West <catharine.west@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>

2 files changed, 39 insertions, 22 deletions

diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm
index 19bd3d5a92..20a61f949c 100644
--- a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm
+++ b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm
@@ -2,7 +2,7 @@
 ; @file

 ; Emits Page Tables for 1:1 mapping of the addresses 0 - 0x8000000000 (512GB)

 ;

-; Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>

+; Copyright (c) 2021 - 2023, Intel Corporation. All rights reserved.<BR>

 ; SPDX-License-Identifier: BSD-2-Clause-Patent

 ; Linear-Address Translation to a 1-GByte Page

 ;

@@ -12,11 +12,18 @@ BITS    64
 

 %define ALIGN_TOP_TO_4K_FOR_PAGING

 

-%define PAGE_PDP_ATTR (PAGE_ACCESSED + \

+;

+; Page table non-leaf entry attribute

+;

+%define PAGE_NLE_ATTR (PAGE_ACCESSED + \

                         PAGE_READ_WRITE + \

                         PAGE_PRESENT)

 

-%define PAGE_PDP_1G_ATTR (PAGE_ACCESSED + \

+;

+; Page table big leaf entry attribute:

+; PDPTE 1GB entry or PDE 2MB entry

+;

+%define PAGE_BLE_ATTR (PAGE_ACCESSED + \

                         PAGE_READ_WRITE + \

                         PAGE_DIRTY + \

                         PAGE_PRESENT + \

@@ -25,10 +32,13 @@ BITS    64
 %define PGTBLS_OFFSET(x) ((x) - TopLevelPageDirectory)

 %define PGTBLS_ADDR(x) (ADDR_OF(TopLevelPageDirectory) + (x))

 

-%define PDP(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \

-                    PAGE_PDP_ATTR)

+;

+; Page table non-leaf entry

+;

+%define PAGE_NLE(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \

+                    PAGE_NLE_ATTR)

 

-%define PDP_1G(x) ((x << 30) + PAGE_PDP_1G_ATTR)

+%define PAGE_PDPTE_1GB(x) ((x << 30) + PAGE_BLE_ATTR)

 

 ALIGN 16

 

@@ -37,7 +47,7 @@ TopLevelPageDirectory:
     ;

     ; Top level Page Directory Pointers (1 * 512GB entry)

     ;

-    DQ      PDP(0x1000)

+    DQ      PAGE_NLE(0x1000)

 

     TIMES 0x1000-PGTBLS_OFFSET($) DB 0

     ;

@@ -45,7 +55,7 @@ TopLevelPageDirectory:
     ;

 %assign i 0

 %rep      512

-    DQ    PDP_1G(i)

+    DQ    PAGE_PDPTE_1GB(i)

     %assign i i+1

 %endrep

     TIMES 0x2000-PGTBLS_OFFSET($) DB 0

diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm
index b97df384ac..1221b023fe 100644
--- a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm
+++ b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm
@@ -2,7 +2,7 @@
 ; @file

 ; Emits Page Tables for 1:1 mapping of the addresses 0 - 0x100000000 (4GB)

 ;

-; Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.<BR>

+; Copyright (c) 2008 - 2023, Intel Corporation. All rights reserved.<BR>

 ; SPDX-License-Identifier: BSD-2-Clause-Patent

 ;

 ;------------------------------------------------------------------------------

@@ -11,29 +11,36 @@ BITS    64
 

 %define ALIGN_TOP_TO_4K_FOR_PAGING

 

-%define PAGE_2M_PDE_ATTR (PAGE_SIZE + \

+;

+; Page table big leaf entry attribute:

+; PDPTE 1GB entry or PDE 2MB entry

+;

+%define PAGE_BLE_ATTR   (PAGE_SIZE + \

                           PAGE_ACCESSED + \

                           PAGE_DIRTY + \

                           PAGE_READ_WRITE + \

                           PAGE_PRESENT)

 

-%define PAGE_PDP_ATTR (PAGE_ACCESSED + \

-                       PAGE_READ_WRITE + \

-                       PAGE_PRESENT)

+;

+; Page table non-leaf entry attribute

+;

+%define PAGE_NLE_ATTR (PAGE_ACCESSED + \

+                        PAGE_READ_WRITE + \

+                        PAGE_PRESENT)

 

 %define PGTBLS_OFFSET(x) ((x) - TopLevelPageDirectory)

 %define PGTBLS_ADDR(x) (ADDR_OF(TopLevelPageDirectory) + (x))

 

-%define PDP(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \

-                     PAGE_PDP_ATTR)

-%define PTE_2MB(x) ((x << 21) + PAGE_2M_PDE_ATTR)

+%define PAGE_NLE(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \

+                    PAGE_NLE_ATTR)

+%define PAGE_PDE_2MB(x) ((x << 21) + PAGE_BLE_ATTR)

 

 TopLevelPageDirectory:

 

     ;

     ; Top level Page Directory Pointers (1 * 512GB entry)

     ;

-    DQ      PDP(0x1000)

+    DQ      PAGE_NLE(0x1000)

 

 

     ;

@@ -41,10 +48,10 @@ TopLevelPageDirectory:
     ;

     TIMES 0x1000-PGTBLS_OFFSET($) DB 0

 

-    DQ      PDP(0x2000)

-    DQ      PDP(0x3000)

-    DQ      PDP(0x4000)

-    DQ      PDP(0x5000)

+    DQ      PAGE_NLE(0x2000)

+    DQ      PAGE_NLE(0x3000)

+    DQ      PAGE_NLE(0x4000)

+    DQ      PAGE_NLE(0x5000)

 

     ;

     ; Page Table Entries (2048 * 2MB entries => 4GB)

@@ -53,7 +60,7 @@ TopLevelPageDirectory:
 

 %assign i 0

 %rep    0x800

-    DQ      PTE_2MB(i)

+    DQ      PAGE_PDE_2MB(i)

     %assign i i+1

 %endrep