summaryrefslogtreecommitdiffstats
path: root/UefiPayloadPkg/Library
diff options
context:
space:
mode:
authorLean Sheng Tan <sheng.tan@9elements.com>2022-03-30 11:29:02 -0700
committermergify[bot] <37929162+mergify[bot]@users.noreply.github.com>2022-04-10 17:46:10 +0000
commitbfefdc2c49ca9487b7aa0df196b2aca6c0c170a2 (patch)
tree0823d2c227d1b042cb8c4637d923ebb8711d3c49 /UefiPayloadPkg/Library
parent4f4afcd28802ff8a3e78ad72e47b6acb6e24819c (diff)
downloadedk2-bfefdc2c49ca9487b7aa0df196b2aca6c0c170a2.tar.gz
edk2-bfefdc2c49ca9487b7aa0df196b2aca6c0c170a2.tar.bz2
edk2-bfefdc2c49ca9487b7aa0df196b2aca6c0c170a2.zip
UefiPayloadPkg: Fix PciHostBridgeLib
Don't assume a 64bit register always holds an address greater than 4GB. Check the value in the register and decide which Aperature it should be assigned to. Fixes assertion "ASSERT [PciHostBridgeDxe] Bridge->MemAbove4G.Base >= 0x0000000100000000ULL". Tested with coreboot as bootloader on platforms that have PCI resource above 4GiB and on platforms that don't have resource above 4GiB. Cc: Guo Dong <guo.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Maurice Ma <maurice.ma@intel.com> Cc: Benjamin You <benjamin.you@intel.com> Cc: Sean Rhodes <sean@starlabs.systems> Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by Sean Rhodes <sean@starlabs.systems> Reviewed-by: Guo Dong <guo.dong@intel.com>
Diffstat (limited to 'UefiPayloadPkg/Library')
-rw-r--r--UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c13
1 files changed, 9 insertions, 4 deletions
diff --git a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c
index 8a890b6b53..e1faa24ae7 100644
--- a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c
+++ b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c
@@ -354,14 +354,19 @@ ScanForRootBridges (
Base = ((UINT32)Pci.Bridge.PrefetchableMemoryBase & 0xfff0) << 16;
Limit = (((UINT32)Pci.Bridge.PrefetchableMemoryLimit & 0xfff0)
<< 16) | 0xfffff;
- MemAperture = &Mem;
+
if (Value == BIT0) {
- Base |= LShiftU64 (Pci.Bridge.PrefetchableBaseUpper32, 32);
- Limit |= LShiftU64 (Pci.Bridge.PrefetchableLimitUpper32, 32);
- MemAperture = &MemAbove4G;
+ Base |= LShiftU64 (Pci.Bridge.PrefetchableBaseUpper32, 32);
+ Limit |= LShiftU64 (Pci.Bridge.PrefetchableLimitUpper32, 32);
}
if ((Base > 0) && (Base < Limit)) {
+ if (Base < BASE_4GB) {
+ MemAperture = &Mem;
+ } else {
+ MemAperture = &MemAbove4G;
+ }
+
if (MemAperture->Base > Base) {
MemAperture->Base = Base;
}