diff options
| author | Michael Kubacki <michael.kubacki@microsoft.com> | 2021-12-05 14:54:18 -0800 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2021-12-07 17:24:28 +0000 |
| commit | e5efcf8be8a1bf59aa98875787475e3144ee4cef (patch) | |
| tree | f872d2f419303dbd9aa1d3ad745635abffb2f233 /UefiPayloadPkg/Library | |
| parent | 053e878bfb5c9d5eca779789b62891add30b14ba (diff) | |
| download | edk2-e5efcf8be8a1bf59aa98875787475e3144ee4cef.tar.gz edk2-e5efcf8be8a1bf59aa98875787475e3144ee4cef.tar.bz2 edk2-e5efcf8be8a1bf59aa98875787475e3144ee4cef.zip | |
UefiPayloadPkg: Apply uncrustify changes
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737
Apply uncrustify changes to .c/.h files in the UefiPayloadPkg package
Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Diffstat (limited to 'UefiPayloadPkg/Library')
24 files changed, 1137 insertions, 1086 deletions
diff --git a/UefiPayloadPkg/Library/AcpiTimerLib/AcpiTimerLib.c b/UefiPayloadPkg/Library/AcpiTimerLib/AcpiTimerLib.c index 1b486647bd..1ed589a6a2 100644 --- a/UefiPayloadPkg/Library/AcpiTimerLib/AcpiTimerLib.c +++ b/UefiPayloadPkg/Library/AcpiTimerLib/AcpiTimerLib.c @@ -18,7 +18,7 @@ #define ACPI_TIMER_COUNT_SIZE BIT24
-UINTN mPmTimerReg = 0;
+UINTN mPmTimerReg = 0;
/**
The constructor function enables ACPI IO space.
@@ -67,6 +67,7 @@ InternalAcpiGetTimerTick ( if (mPmTimerReg == 0) {
AcpiTimerLibConstructor ();
}
+
return IoRead32 (mPmTimerReg);
}
@@ -81,20 +82,20 @@ InternalAcpiGetTimerTick ( **/
VOID
InternalAcpiDelay (
- IN UINT32 Delay
+ IN UINT32 Delay
)
{
- UINT32 Ticks;
- UINT32 Times;
+ UINT32 Ticks;
+ UINT32 Times;
- Times = Delay >> 22;
- Delay &= BIT22 - 1;
+ Times = Delay >> 22;
+ Delay &= BIT22 - 1;
do {
//
// The target timer count is calculated here
//
- Ticks = InternalAcpiGetTimerTick () + Delay;
- Delay = BIT22;
+ Ticks = InternalAcpiGetTimerTick () + Delay;
+ Delay = BIT22;
//
// Wait until time out
// Delay >= 2^23 could not be handled by this function
@@ -119,7 +120,7 @@ InternalAcpiDelay ( UINTN
EFIAPI
MicroSecondDelay (
- IN UINTN MicroSeconds
+ IN UINTN MicroSeconds
)
{
InternalAcpiDelay (
@@ -147,7 +148,7 @@ MicroSecondDelay ( UINTN
EFIAPI
NanoSecondDelay (
- IN UINTN NanoSeconds
+ IN UINTN NanoSeconds
)
{
InternalAcpiDelay (
@@ -209,8 +210,8 @@ GetPerformanceCounter ( UINT64
EFIAPI
GetPerformanceCounterProperties (
- OUT UINT64 *StartValue OPTIONAL,
- OUT UINT64 *EndValue OPTIONAL
+ OUT UINT64 *StartValue OPTIONAL,
+ OUT UINT64 *EndValue OPTIONAL
)
{
if (StartValue != NULL) {
@@ -238,7 +239,7 @@ GetPerformanceCounterProperties ( UINT64
EFIAPI
GetTimeInNanoSecond (
- IN UINT64 Ticks
+ IN UINT64 Ticks
)
{
UINT64 Frequency;
@@ -260,9 +261,9 @@ GetTimeInNanoSecond ( // Since 2^29 < 1,000,000,000 = 0x3B9ACA00 < 2^30, Remainder should < 2^(64-30) = 2^34,
// i.e. highest bit set in Remainder should <= 33.
//
- Shift = MAX (0, HighBitSet64 (Remainder) - 33);
- Remainder = RShiftU64 (Remainder, (UINTN) Shift);
- Frequency = RShiftU64 (Frequency, (UINTN) Shift);
+ Shift = MAX (0, HighBitSet64 (Remainder) - 33);
+ Remainder = RShiftU64 (Remainder, (UINTN)Shift);
+ Frequency = RShiftU64 (Frequency, (UINTN)Shift);
NanoSeconds += DivU64x64Remainder (MultU64x32 (Remainder, 1000000000u), Frequency, NULL);
return NanoSeconds;
diff --git a/UefiPayloadPkg/Library/CbParseLib/CbParseLib.c b/UefiPayloadPkg/Library/CbParseLib/CbParseLib.c index f73fcd8823..8a353f77f6 100644 --- a/UefiPayloadPkg/Library/CbParseLib/CbParseLib.c +++ b/UefiPayloadPkg/Library/CbParseLib/CbParseLib.c @@ -17,7 +17,6 @@ #include <IndustryStandard/Acpi.h>
#include <Coreboot.h>
-
/**
Convert a packed value from cbuint64 to a UINT64 value.
@@ -28,13 +27,12 @@ **/
UINT64
cb_unpack64 (
- IN struct cbuint64 val
+ IN struct cbuint64 val
)
{
return LShiftU64 (val.hi, 32) | val.lo;
}
-
/**
Returns the sum of all elements in a buffer of 16-bit values. During
calculation, the carry bits are also been added.
@@ -47,19 +45,19 @@ cb_unpack64 ( **/
UINT16
CbCheckSum16 (
- IN UINT16 *Buffer,
- IN UINTN Length
+ IN UINT16 *Buffer,
+ IN UINTN Length
)
{
- UINT32 Sum;
- UINT32 TmpValue;
- UINTN Idx;
- UINT8 *TmpPtr;
+ UINT32 Sum;
+ UINT32 TmpValue;
+ UINTN Idx;
+ UINT8 *TmpPtr;
- Sum = 0;
+ Sum = 0;
TmpPtr = (UINT8 *)Buffer;
- for(Idx = 0; Idx < Length; Idx++) {
- TmpValue = TmpPtr[Idx];
+ for (Idx = 0; Idx < Length; Idx++) {
+ TmpValue = TmpPtr[Idx];
if (Idx % 2 == 1) {
TmpValue <<= 8;
}
@@ -75,7 +73,6 @@ CbCheckSum16 ( return (UINT16)((~Sum) & 0xFFFF);
}
-
/**
Check the coreboot table if it is valid.
@@ -87,10 +84,10 @@ CbCheckSum16 ( **/
BOOLEAN
IsValidCbTable (
- IN struct cb_header *Header
+ IN struct cb_header *Header
)
{
- UINT16 CheckSum;
+ UINT16 CheckSum;
if ((Header == NULL) || (Header->table_bytes == 0)) {
return FALSE;
@@ -118,7 +115,6 @@ IsValidCbTable ( return TRUE;
}
-
/**
This function retrieves the parameter base address from boot loader.
@@ -135,12 +131,12 @@ GetParameterBase ( VOID
)
{
- struct cb_header *Header;
- struct cb_record *Record;
- UINT8 *TmpPtr;
- UINT8 *CbTablePtr;
- UINTN Idx;
- EFI_STATUS Status;
+ struct cb_header *Header;
+ struct cb_record *Record;
+ UINT8 *TmpPtr;
+ UINT8 *CbTablePtr;
+ UINTN Idx;
+ EFI_STATUS Status;
//
// coreboot could pass coreboot table to UEFI payload
@@ -177,13 +173,14 @@ GetParameterBase ( // Find full coreboot table in high memory
//
CbTablePtr = NULL;
- TmpPtr = (UINT8 *)Header + Header->header_bytes;
+ TmpPtr = (UINT8 *)Header + Header->header_bytes;
for (Idx = 0; Idx < Header->table_entries; Idx++) {
Record = (struct cb_record *)TmpPtr;
if (Record->tag == CB_TAG_FORWARD) {
CbTablePtr = (VOID *)(UINTN)((struct cb_forward *)(UINTN)Record)->forward;
break;
}
+
TmpPtr += Record->size;
}
@@ -200,7 +197,6 @@ GetParameterBase ( return CbTablePtr;
}
-
/**
Find coreboot record with given Tag.
@@ -212,16 +208,16 @@ GetParameterBase ( **/
VOID *
FindCbTag (
- IN UINT32 Tag
+ IN UINT32 Tag
)
{
- struct cb_header *Header;
- struct cb_record *Record;
- UINT8 *TmpPtr;
- UINT8 *TagPtr;
- UINTN Idx;
+ struct cb_header *Header;
+ struct cb_record *Record;
+ UINT8 *TmpPtr;
+ UINT8 *TagPtr;
+ UINTN Idx;
- Header = (struct cb_header *) GetParameterBase ();
+ Header = (struct cb_header *)GetParameterBase ();
TagPtr = NULL;
TmpPtr = (UINT8 *)Header + Header->header_bytes;
@@ -231,13 +227,13 @@ FindCbTag ( TagPtr = TmpPtr;
break;
}
+
TmpPtr += Record->size;
}
return TagPtr;
}
-
/**
Find the given table with TableId from the given coreboot memory Root.
@@ -259,13 +255,14 @@ FindCbMemTable ( OUT UINT32 *MemTableSize
)
{
- UINTN Idx;
- BOOLEAN IsImdEntry;
- struct cbmem_entry *Entries;
+ UINTN Idx;
+ BOOLEAN IsImdEntry;
+ struct cbmem_entry *Entries;
if ((Root == NULL) || (MemTable == NULL)) {
return RETURN_INVALID_PARAMETER;
}
+
//
// Check if the entry is CBMEM or IMD
// and handle them separately
@@ -285,16 +282,22 @@ FindCbMemTable ( for (Idx = 0; Idx < Root->num_entries; Idx++) {
if (Entries[Idx].id == TableId) {
if (IsImdEntry) {
- *MemTable = (VOID *) ((UINTN)Entries[Idx].start + (UINTN)Root);
+ *MemTable = (VOID *)((UINTN)Entries[Idx].start + (UINTN)Root);
} else {
- *MemTable = (VOID *) (UINTN)Entries[Idx].start;
+ *MemTable = (VOID *)(UINTN)Entries[Idx].start;
}
+
if (MemTableSize != NULL) {
*MemTableSize = Entries[Idx].size;
}
- DEBUG ((DEBUG_INFO, "Find CbMemTable Id 0x%x, base %p, size 0x%x\n",
- TableId, *MemTable, Entries[Idx].size));
+ DEBUG ((
+ DEBUG_INFO,
+ "Find CbMemTable Id 0x%x, base %p, size 0x%x\n",
+ TableId,
+ *MemTable,
+ Entries[Idx].size
+ ));
return RETURN_SUCCESS;
}
}
@@ -316,18 +319,18 @@ FindCbMemTable ( **/
RETURN_STATUS
ParseCbMemTable (
- IN UINT32 TableId,
- OUT VOID **MemTable,
- OUT UINT32 *MemTableSize
+ IN UINT32 TableId,
+ OUT VOID **MemTable,
+ OUT UINT32 *MemTableSize
)
{
- EFI_STATUS Status;
- CB_MEMORY *Rec;
- struct cb_memory_range *Range;
- UINT64 Start;
- UINT64 Size;
- UINTN Index;
- struct cbmem_root *CbMemRoot;
+ EFI_STATUS Status;
+ CB_MEMORY *Rec;
+ struct cb_memory_range *Range;
+ UINT64 Start;
+ UINT64 Size;
+ UINTN Index;
+ struct cbmem_root *CbMemRoot;
if (MemTable == NULL) {
return RETURN_INVALID_PARAMETER;
@@ -344,14 +347,14 @@ ParseCbMemTable ( return Status;
}
- for (Index = 0; Index < MEM_RANGE_COUNT(Rec); Index++) {
- Range = MEM_RANGE_PTR(Rec, Index);
- Start = cb_unpack64(Range->start);
- Size = cb_unpack64(Range->size);
+ for (Index = 0; Index < MEM_RANGE_COUNT (Rec); Index++) {
+ Range = MEM_RANGE_PTR (Rec, Index);
+ Start = cb_unpack64 (Range->start);
+ Size = cb_unpack64 (Range->size);
if ((Range->type == CB_MEM_TABLE) && (Start > 0x1000)) {
CbMemRoot = (struct cbmem_root *)(UINTN)(Start + Size - DYN_CBMEM_ALIGN_SIZE);
- Status = FindCbMemTable (CbMemRoot, TableId, MemTable, MemTableSize);
+ Status = FindCbMemTable (CbMemRoot, TableId, MemTable, MemTableSize);
if (!EFI_ERROR (Status)) {
break;
}
@@ -361,8 +364,6 @@ ParseCbMemTable ( return Status;
}
-
-
/**
Acquire the memory information from the coreboot table in memory.
@@ -380,10 +381,10 @@ ParseMemoryInfo ( IN VOID *Params
)
{
- CB_MEMORY *Rec;
- struct cb_memory_range *Range;
- UINTN Index;
- MEMORY_MAP_ENTRY MemoryMap;
+ CB_MEMORY *Rec;
+ struct cb_memory_range *Range;
+ UINTN Index;
+ MEMORY_MAP_ENTRY MemoryMap;
//
// Get the coreboot memory table
@@ -393,14 +394,20 @@ ParseMemoryInfo ( return RETURN_NOT_FOUND;
}
- for (Index = 0; Index < MEM_RANGE_COUNT(Rec); Index++) {
- Range = MEM_RANGE_PTR(Rec, Index);
- MemoryMap.Base = cb_unpack64(Range->start);
- MemoryMap.Size = cb_unpack64(Range->size);
+ for (Index = 0; Index < MEM_RANGE_COUNT (Rec); Index++) {
+ Range = MEM_RANGE_PTR (Rec, Index);
+ MemoryMap.Base = cb_unpack64 (Range->start);
+ MemoryMap.Size = cb_unpack64 (Range->size);
MemoryMap.Type = (UINT8)Range->type;
MemoryMap.Flag = 0;
- DEBUG ((DEBUG_INFO, "%d. %016lx - %016lx [%02x]\n",
- Index, MemoryMap.Base, MemoryMap.Base + MemoryMap.Size - 1, MemoryMap.Type));
+ DEBUG ((
+ DEBUG_INFO,
+ "%d. %016lx - %016lx [%02x]\n",
+ Index,
+ MemoryMap.Base,
+ MemoryMap.Base + MemoryMap.Size - 1,
+ MemoryMap.Type
+ ));
MemInfoCallback (&MemoryMap, Params);
}
@@ -408,7 +415,6 @@ ParseMemoryInfo ( return RETURN_SUCCESS;
}
-
/**
Acquire SMBIOS table from coreboot.
@@ -421,23 +427,23 @@ ParseMemoryInfo ( RETURN_STATUS
EFIAPI
ParseSmbiosTable (
- OUT UNIVERSAL_PAYLOAD_SMBIOS_TABLE *SmbiosTable
+ OUT UNIVERSAL_PAYLOAD_SMBIOS_TABLE *SmbiosTable
)
{
- EFI_STATUS Status;
- VOID *MemTable;
- UINT32 MemTableSize;
+ EFI_STATUS Status;
+ VOID *MemTable;
+ UINT32 MemTableSize;
Status = ParseCbMemTable (SIGNATURE_32 ('T', 'B', 'M', 'S'), &MemTable, &MemTableSize);
if (EFI_ERROR (Status)) {
return EFI_NOT_FOUND;
}
- SmbiosTable->SmBiosEntryPoint = (UINT64) (UINTN)MemTable;
+
+ SmbiosTable->SmBiosEntryPoint = (UINT64)(UINTN)MemTable;
return RETURN_SUCCESS;
}
-
/**
Acquire ACPI table from coreboot.
@@ -450,23 +456,23 @@ ParseSmbiosTable ( RETURN_STATUS
EFIAPI
ParseAcpiTableInfo (
- OUT UNIVERSAL_PAYLOAD_ACPI_TABLE *AcpiTableHob
+ OUT UNIVERSAL_PAYLOAD_ACPI_TABLE *AcpiTableHob
)
{
- EFI_STATUS Status;
- VOID *MemTable;
- UINT32 MemTableSize;
+ EFI_STATUS Status;
+ VOID *MemTable;
+ UINT32 MemTableSize;
Status = ParseCbMemTable (SIGNATURE_32 ('I', 'P', 'C', 'A'), &MemTable, &MemTableSize);
if (EFI_ERROR (Status)) {
return EFI_NOT_FOUND;
}
- AcpiTableHob->Rsdp = (UINT64) (UINTN)MemTable;
+
+ AcpiTableHob->Rsdp = (UINT64)(UINTN)MemTable;
return RETURN_SUCCESS;
}
-
/**
Find the serial port information
@@ -479,10 +485,10 @@ ParseAcpiTableInfo ( RETURN_STATUS
EFIAPI
ParseSerialInfo (
- OUT SERIAL_PORT_INFO *SerialPortInfo
+ OUT SERIAL_PORT_INFO *SerialPortInfo
)
{
- struct cb_serial *CbSerial;
+ struct cb_serial *CbSerial;
CbSerial = FindCbTag (CB_TAG_SERIAL);
if (CbSerial == NULL) {
@@ -511,7 +517,7 @@ ParseSerialInfo ( RETURN_STATUS
EFIAPI
ParseGfxInfo (
- OUT EFI_PEI_GRAPHICS_INFO_HOB *GfxInfo
+ OUT EFI_PEI_GRAPHICS_INFO_HOB *GfxInfo
)
{
struct cb_framebuffer *CbFbRec;
@@ -542,7 +548,7 @@ ParseGfxInfo ( DEBUG ((DEBUG_INFO, "reserved_mask_size: 0x%x\n", CbFbRec->reserved_mask_size));
DEBUG ((DEBUG_INFO, "reserved_mask_pos: 0x%x\n", CbFbRec->reserved_mask_pos));
- GfxMode = &GfxInfo->GraphicsMode;
+ GfxMode = &GfxInfo->GraphicsMode;
GfxMode->Version = 0;
GfxMode->HorizontalResolution = CbFbRec->x_resolution;
GfxMode->VerticalResolution = CbFbRec->y_resolution;
@@ -550,8 +556,9 @@ ParseGfxInfo ( if ((CbFbRec->red_mask_pos == 0) && (CbFbRec->green_mask_pos == 8) && (CbFbRec->blue_mask_pos == 16)) {
GfxMode->PixelFormat = PixelRedGreenBlueReserved8BitPerColor;
} else if ((CbFbRec->blue_mask_pos == 0) && (CbFbRec->green_mask_pos == 8) && (CbFbRec->red_mask_pos == 16)) {
- GfxMode->PixelFormat = PixelBlueGreenRedReserved8BitPerColor;
+ GfxMode->PixelFormat = PixelBlueGreenRedReserved8BitPerColor;
}
+
GfxMode->PixelInformation.RedMask = ((1 << CbFbRec->red_mask_size) - 1) << CbFbRec->red_mask_pos;
GfxMode->PixelInformation.GreenMask = ((1 << CbFbRec->green_mask_size) - 1) << CbFbRec->green_mask_pos;
GfxMode->PixelInformation.BlueMask = ((1 << CbFbRec->blue_mask_size) - 1) << CbFbRec->blue_mask_pos;
@@ -575,7 +582,7 @@ ParseGfxInfo ( RETURN_STATUS
EFIAPI
ParseGfxDeviceInfo (
- OUT EFI_PEI_GRAPHICS_DEVICE_INFO_HOB *GfxDeviceInfo
+ OUT EFI_PEI_GRAPHICS_DEVICE_INFO_HOB *GfxDeviceInfo
)
{
return RETURN_NOT_FOUND;
diff --git a/UefiPayloadPkg/Library/DxeHobLib/HobLib.c b/UefiPayloadPkg/Library/DxeHobLib/HobLib.c index 6787f65e18..a08cda79e9 100644 --- a/UefiPayloadPkg/Library/DxeHobLib/HobLib.c +++ b/UefiPayloadPkg/Library/DxeHobLib/HobLib.c @@ -59,15 +59,15 @@ GetHobList ( VOID *
EFIAPI
GetNextHob (
- IN UINT16 Type,
- IN CONST VOID *HobStart
+ IN UINT16 Type,
+ IN CONST VOID *HobStart
)
{
EFI_PEI_HOB_POINTERS Hob;
ASSERT (HobStart != NULL);
- Hob.Raw = (UINT8 *) HobStart;
+ Hob.Raw = (UINT8 *)HobStart;
//
// Parse the HOB list until end of list or matching type is found.
//
@@ -75,8 +75,10 @@ GetNextHob ( if (Hob.Header->HobType == Type) {
return Hob.Raw;
}
+
Hob.Raw = GET_NEXT_HOB (Hob);
}
+
return NULL;
}
@@ -96,10 +98,10 @@ GetNextHob ( VOID *
EFIAPI
GetFirstHob (
- IN UINT16 Type
+ IN UINT16 Type
)
{
- VOID *HobList;
+ VOID *HobList;
HobList = GetHobList ();
return GetNextHob (Type, HobList);
@@ -130,19 +132,21 @@ GetFirstHob ( VOID *
EFIAPI
GetNextGuidHob (
- IN CONST EFI_GUID *Guid,
- IN CONST VOID *HobStart
+ IN CONST EFI_GUID *Guid,
+ IN CONST VOID *HobStart
)
{
EFI_PEI_HOB_POINTERS GuidHob;
- GuidHob.Raw = (UINT8 *) HobStart;
+ GuidHob.Raw = (UINT8 *)HobStart;
while ((GuidHob.Raw = GetNextHob (EFI_HOB_TYPE_GUID_EXTENSION, GuidHob.Raw)) != NULL) {
if (CompareGuid (Guid, &GuidHob.Guid->Name)) {
break;
}
+
GuidHob.Raw = GET_NEXT_HOB (GuidHob);
}
+
return GuidHob.Raw;
}
@@ -167,10 +171,10 @@ GetNextGuidHob ( VOID *
EFIAPI
GetFirstGuidHob (
- IN CONST EFI_GUID *Guid
+ IN CONST EFI_GUID *Guid
)
{
- VOID *HobList;
+ VOID *HobList;
HobList = GetHobList ();
return GetNextGuidHob (Guid, HobList);
@@ -195,11 +199,11 @@ GetBootModeHob ( VOID
)
{
- EFI_HOB_HANDOFF_INFO_TABLE *HandOffHob;
+ EFI_HOB_HANDOFF_INFO_TABLE *HandOffHob;
- HandOffHob = (EFI_HOB_HANDOFF_INFO_TABLE *) GetHobList ();
+ HandOffHob = (EFI_HOB_HANDOFF_INFO_TABLE *)GetHobList ();
- return HandOffHob->BootMode;
+ return HandOffHob->BootMode;
}
/**
@@ -221,10 +225,10 @@ GetBootModeHob ( VOID
EFIAPI
BuildModuleHob (
- IN CONST EFI_GUID *ModuleName,
- IN EFI_PHYSICAL_ADDRESS MemoryAllocationModule,
- IN UINT64 ModuleLength,
- IN EFI_PHYSICAL_ADDRESS EntryPoint
+ IN CONST EFI_GUID *ModuleName,
+ IN EFI_PHYSICAL_ADDRESS MemoryAllocationModule,
+ IN UINT64 ModuleLength,
+ IN EFI_PHYSICAL_ADDRESS EntryPoint
)
{
//
@@ -320,8 +324,8 @@ BuildResourceDescriptorHob ( VOID *
EFIAPI
BuildGuidHob (
- IN CONST EFI_GUID *Guid,
- IN UINTN DataLength
+ IN CONST EFI_GUID *Guid,
+ IN UINTN DataLength
)
{
//
@@ -359,9 +363,9 @@ BuildGuidHob ( VOID *
EFIAPI
BuildGuidDataHob (
- IN CONST EFI_GUID *Guid,
- IN VOID *Data,
- IN UINTN DataLength
+ IN CONST EFI_GUID *Guid,
+ IN VOID *Data,
+ IN UINTN DataLength
)
{
//
@@ -388,8 +392,8 @@ BuildGuidDataHob ( VOID
EFIAPI
BuildFvHob (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
)
{
//
@@ -417,10 +421,10 @@ BuildFvHob ( VOID
EFIAPI
BuildFv2Hob (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length,
- IN CONST EFI_GUID *FvName,
- IN CONST EFI_GUID *FileName
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN CONST EFI_GUID *FvName,
+ IN CONST EFI_GUID *FileName
)
{
ASSERT (FALSE);
@@ -450,12 +454,12 @@ BuildFv2Hob ( VOID
EFIAPI
BuildFv3Hob (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length,
- IN UINT32 AuthenticationStatus,
- IN BOOLEAN ExtractedFv,
- IN CONST EFI_GUID *FvName OPTIONAL,
- IN CONST EFI_GUID *FileName OPTIONAL
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN UINT32 AuthenticationStatus,
+ IN BOOLEAN ExtractedFv,
+ IN CONST EFI_GUID *FvName OPTIONAL,
+ IN CONST EFI_GUID *FileName OPTIONAL
)
{
ASSERT (FALSE);
@@ -478,8 +482,8 @@ BuildFv3Hob ( VOID
EFIAPI
BuildCvHob (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
)
{
//
@@ -504,8 +508,8 @@ BuildCvHob ( VOID
EFIAPI
BuildCpuHob (
- IN UINT8 SizeOfMemorySpace,
- IN UINT8 SizeOfIoSpace
+ IN UINT8 SizeOfMemorySpace,
+ IN UINT8 SizeOfIoSpace
)
{
//
@@ -530,8 +534,8 @@ BuildCpuHob ( VOID
EFIAPI
BuildStackHob (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
)
{
//
@@ -557,9 +561,9 @@ BuildStackHob ( VOID
EFIAPI
BuildBspStoreHob (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length,
- IN EFI_MEMORY_TYPE MemoryType
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN EFI_MEMORY_TYPE MemoryType
)
{
//
@@ -585,9 +589,9 @@ BuildBspStoreHob ( VOID
EFIAPI
BuildMemoryAllocationHob (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length,
- IN EFI_MEMORY_TYPE MemoryType
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN EFI_MEMORY_TYPE MemoryType
)
{
//
diff --git a/UefiPayloadPkg/Library/DxeHobListLib/DxeHobListLib.c b/UefiPayloadPkg/Library/DxeHobListLib/DxeHobListLib.c index 8bb31b3f9c..839aa7270b 100644 --- a/UefiPayloadPkg/Library/DxeHobListLib/DxeHobListLib.c +++ b/UefiPayloadPkg/Library/DxeHobListLib/DxeHobListLib.c @@ -7,7 +7,6 @@ **/
-
#include <Uefi.h>
VOID *gHobList = NULL;
@@ -33,10 +32,10 @@ LocalCompareGuid ( UINT64 *Left;
UINT64 *Right;
- Left = (UINT64 *) Guid1;
- Right = (UINT64 *) Guid2;
+ Left = (UINT64 *)Guid1;
+ Right = (UINT64 *)Guid2;
- return (BOOLEAN) (Left[0] == Right[0] && Left[1] == Right[1]);
+ return (BOOLEAN)(Left[0] == Right[0] && Left[1] == Right[1]);
}
/**
@@ -53,7 +52,7 @@ DxeHobListLibConstructor ( IN EFI_SYSTEM_TABLE *SystemTable
)
{
- UINTN Index;
+ UINTN Index;
for (Index = 0; Index < SystemTable->NumberOfTableEntries; Index++) {
if (LocalCompareGuid (&gEfiHobListGuid, &SystemTable->ConfigurationTable[Index].VendorGuid)) {
diff --git a/UefiPayloadPkg/Library/DxeHobListLibNull/DxeHobListLibNull.c b/UefiPayloadPkg/Library/DxeHobListLibNull/DxeHobListLibNull.c index 6c69f9879e..928abf97d1 100644 --- a/UefiPayloadPkg/Library/DxeHobListLibNull/DxeHobListLibNull.c +++ b/UefiPayloadPkg/Library/DxeHobListLibNull/DxeHobListLibNull.c @@ -7,7 +7,6 @@ **/
-
#include <Uefi.h>
/**
diff --git a/UefiPayloadPkg/Library/FlashDeviceLib/FlashDeviceLib.c b/UefiPayloadPkg/Library/FlashDeviceLib/FlashDeviceLib.c index 065841bc93..5a27043285 100644 --- a/UefiPayloadPkg/Library/FlashDeviceLib/FlashDeviceLib.c +++ b/UefiPayloadPkg/Library/FlashDeviceLib/FlashDeviceLib.c @@ -27,7 +27,6 @@ LibFvbFlashDeviceInit ( return SpiConstructor ();
}
-
/**
Read NumBytes bytes of data from the address specified by
PAddress into Buffer.
@@ -44,15 +43,15 @@ LibFvbFlashDeviceInit ( EFI_STATUS
EFIAPI
LibFvbFlashDeviceRead (
- IN UINTN PAddress,
- IN OUT UINTN *NumBytes,
- OUT UINT8 *Buffer
+ IN UINTN PAddress,
+ IN OUT UINTN *NumBytes,
+ OUT UINT8 *Buffer
)
{
- EFI_STATUS Status;
- UINT32 ByteCount;
- UINT32 RgnSize;
- UINT32 AddrOffset;
+ EFI_STATUS Status;
+ UINT32 ByteCount;
+ UINT32 RgnSize;
+ UINT32 AddrOffset;
Status = SpiGetRegionAddress (FlashRegionBios, NULL, &RgnSize);
if (EFI_ERROR (Status)) {
@@ -66,7 +65,6 @@ LibFvbFlashDeviceRead ( return SpiFlashRead (FlashRegionBios, AddrOffset, ByteCount, Buffer);
}
-
/**
Write NumBytes bytes of data from Buffer to the address specified by
PAddresss.
@@ -83,15 +81,15 @@ LibFvbFlashDeviceRead ( EFI_STATUS
EFIAPI
LibFvbFlashDeviceWrite (
- IN UINTN PAddress,
- IN OUT UINTN *NumBytes,
- IN UINT8 *Buffer
+ IN UINTN PAddress,
+ IN OUT UINTN *NumBytes,
+ IN UINT8 *Buffer
)
{
- EFI_STATUS Status;
- UINT32 ByteCount;
- UINT32 RgnSize;
- UINT32 AddrOffset;
+ EFI_STATUS Status;
+ UINT32 ByteCount;
+ UINT32 RgnSize;
+ UINT32 AddrOffset;
Status = SpiGetRegionAddress (FlashRegionBios, NULL, &RgnSize);
if (EFI_ERROR (Status)) {
@@ -105,7 +103,6 @@ LibFvbFlashDeviceWrite ( return SpiFlashWrite (FlashRegionBios, AddrOffset, ByteCount, Buffer);
}
-
/**
Erase the block starting at PAddress.
@@ -121,13 +118,13 @@ LibFvbFlashDeviceWrite ( EFI_STATUS
EFIAPI
LibFvbFlashDeviceBlockErase (
- IN UINTN PAddress,
- IN UINTN LbaLength
+ IN UINTN PAddress,
+ IN UINTN LbaLength
)
{
- EFI_STATUS Status;
- UINT32 RgnSize;
- UINT32 AddrOffset;
+ EFI_STATUS Status;
+ UINT32 RgnSize;
+ UINT32 AddrOffset;
Status = SpiGetRegionAddress (FlashRegionBios, NULL, &RgnSize);
if (EFI_ERROR (Status)) {
@@ -140,7 +137,6 @@ LibFvbFlashDeviceBlockErase ( return SpiFlashErase (FlashRegionBios, AddrOffset, (UINT32)LbaLength);
}
-
/**
Lock or unlock the block starting at PAddress.
@@ -155,11 +151,10 @@ LibFvbFlashDeviceBlockErase ( EFI_STATUS
EFIAPI
LibFvbFlashDeviceBlockLock (
- IN UINTN PAddress,
- IN UINTN LbaLength,
- IN BOOLEAN Lock
+ IN UINTN PAddress,
+ IN UINTN LbaLength,
+ IN BOOLEAN Lock
)
{
return EFI_SUCCESS;
}
-
diff --git a/UefiPayloadPkg/Library/PayloadEntryHobLib/Hob.c b/UefiPayloadPkg/Library/PayloadEntryHobLib/Hob.c index 6853f2e55f..2c3acbbc19 100644 --- a/UefiPayloadPkg/Library/PayloadEntryHobLib/Hob.c +++ b/UefiPayloadPkg/Library/PayloadEntryHobLib/Hob.c @@ -15,7 +15,7 @@ #include <Library/HobLib.h>
#include <Library/PcdLib.h>
-VOID *mHobList;
+VOID *mHobList;
/**
Returns the pointer to the HOB list.
@@ -35,7 +35,6 @@ GetHobList ( return mHobList;
}
-
/**
Build a Handoff Information Table HOB
@@ -51,13 +50,13 @@ GetHobList ( @return The pointer to the handoff HOB table.
**/
-EFI_HOB_HANDOFF_INFO_TABLE*
+EFI_HOB_HANDOFF_INFO_TABLE *
EFIAPI
HobConstructor (
- IN VOID *EfiMemoryBottom,
- IN VOID *EfiMemoryTop,
- IN VOID *EfiFreeMemoryBottom,
- IN VOID *EfiFreeMemoryTop
+ IN VOID *EfiMemoryBottom,
+ IN VOID *EfiMemoryTop,
+ IN VOID *EfiFreeMemoryBottom,
+ IN VOID *EfiFreeMemoryTop
)
{
EFI_HOB_HANDOFF_INFO_TABLE *Hob;
@@ -66,22 +65,22 @@ HobConstructor ( Hob = EfiFreeMemoryBottom;
HobEnd = (EFI_HOB_GENERIC_HEADER *)(Hob+1);
- Hob->Header.HobType = EFI_HOB_TYPE_HANDOFF;
- Hob->Header.HobLength = sizeof(EFI_HOB_HANDOFF_INFO_TABLE);
- Hob->Header.Reserved = 0;
+ Hob->Header.HobType = EFI_HOB_TYPE_HANDOFF;
+ Hob->Header.HobLength = sizeof (EFI_HOB_HANDOFF_INFO_TABLE);
+ Hob->Header.Reserved = 0;
- HobEnd->HobType = EFI_HOB_TYPE_END_OF_HOB_LIST;
- HobEnd->HobLength = sizeof(EFI_HOB_GENERIC_HEADER);
- HobEnd->Reserved = 0;
+ HobEnd->HobType = EFI_HOB_TYPE_END_OF_HOB_LIST;
+ HobEnd->HobLength = sizeof (EFI_HOB_GENERIC_HEADER);
+ HobEnd->Reserved = 0;
- Hob->Version = EFI_HOB_HANDOFF_TABLE_VERSION;
- Hob->BootMode = BOOT_WITH_FULL_CONFIGURATION;
+ Hob->Version = EFI_HOB_HANDOFF_TABLE_VERSION;
+ Hob->BootMode = BOOT_WITH_FULL_CONFIGURATION;
- Hob->EfiMemoryTop = (EFI_PHYSICAL_ADDRESS) (UINTN) EfiMemoryTop;
- Hob->EfiMemoryBottom = (EFI_PHYSICAL_ADDRESS) (UINTN) EfiMemoryBottom;
- Hob->EfiFreeMemoryTop = (EFI_PHYSICAL_ADDRESS) (UINTN) EfiFreeMemoryTop;
- Hob->EfiFreeMemoryBottom = (EFI_PHYSICAL_ADDRESS) (UINTN) (HobEnd+1);
- Hob->EfiEndOfHobList = (EFI_PHYSICAL_ADDRESS) (UINTN) HobEnd;
+ Hob->EfiMemoryTop = (EFI_PHYSICAL_ADDRESS)(UINTN)EfiMemoryTop;
+ Hob->EfiMemoryBottom = (EFI_PHYSICAL_ADDRESS)(UINTN)EfiMemoryBottom;
+ Hob->EfiFreeMemoryTop = (EFI_PHYSICAL_ADDRESS)(UINTN)EfiFreeMemoryTop;
+ Hob->EfiFreeMemoryBottom = (EFI_PHYSICAL_ADDRESS)(UINTN)(HobEnd+1);
+ Hob->EfiEndOfHobList = (EFI_PHYSICAL_ADDRESS)(UINTN)HobEnd;
mHobList = Hob;
return Hob;
@@ -100,8 +99,8 @@ HobConstructor ( VOID *
EFIAPI
CreateHob (
- IN UINT16 HobType,
- IN UINT16 HobLength
+ IN UINT16 HobType,
+ IN UINT16 HobLength
)
{
EFI_HOB_HANDOFF_INFO_TABLE *HandOffHob;
@@ -116,22 +115,22 @@ CreateHob ( FreeMemory = HandOffHob->EfiFreeMemoryTop - HandOffHob->EfiFreeMemoryBottom;
if (FreeMemory < HobLength) {
- return NULL;
+ return NULL;
}
- Hob = (VOID*) (UINTN) HandOffHob->EfiEndOfHobList;
- ((EFI_HOB_GENERIC_HEADER*) Hob)->HobType = HobType;
- ((EFI_HOB_GENERIC_HEADER*) Hob)->HobLength = HobLength;
- ((EFI_HOB_GENERIC_HEADER*) Hob)->Reserved = 0;
+ Hob = (VOID *)(UINTN)HandOffHob->EfiEndOfHobList;
+ ((EFI_HOB_GENERIC_HEADER *)Hob)->HobType = HobType;
+ ((EFI_HOB_GENERIC_HEADER *)Hob)->HobLength = HobLength;
+ ((EFI_HOB_GENERIC_HEADER *)Hob)->Reserved = 0;
- HobEnd = (EFI_HOB_GENERIC_HEADER*) ((UINTN)Hob + HobLength);
- HandOffHob->EfiEndOfHobList = (EFI_PHYSICAL_ADDRESS) (UINTN) HobEnd;
+ HobEnd = (EFI_HOB_GENERIC_HEADER *)((UINTN)Hob + HobLength);
+ HandOffHob->EfiEndOfHobList = (EFI_PHYSICAL_ADDRESS)(UINTN)HobEnd;
HobEnd->HobType = EFI_HOB_TYPE_END_OF_HOB_LIST;
- HobEnd->HobLength = sizeof(EFI_HOB_GENERIC_HEADER);
+ HobEnd->HobLength = sizeof (EFI_HOB_GENERIC_HEADER);
HobEnd->Reserved = 0;
HobEnd++;
- HandOffHob->EfiFreeMemoryBottom = (EFI_PHYSICAL_ADDRESS) (UINTN) HobEnd;
+ HandOffHob->EfiFreeMemoryBottom = (EFI_PHYSICAL_ADDRESS)(UINTN)HobEnd;
return Hob;
}
@@ -160,7 +159,7 @@ BuildResourceDescriptorHob ( EFI_HOB_RESOURCE_DESCRIPTOR *Hob;
Hob = CreateHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, sizeof (EFI_HOB_RESOURCE_DESCRIPTOR));
- ASSERT(Hob != NULL);
+ ASSERT (Hob != NULL);
Hob->ResourceType = ResourceType;
Hob->ResourceAttribute = ResourceAttribute;
@@ -187,15 +186,15 @@ BuildResourceDescriptorHob ( VOID *
EFIAPI
GetNextHob (
- IN UINT16 Type,
- IN CONST VOID *HobStart
+ IN UINT16 Type,
+ IN CONST VOID *HobStart
)
{
EFI_PEI_HOB_POINTERS Hob;
ASSERT (HobStart != NULL);
- Hob.Raw = (UINT8 *) HobStart;
+ Hob.Raw = (UINT8 *)HobStart;
//
// Parse the HOB list until end of list or matching type is found.
//
@@ -203,13 +202,13 @@ GetNextHob ( if (Hob.Header->HobType == Type) {
return Hob.Raw;
}
+
Hob.Raw = GET_NEXT_HOB (Hob);
}
+
return NULL;
}
-
-
/**
Returns the first instance of a HOB type among the whole HOB list.
@@ -224,16 +223,15 @@ GetNextHob ( VOID *
EFIAPI
GetFirstHob (
- IN UINT16 Type
+ IN UINT16 Type
)
{
- VOID *HobList;
+ VOID *HobList;
HobList = GetHobList ();
return GetNextHob (Type, HobList);
}
-
/**
This function searches the first instance of a HOB from the starting HOB pointer.
Such HOB should satisfy two conditions:
@@ -256,23 +254,24 @@ GetFirstHob ( VOID *
EFIAPI
GetNextGuidHob (
- IN CONST EFI_GUID *Guid,
- IN CONST VOID *HobStart
+ IN CONST EFI_GUID *Guid,
+ IN CONST VOID *HobStart
)
{
EFI_PEI_HOB_POINTERS GuidHob;
- GuidHob.Raw = (UINT8 *) HobStart;
+ GuidHob.Raw = (UINT8 *)HobStart;
while ((GuidHob.Raw = GetNextHob (EFI_HOB_TYPE_GUID_EXTENSION, GuidHob.Raw)) != NULL) {
if (CompareGuid (Guid, &GuidHob.Guid->Name)) {
break;
}
+
GuidHob.Raw = GET_NEXT_HOB (GuidHob);
}
+
return GuidHob.Raw;
}
-
/**
This function searches the first instance of a HOB among the whole HOB list.
Such HOB should satisfy two conditions:
@@ -290,18 +289,15 @@ GetNextGuidHob ( VOID *
EFIAPI
GetFirstGuidHob (
- IN CONST EFI_GUID *Guid
+ IN CONST EFI_GUID *Guid
)
{
- VOID *HobList;
+ VOID *HobList;
HobList = GetHobList ();
return GetNextGuidHob (Guid, HobList);
}
-
-
-
/**
Builds a HOB for a loaded PE32 module.
@@ -320,16 +316,18 @@ GetFirstGuidHob ( VOID
EFIAPI
BuildModuleHob (
- IN CONST EFI_GUID *ModuleName,
- IN EFI_PHYSICAL_ADDRESS MemoryAllocationModule,
- IN UINT64 ModuleLength,
- IN EFI_PHYSICAL_ADDRESS EntryPoint
+ IN CONST EFI_GUID *ModuleName,
+ IN EFI_PHYSICAL_ADDRESS MemoryAllocationModule,
+ IN UINT64 ModuleLength,
+ IN EFI_PHYSICAL_ADDRESS EntryPoint
)
{
EFI_HOB_MEMORY_ALLOCATION_MODULE *Hob;
- ASSERT (((MemoryAllocationModule & (EFI_PAGE_SIZE - 1)) == 0) &&
- ((ModuleLength & (EFI_PAGE_SIZE - 1)) == 0));
+ ASSERT (
+ ((MemoryAllocationModule & (EFI_PAGE_SIZE - 1)) == 0) &&
+ ((ModuleLength & (EFI_PAGE_SIZE - 1)) == 0)
+ );
Hob = CreateHob (EFI_HOB_TYPE_MEMORY_ALLOCATION, sizeof (EFI_HOB_MEMORY_ALLOCATION_MODULE));
@@ -368,23 +366,22 @@ BuildModuleHob ( VOID *
EFIAPI
BuildGuidHob (
- IN CONST EFI_GUID *Guid,
- IN UINTN DataLength
+ IN CONST EFI_GUID *Guid,
+ IN UINTN DataLength
)
{
- EFI_HOB_GUID_TYPE *Hob;
+ EFI_HOB_GUID_TYPE *Hob;
//
// Make sure that data length is not too long.
//
ASSERT (DataLength <= (0xffff - sizeof (EFI_HOB_GUID_TYPE)));
- Hob = CreateHob (EFI_HOB_TYPE_GUID_EXTENSION, (UINT16) (sizeof (EFI_HOB_GUID_TYPE) + DataLength));
+ Hob = CreateHob (EFI_HOB_TYPE_GUID_EXTENSION, (UINT16)(sizeof (EFI_HOB_GUID_TYPE) + DataLength));
CopyGuid (&Hob->Name, Guid);
return Hob + 1;
}
-
/**
Copies a data buffer to a newly-built HOB.
@@ -408,9 +405,9 @@ BuildGuidHob ( VOID *
EFIAPI
BuildGuidDataHob (
- IN CONST EFI_GUID *Guid,
- IN VOID *Data,
- IN UINTN DataLength
+ IN CONST EFI_GUID *Guid,
+ IN VOID *Data,
+ IN UINTN DataLength
)
{
VOID *HobData;
@@ -422,7 +419,6 @@ BuildGuidDataHob ( return CopyMem (HobData, Data, DataLength);
}
-
/**
Builds a Firmware Volume HOB.
@@ -438,8 +434,8 @@ BuildGuidDataHob ( VOID
EFIAPI
BuildFvHob (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
)
{
EFI_HOB_FIRMWARE_VOLUME *Hob;
@@ -450,7 +446,6 @@ BuildFvHob ( Hob->Length = Length;
}
-
/**
Builds a EFI_HOB_TYPE_FV2 HOB.
@@ -468,10 +463,10 @@ BuildFvHob ( VOID
EFIAPI
BuildFv2Hob (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length,
- IN CONST EFI_GUID *FvName,
- IN CONST EFI_GUID *FileName
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN CONST EFI_GUID *FvName,
+ IN CONST EFI_GUID *FileName
)
{
EFI_HOB_FIRMWARE_VOLUME2 *Hob;
@@ -507,12 +502,12 @@ BuildFv2Hob ( VOID
EFIAPI
BuildFv3Hob (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length,
- IN UINT32 AuthenticationStatus,
- IN BOOLEAN ExtractedFv,
- IN CONST EFI_GUID *FvName OPTIONAL,
- IN CONST EFI_GUID *FileName OPTIONAL
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN UINT32 AuthenticationStatus,
+ IN BOOLEAN ExtractedFv,
+ IN CONST EFI_GUID *FvName OPTIONAL,
+ IN CONST EFI_GUID *FileName OPTIONAL
)
{
EFI_HOB_FIRMWARE_VOLUME3 *Hob;
@@ -529,7 +524,6 @@ BuildFv3Hob ( }
}
-
/**
Builds a HOB for the CPU.
@@ -545,8 +539,8 @@ BuildFv3Hob ( VOID
EFIAPI
BuildCpuHob (
- IN UINT8 SizeOfMemorySpace,
- IN UINT8 SizeOfIoSpace
+ IN UINT8 SizeOfMemorySpace,
+ IN UINT8 SizeOfIoSpace
)
{
EFI_HOB_CPU *Hob;
@@ -562,7 +556,6 @@ BuildCpuHob ( ZeroMem (Hob->Reserved, sizeof (Hob->Reserved));
}
-
/**
Builds a HOB for the Stack.
@@ -578,14 +571,16 @@ BuildCpuHob ( VOID
EFIAPI
BuildStackHob (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
)
{
EFI_HOB_MEMORY_ALLOCATION_STACK *Hob;
- ASSERT (((BaseAddress & (EFI_PAGE_SIZE - 1)) == 0) &&
- ((Length & (EFI_PAGE_SIZE - 1)) == 0));
+ ASSERT (
+ ((BaseAddress & (EFI_PAGE_SIZE - 1)) == 0) &&
+ ((Length & (EFI_PAGE_SIZE - 1)) == 0)
+ );
Hob = CreateHob (EFI_HOB_TYPE_MEMORY_ALLOCATION, sizeof (EFI_HOB_MEMORY_ALLOCATION_STACK));
@@ -600,7 +595,6 @@ BuildStackHob ( ZeroMem (Hob->AllocDescriptor.Reserved, sizeof (Hob->AllocDescriptor.Reserved));
}
-
/**
Update the Stack Hob if the stack has been moved
@@ -611,11 +605,11 @@ BuildStackHob ( VOID
EFIAPI
UpdateStackHob (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
)
{
- EFI_PEI_HOB_POINTERS Hob;
+ EFI_PEI_HOB_POINTERS Hob;
Hob.Raw = GetHobList ();
while ((Hob.Raw = GetNextHob (EFI_HOB_TYPE_MEMORY_ALLOCATION, Hob.Raw)) != NULL) {
@@ -633,15 +627,14 @@ UpdateStackHob ( // Update the BSP Stack Hob to reflect the new stack info.
//
Hob.MemoryAllocationStack->AllocDescriptor.MemoryBaseAddress = BaseAddress;
- Hob.MemoryAllocationStack->AllocDescriptor.MemoryLength = Length;
+ Hob.MemoryAllocationStack->AllocDescriptor.MemoryLength = Length;
break;
}
+
Hob.Raw = GET_NEXT_HOB (Hob);
}
}
-
-
/**
Builds a HOB for the memory allocation.
@@ -658,15 +651,17 @@ UpdateStackHob ( VOID
EFIAPI
BuildMemoryAllocationHob (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length,
- IN EFI_MEMORY_TYPE MemoryType
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN EFI_MEMORY_TYPE MemoryType
)
{
EFI_HOB_MEMORY_ALLOCATION *Hob;
- ASSERT (((BaseAddress & (EFI_PAGE_SIZE - 1)) == 0) &&
- ((Length & (EFI_PAGE_SIZE - 1)) == 0));
+ ASSERT (
+ ((BaseAddress & (EFI_PAGE_SIZE - 1)) == 0) &&
+ ((Length & (EFI_PAGE_SIZE - 1)) == 0)
+ );
Hob = CreateHob (EFI_HOB_TYPE_MEMORY_ALLOCATION, sizeof (EFI_HOB_MEMORY_ALLOCATION));
diff --git a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridge.h b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridge.h index 2848da5ce6..431ccab9b9 100644 --- a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridge.h +++ b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridge.h @@ -14,8 +14,8 @@ #include <UniversalPayload/PciRootBridges.h>
typedef struct {
- ACPI_HID_DEVICE_PATH AcpiDevicePath;
- EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
+ ACPI_HID_DEVICE_PATH AcpiDevicePath;
+ EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
} CB_PCI_ROOT_BRIDGE_DEVICE_PATH;
/**
@@ -27,8 +27,8 @@ typedef struct { **/
PCI_ROOT_BRIDGE *
ScanForRootBridges (
- OUT UINTN *NumberOfRootBridges
-);
+ OUT UINTN *NumberOfRootBridges
+ );
/**
Scan for all root bridges from Universal Payload PciRootBridgeInfoHob
@@ -43,7 +43,7 @@ PCI_ROOT_BRIDGE * RetrieveRootBridgeInfoFromHob (
IN UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES *PciRootBridgeInfo,
OUT UINTN *NumberOfRootBridges
-);
+ );
/**
Initialize a PCI_ROOT_BRIDGE structure.
@@ -88,18 +88,18 @@ RetrieveRootBridgeInfoFromHob ( **/
EFI_STATUS
InitRootBridge (
- IN UINT64 Supports,
- IN UINT64 Attributes,
- IN UINT64 AllocAttributes,
- IN UINT8 RootBusNumber,
- IN UINT8 MaxSubBusNumber,
- IN PCI_ROOT_BRIDGE_APERTURE *Io,
- IN PCI_ROOT_BRIDGE_APERTURE *Mem,
- IN PCI_ROOT_BRIDGE_APERTURE *MemAbove4G,
- IN PCI_ROOT_BRIDGE_APERTURE *PMem,
- IN PCI_ROOT_BRIDGE_APERTURE *PMemAbove4G,
- OUT PCI_ROOT_BRIDGE *RootBus
-);
+ IN UINT64 Supports,
+ IN UINT64 Attributes,
+ IN UINT64 AllocAttributes,
+ IN UINT8 RootBusNumber,
+ IN UINT8 MaxSubBusNumber,
+ IN PCI_ROOT_BRIDGE_APERTURE *Io,
+ IN PCI_ROOT_BRIDGE_APERTURE *Mem,
+ IN PCI_ROOT_BRIDGE_APERTURE *MemAbove4G,
+ IN PCI_ROOT_BRIDGE_APERTURE *PMem,
+ IN PCI_ROOT_BRIDGE_APERTURE *PMemAbove4G,
+ OUT PCI_ROOT_BRIDGE *RootBus
+ );
/**
Initialize DevicePath for a PCI_ROOT_BRIDGE.
@@ -110,7 +110,8 @@ InitRootBridge ( **/
EFI_DEVICE_PATH_PROTOCOL *
CreateRootBridgeDevicePath (
- IN UINT32 HID,
- IN UINT32 UID
-);
+ IN UINT32 HID,
+ IN UINT32 UID
+ );
+
#endif
diff --git a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c index 0eddebe229..9847063d3d 100644 --- a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c +++ b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c @@ -25,18 +25,18 @@ STATIC
CONST
-CB_PCI_ROOT_BRIDGE_DEVICE_PATH mRootBridgeDevicePathTemplate = {
+CB_PCI_ROOT_BRIDGE_DEVICE_PATH mRootBridgeDevicePathTemplate = {
{
{
ACPI_DEVICE_PATH,
ACPI_DP,
{
- (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
- (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
+ (UINT8)(sizeof (ACPI_HID_DEVICE_PATH)),
+ (UINT8)((sizeof (ACPI_HID_DEVICE_PATH)) >> 8)
}
},
- EISA_PNP_ID(0x0A03), // HID
- 0 // UID
+ EISA_PNP_ID (0x0A03), // HID
+ 0 // UID
},
{
@@ -92,20 +92,20 @@ CB_PCI_ROOT_BRIDGE_DEVICE_PATH mRootBridgeDevicePathTemplate = { **/
EFI_STATUS
InitRootBridge (
- IN UINT64 Supports,
- IN UINT64 Attributes,
- IN UINT64 AllocAttributes,
- IN UINT8 RootBusNumber,
- IN UINT8 MaxSubBusNumber,
- IN PCI_ROOT_BRIDGE_APERTURE *Io,
- IN PCI_ROOT_BRIDGE_APERTURE *Mem,
- IN PCI_ROOT_BRIDGE_APERTURE *MemAbove4G,
- IN PCI_ROOT_BRIDGE_APERTURE *PMem,
- IN PCI_ROOT_BRIDGE_APERTURE *PMemAbove4G,
- OUT PCI_ROOT_BRIDGE *RootBus
-)
+ IN UINT64 Supports,
+ IN UINT64 Attributes,
+ IN UINT64 AllocAttributes,
+ IN UINT8 RootBusNumber,
+ IN UINT8 MaxSubBusNumber,
+ IN PCI_ROOT_BRIDGE_APERTURE *Io,
+ IN PCI_ROOT_BRIDGE_APERTURE *Mem,
+ IN PCI_ROOT_BRIDGE_APERTURE *MemAbove4G,
+ IN PCI_ROOT_BRIDGE_APERTURE *PMem,
+ IN PCI_ROOT_BRIDGE_APERTURE *PMemAbove4G,
+ OUT PCI_ROOT_BRIDGE *RootBus
+ )
{
- CB_PCI_ROOT_BRIDGE_DEVICE_PATH *DevicePath;
+ CB_PCI_ROOT_BRIDGE_DEVICE_PATH *DevicePath;
//
// Be safe if other fields are added to PCI_ROOT_BRIDGE later.
@@ -120,8 +120,8 @@ InitRootBridge ( RootBus->DmaAbove4G = FALSE;
RootBus->AllocationAttributes = AllocAttributes;
- RootBus->Bus.Base = RootBusNumber;
- RootBus->Bus.Limit = MaxSubBusNumber;
+ RootBus->Bus.Base = RootBusNumber;
+ RootBus->Bus.Limit = MaxSubBusNumber;
CopyMem (&RootBus->Io, Io, sizeof (*Io));
CopyMem (&RootBus->Mem, Mem, sizeof (*Mem));
CopyMem (&RootBus->MemAbove4G, MemAbove4G, sizeof (*MemAbove4G));
@@ -130,18 +130,25 @@ InitRootBridge ( RootBus->NoExtendedConfigSpace = FALSE;
- DevicePath = AllocateCopyPool (sizeof (mRootBridgeDevicePathTemplate),
- &mRootBridgeDevicePathTemplate);
+ DevicePath = AllocateCopyPool (
+ sizeof (mRootBridgeDevicePathTemplate),
+ &mRootBridgeDevicePathTemplate
+ );
if (DevicePath == NULL) {
DEBUG ((DEBUG_ERROR, "%a: %r\n", __FUNCTION__, EFI_OUT_OF_RESOURCES));
return EFI_OUT_OF_RESOURCES;
}
- DevicePath->AcpiDevicePath.UID = RootBusNumber;
- RootBus->DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)DevicePath;
- DEBUG ((DEBUG_INFO,
- "%a: populated root bus %d, with room for %d subordinate bus(es)\n",
- __FUNCTION__, RootBusNumber, MaxSubBusNumber - RootBusNumber));
+ DevicePath->AcpiDevicePath.UID = RootBusNumber;
+ RootBus->DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)DevicePath;
+
+ DEBUG ((
+ DEBUG_INFO,
+ "%a: populated root bus %d, with room for %d subordinate bus(es)\n",
+ __FUNCTION__,
+ RootBusNumber,
+ MaxSubBusNumber - RootBusNumber
+ ));
return EFI_SUCCESS;
}
@@ -154,13 +161,16 @@ InitRootBridge ( **/
EFI_DEVICE_PATH_PROTOCOL *
CreateRootBridgeDevicePath (
- IN UINT32 HID,
- IN UINT32 UID
-)
+ IN UINT32 HID,
+ IN UINT32 UID
+ )
{
- CB_PCI_ROOT_BRIDGE_DEVICE_PATH *DevicePath;
- DevicePath = AllocateCopyPool (sizeof (mRootBridgeDevicePathTemplate),
- &mRootBridgeDevicePathTemplate);
+ CB_PCI_ROOT_BRIDGE_DEVICE_PATH *DevicePath;
+
+ DevicePath = AllocateCopyPool (
+ sizeof (mRootBridgeDevicePathTemplate),
+ &mRootBridgeDevicePathTemplate
+ );
ASSERT (DevicePath != NULL);
DevicePath->AcpiDevicePath.HID = HID;
DevicePath->AcpiDevicePath.UID = UID;
@@ -179,30 +189,32 @@ CreateRootBridgeDevicePath ( PCI_ROOT_BRIDGE *
EFIAPI
PciHostBridgeGetRootBridges (
- UINTN *Count
-)
+ UINTN *Count
+ )
{
UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES *PciRootBridgeInfo;
EFI_HOB_GUID_TYPE *GuidHob;
UNIVERSAL_PAYLOAD_GENERIC_HEADER *GenericHeader;
+
//
// Find Universal Payload PCI Root Bridge Info hob
//
GuidHob = GetFirstGuidHob (&gUniversalPayloadPciRootBridgeInfoGuid);
if (GuidHob != NULL) {
- GenericHeader = (UNIVERSAL_PAYLOAD_GENERIC_HEADER *) GET_GUID_HOB_DATA (GuidHob);
- if ((sizeof(UNIVERSAL_PAYLOAD_GENERIC_HEADER) <= GET_GUID_HOB_DATA_SIZE (GuidHob)) && (GenericHeader->Length <= GET_GUID_HOB_DATA_SIZE (GuidHob))) {
+ GenericHeader = (UNIVERSAL_PAYLOAD_GENERIC_HEADER *)GET_GUID_HOB_DATA (GuidHob);
+ if ((sizeof (UNIVERSAL_PAYLOAD_GENERIC_HEADER) <= GET_GUID_HOB_DATA_SIZE (GuidHob)) && (GenericHeader->Length <= GET_GUID_HOB_DATA_SIZE (GuidHob))) {
if ((GenericHeader->Revision == UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES_REVISION) && (GenericHeader->Length >= sizeof (UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES))) {
//
// UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES structure is used when Revision equals to UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES_REVISION
//
- PciRootBridgeInfo = (UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES *) GET_GUID_HOB_DATA (GuidHob);
- if (PciRootBridgeInfo->Count <= (GET_GUID_HOB_DATA_SIZE (GuidHob) - sizeof(UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES)) / sizeof(UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE)) {
+ PciRootBridgeInfo = (UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES *)GET_GUID_HOB_DATA (GuidHob);
+ if (PciRootBridgeInfo->Count <= (GET_GUID_HOB_DATA_SIZE (GuidHob) - sizeof (UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES)) / sizeof (UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE)) {
return RetrieveRootBridgeInfoFromHob (PciRootBridgeInfo, Count);
}
}
}
}
+
return ScanForRootBridges (Count);
}
@@ -216,13 +228,14 @@ PciHostBridgeGetRootBridges ( VOID
EFIAPI
PciHostBridgeFreeRootBridges (
- PCI_ROOT_BRIDGE *Bridges,
- UINTN Count
-)
+ PCI_ROOT_BRIDGE *Bridges,
+ UINTN Count
+ )
{
- if (Bridges == NULL && Count == 0) {
+ if ((Bridges == NULL) && (Count == 0)) {
return;
}
+
ASSERT (Bridges != NULL && Count > 0);
do {
@@ -233,7 +246,6 @@ PciHostBridgeFreeRootBridges ( FreePool (Bridges);
}
-
/**
Inform the platform that the resource conflict happens.
@@ -251,9 +263,9 @@ PciHostBridgeFreeRootBridges ( VOID
EFIAPI
PciHostBridgeResourceConflict (
- EFI_HANDLE HostBridgeHandle,
- VOID *Configuration
-)
+ EFI_HANDLE HostBridgeHandle,
+ VOID *Configuration
+ )
{
//
// coreboot UEFI Payload does not do PCI enumeration and should not call this
diff --git a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c index eb28d48b3b..bf2d10f4bf 100644 --- a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c +++ b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c @@ -33,12 +33,12 @@ **/
VOID
AdjustRootBridgeResource (
- IN PCI_ROOT_BRIDGE_APERTURE *Io,
- IN PCI_ROOT_BRIDGE_APERTURE *Mem,
- IN PCI_ROOT_BRIDGE_APERTURE *MemAbove4G,
- IN PCI_ROOT_BRIDGE_APERTURE *PMem,
- IN PCI_ROOT_BRIDGE_APERTURE *PMemAbove4G
-)
+ IN PCI_ROOT_BRIDGE_APERTURE *Io,
+ IN PCI_ROOT_BRIDGE_APERTURE *Mem,
+ IN PCI_ROOT_BRIDGE_APERTURE *MemAbove4G,
+ IN PCI_ROOT_BRIDGE_APERTURE *PMem,
+ IN PCI_ROOT_BRIDGE_APERTURE *PMemAbove4G
+ )
{
UINT64 Mask;
@@ -61,22 +61,26 @@ AdjustRootBridgeResource ( if (MemAbove4G->Base < 0x100000000ULL) {
if (MemAbove4G->Base < Mem->Base) {
- Mem->Base = MemAbove4G->Base;
+ Mem->Base = MemAbove4G->Base;
}
+
if (MemAbove4G->Limit > Mem->Limit) {
Mem->Limit = MemAbove4G->Limit;
}
+
MemAbove4G->Base = MAX_UINT64;
MemAbove4G->Limit = 0;
}
if (PMemAbove4G->Base < 0x100000000ULL) {
if (PMemAbove4G->Base < Mem->Base) {
- Mem->Base = PMemAbove4G->Base;
+ Mem->Base = PMemAbove4G->Base;
}
+
if (PMemAbove4G->Limit > Mem->Limit) {
Mem->Limit = PMemAbove4G->Limit;
}
+
PMemAbove4G->Base = MAX_UINT64;
PMemAbove4G->Limit = 0;
}
@@ -84,8 +88,8 @@ AdjustRootBridgeResource ( //
// Align IO resource at 4K boundary
//
- Mask = 0xFFFULL;
- Io->Limit = ((Io->Limit + Mask) & ~Mask) - 1;
+ Mask = 0xFFFULL;
+ Io->Limit = ((Io->Limit + Mask) & ~Mask) - 1;
if (Io->Base != MAX_UINT64) {
Io->Base &= ~Mask;
}
@@ -93,8 +97,8 @@ AdjustRootBridgeResource ( //
// Align MEM resource at 1MB boundary
//
- Mask = 0xFFFFFULL;
- Mem->Limit = ((Mem->Limit + Mask) & ~Mask) - 1;
+ Mask = 0xFFFFFULL;
+ Mem->Limit = ((Mem->Limit + Mask) & ~Mask) - 1;
if (Mem->Base != MAX_UINT64) {
Mem->Base &= ~Mask;
}
@@ -110,12 +114,12 @@ AdjustRootBridgeResource ( STATIC
VOID
PcatPciRootBridgeBarExisted (
- IN UINT64 Address,
- OUT UINT32 *OriginalValue,
- OUT UINT32 *Value
-)
+ IN UINT64 Address,
+ OUT UINT32 *OriginalValue,
+ OUT UINT32 *Value
+ )
{
- UINTN PciAddress;
+ UINTN PciAddress;
PciAddress = (UINTN)Address;
@@ -167,57 +171,61 @@ PcatPciRootBridgeBarExisted ( STATIC
VOID
PcatPciRootBridgeParseBars (
- IN UINT16 Command,
- IN UINTN Bus,
- IN UINTN Device,
- IN UINTN Function,
- IN UINTN BarOffsetBase,
- IN UINTN BarOffsetEnd,
- IN PCI_ROOT_BRIDGE_APERTURE *Io,
- IN PCI_ROOT_BRIDGE_APERTURE *Mem,
- IN PCI_ROOT_BRIDGE_APERTURE *MemAbove4G,
- IN PCI_ROOT_BRIDGE_APERTURE *PMem,
- IN PCI_ROOT_BRIDGE_APERTURE *PMemAbove4G
-
-)
+ IN UINT16 Command,
+ IN UINTN Bus,
+ IN UINTN Device,
+ IN UINTN Function,
+ IN UINTN BarOffsetBase,
+ IN UINTN BarOffsetEnd,
+ IN PCI_ROOT_BRIDGE_APERTURE *Io,
+ IN PCI_ROOT_BRIDGE_APERTURE *Mem,
+ IN PCI_ROOT_BRIDGE_APERTURE *MemAbove4G,
+ IN PCI_ROOT_BRIDGE_APERTURE *PMem,
+ IN PCI_ROOT_BRIDGE_APERTURE *PMemAbove4G
+
+ )
{
- UINT32 OriginalValue;
- UINT32 Value;
- UINT32 OriginalUpperValue;
- UINT32 UpperValue;
- UINT64 Mask;
- UINTN Offset;
- UINTN LowBit;
- UINT64 Base;
- UINT64 Length;
- UINT64 Limit;
- PCI_ROOT_BRIDGE_APERTURE *MemAperture;
+ UINT32 OriginalValue;
+ UINT32 Value;
+ UINT32 OriginalUpperValue;
+ UINT32 UpperValue;
+ UINT64 Mask;
+ UINTN Offset;
+ UINTN LowBit;
+ UINT64 Base;
+ UINT64 Length;
+ UINT64 Limit;
+ PCI_ROOT_BRIDGE_APERTURE *MemAperture;
for (Offset = BarOffsetBase; Offset < BarOffsetEnd; Offset += sizeof (UINT32)) {
PcatPciRootBridgeBarExisted (
PCI_LIB_ADDRESS (Bus, Device, Function, Offset),
- &OriginalValue, &Value
- );
+ &OriginalValue,
+ &Value
+ );
if (Value == 0) {
continue;
}
+
if ((Value & BIT0) == BIT0) {
//
// IO Bar
//
if ((Command & EFI_PCI_COMMAND_IO_SPACE) != 0) {
- Mask = 0xfffffffc;
- Base = OriginalValue & Mask;
+ Mask = 0xfffffffc;
+ Base = OriginalValue & Mask;
Length = ((~(Value & Mask)) & Mask) + 0x04;
if (!(Value & 0xFFFF0000)) {
Length &= 0x0000FFFF;
}
+
Limit = Base + Length - 1;
if ((Base > 0) && (Base < Limit)) {
if (Io->Base > Base) {
Io->Base = Base;
}
+
if (Io->Limit < Limit) {
Io->Limit = Limit;
}
@@ -228,9 +236,8 @@ PcatPciRootBridgeParseBars ( // Mem Bar
//
if ((Command & EFI_PCI_COMMAND_MEMORY_SPACE) != 0) {
-
- Mask = 0xfffffff0;
- Base = OriginalValue & Mask;
+ Mask = 0xfffffff0;
+ Base = OriginalValue & Mask;
Length = Value & Mask;
if ((Value & (BIT1 | BIT2)) == 0) {
@@ -253,10 +260,10 @@ PcatPciRootBridgeParseBars ( PCI_LIB_ADDRESS (Bus, Device, Function, Offset),
&OriginalUpperValue,
&UpperValue
- );
+ );
- Base = Base | LShiftU64 ((UINT64) OriginalUpperValue, 32);
- Length = Length | LShiftU64 ((UINT64) UpperValue, 32);
+ Base = Base | LShiftU64 ((UINT64)OriginalUpperValue, 32);
+ Length = Length | LShiftU64 ((UINT64)UpperValue, 32);
if (Length != 0) {
LowBit = LowBitSet64 (Length);
Length = LShiftU64 (1ULL, LowBit);
@@ -274,6 +281,7 @@ PcatPciRootBridgeParseBars ( if (MemAperture->Base > Base) {
MemAperture->Base = Base;
}
+
if (MemAperture->Limit < Limit) {
MemAperture->Limit = Limit;
}
@@ -292,32 +300,31 @@ PcatPciRootBridgeParseBars ( **/
PCI_ROOT_BRIDGE *
ScanForRootBridges (
- OUT UINTN *NumberOfRootBridges
-)
+ OUT UINTN *NumberOfRootBridges
+ )
{
- UINTN PrimaryBus;
- UINTN SubBus;
- UINT8 Device;
- UINT8 Function;
- UINTN NumberOfDevices;
- UINTN Address;
- PCI_TYPE01 Pci;
- UINT64 Attributes;
- UINT64 Base;
- UINT64 Limit;
- UINT64 Value;
- PCI_ROOT_BRIDGE_APERTURE Io;
- PCI_ROOT_BRIDGE_APERTURE Mem;
- PCI_ROOT_BRIDGE_APERTURE MemAbove4G;
- PCI_ROOT_BRIDGE_APERTURE PMem;
- PCI_ROOT_BRIDGE_APERTURE PMemAbove4G;
- PCI_ROOT_BRIDGE_APERTURE *MemAperture;
- PCI_ROOT_BRIDGE *RootBridges;
- UINTN BarOffsetEnd;
-
+ UINTN PrimaryBus;
+ UINTN SubBus;
+ UINT8 Device;
+ UINT8 Function;
+ UINTN NumberOfDevices;
+ UINTN Address;
+ PCI_TYPE01 Pci;
+ UINT64 Attributes;
+ UINT64 Base;
+ UINT64 Limit;
+ UINT64 Value;
+ PCI_ROOT_BRIDGE_APERTURE Io;
+ PCI_ROOT_BRIDGE_APERTURE Mem;
+ PCI_ROOT_BRIDGE_APERTURE MemAbove4G;
+ PCI_ROOT_BRIDGE_APERTURE PMem;
+ PCI_ROOT_BRIDGE_APERTURE PMemAbove4G;
+ PCI_ROOT_BRIDGE_APERTURE *MemAperture;
+ PCI_ROOT_BRIDGE *RootBridges;
+ UINTN BarOffsetEnd;
*NumberOfRootBridges = 0;
- RootBridges = NULL;
+ RootBridges = NULL;
//
// After scanning all the PCI devices on the PCI root bridge's primary bus,
@@ -325,7 +332,7 @@ ScanForRootBridges ( // root bridge's subordinate bus number + 1.
//
for (PrimaryBus = 0; PrimaryBus <= PCI_MAX_BUS; PrimaryBus = SubBus + 1) {
- SubBus = PrimaryBus;
+ SubBus = PrimaryBus;
Attributes = 0;
ZeroMem (&Io, sizeof (Io));
@@ -338,9 +345,7 @@ ScanForRootBridges ( // Scan all the PCI devices on the primary bus of the PCI root bridge
//
for (Device = 0, NumberOfDevices = 0; Device <= PCI_MAX_DEVICE; Device++) {
-
for (Function = 0; Function <= PCI_MAX_FUNC; Function++) {
-
//
// Compute the PCI configuration address of the PCI device to probe
//
@@ -407,16 +412,18 @@ ScanForRootBridges ( // Get the I/O range that the PPB is decoding
//
Value = Pci.Bridge.IoBase & 0x0f;
- Base = ((UINT32) Pci.Bridge.IoBase & 0xf0) << 8;
- Limit = (((UINT32) Pci.Bridge.IoLimit & 0xf0) << 8) | 0x0fff;
+ Base = ((UINT32)Pci.Bridge.IoBase & 0xf0) << 8;
+ Limit = (((UINT32)Pci.Bridge.IoLimit & 0xf0) << 8) | 0x0fff;
if (Value == BIT0) {
- Base |= ((UINT32) Pci.Bridge.IoBaseUpper16 << 16);
- Limit |= ((UINT32) Pci.Bridge.IoLimitUpper16 << 16);
+ Base |= ((UINT32)Pci.Bridge.IoBaseUpper16 << 16);
+ Limit |= ((UINT32)Pci.Bridge.IoLimitUpper16 << 16);
}
+
if ((Base > 0) && (Base < Limit)) {
if (Io.Base > Base) {
Io.Base = Base;
}
+
if (Io.Limit < Limit) {
Io.Limit = Limit;
}
@@ -425,12 +432,13 @@ ScanForRootBridges ( //
// Get the Memory range that the PPB is decoding
//
- Base = ((UINT32) Pci.Bridge.MemoryBase & 0xfff0) << 16;
- Limit = (((UINT32) Pci.Bridge.MemoryLimit & 0xfff0) << 16) | 0xfffff;
+ Base = ((UINT32)Pci.Bridge.MemoryBase & 0xfff0) << 16;
+ Limit = (((UINT32)Pci.Bridge.MemoryLimit & 0xfff0) << 16) | 0xfffff;
if ((Base > 0) && (Base < Limit)) {
if (Mem.Base > Base) {
Mem.Base = Base;
}
+
if (Mem.Limit < Limit) {
Mem.Limit = Limit;
}
@@ -440,19 +448,21 @@ ScanForRootBridges ( // Get the Prefetchable Memory range that the PPB is decoding
//
Value = Pci.Bridge.PrefetchableMemoryBase & 0x0f;
- Base = ((UINT32) Pci.Bridge.PrefetchableMemoryBase & 0xfff0) << 16;
- Limit = (((UINT32) Pci.Bridge.PrefetchableMemoryLimit & 0xfff0)
+ Base = ((UINT32)Pci.Bridge.PrefetchableMemoryBase & 0xfff0) << 16;
+ Limit = (((UINT32)Pci.Bridge.PrefetchableMemoryLimit & 0xfff0)
<< 16) | 0xfffff;
MemAperture = &PMem;
if (Value == BIT0) {
- Base |= LShiftU64 (Pci.Bridge.PrefetchableBaseUpper32, 32);
- Limit |= LShiftU64 (Pci.Bridge.PrefetchableLimitUpper32, 32);
+ Base |= LShiftU64 (Pci.Bridge.PrefetchableBaseUpper32, 32);
+ Limit |= LShiftU64 (Pci.Bridge.PrefetchableLimitUpper32, 32);
MemAperture = &PMemAbove4G;
}
+
if ((Base > 0) && (Base < Limit)) {
if (MemAperture->Base > Base) {
MemAperture->Base = Base;
}
+
if (MemAperture->Limit < Limit) {
MemAperture->Limit = Limit;
}
@@ -462,18 +472,22 @@ ScanForRootBridges ( // Look at the PPB Configuration for legacy decoding attributes
//
if ((Pci.Bridge.BridgeControl & EFI_PCI_BRIDGE_CONTROL_ISA)
- == EFI_PCI_BRIDGE_CONTROL_ISA) {
+ == EFI_PCI_BRIDGE_CONTROL_ISA)
+ {
Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO;
Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO_16;
Attributes |= EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO;
}
+
if ((Pci.Bridge.BridgeControl & EFI_PCI_BRIDGE_CONTROL_VGA)
- == EFI_PCI_BRIDGE_CONTROL_VGA) {
+ == EFI_PCI_BRIDGE_CONTROL_VGA)
+ {
Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO;
Attributes |= EFI_PCI_ATTRIBUTE_VGA_MEMORY;
Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO;
if ((Pci.Bridge.BridgeControl & EFI_PCI_BRIDGE_CONTROL_VGA_16)
- != 0) {
+ != 0)
+ {
Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;
Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO_16;
}
@@ -498,22 +512,30 @@ ScanForRootBridges ( OFFSET_OF (PCI_TYPE00, Device.Bar),
BarOffsetEnd,
&Io,
- &Mem, &MemAbove4G,
- &PMem, &PMemAbove4G
- );
+ &Mem,
+ &MemAbove4G,
+ &PMem,
+ &PMemAbove4G
+ );
//
// See if the PCI device is an IDE controller
//
- if (IS_CLASS2 (&Pci, PCI_CLASS_MASS_STORAGE,
- PCI_CLASS_MASS_STORAGE_IDE)) {
+ if (IS_CLASS2 (
+ &Pci,
+ PCI_CLASS_MASS_STORAGE,
+ PCI_CLASS_MASS_STORAGE_IDE
+ ))
+ {
if (Pci.Hdr.ClassCode[0] & 0x80) {
Attributes |= EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO;
Attributes |= EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO;
}
+
if (Pci.Hdr.ClassCode[0] & 0x01) {
Attributes |= EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO;
}
+
if (Pci.Hdr.ClassCode[0] & 0x04) {
Attributes |= EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO;
}
@@ -525,7 +547,8 @@ ScanForRootBridges ( //
if (IS_CLASS2 (&Pci, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA) ||
IS_CLASS2 (&Pci, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA)
- ) {
+ )
+ {
Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO;
Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;
Attributes |= EFI_PCI_ATTRIBUTE_VGA_MEMORY;
@@ -538,9 +561,10 @@ ScanForRootBridges ( // or ISA_POSITIVE_DECODE Bridge device
//
if (Pci.Hdr.ClassCode[2] == PCI_CLASS_BRIDGE) {
- if (Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_ISA ||
- Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_EISA ||
- Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_ISA_PDECODE) {
+ if ((Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_ISA) ||
+ (Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_EISA) ||
+ (Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_ISA_PDECODE))
+ {
Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO;
Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO_16;
Attributes |= EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO;
@@ -551,7 +575,7 @@ ScanForRootBridges ( // If this device is not a multi function device, then skip the rest
// of this PCI device
//
- if (Function == 0 && !IS_PCI_MULTI_FUNC (&Pci)) {
+ if ((Function == 0) && !IS_PCI_MULTI_FUNC (&Pci)) {
break;
}
}
@@ -566,17 +590,24 @@ ScanForRootBridges ( (*NumberOfRootBridges) * sizeof (PCI_ROOT_BRIDGE),
(*NumberOfRootBridges + 1) * sizeof (PCI_ROOT_BRIDGE),
RootBridges
- );
+ );
ASSERT (RootBridges != NULL);
AdjustRootBridgeResource (&Io, &Mem, &MemAbove4G, &PMem, &PMemAbove4G);
InitRootBridge (
- Attributes, Attributes, 0,
- (UINT8) PrimaryBus, (UINT8) SubBus,
- &Io, &Mem, &MemAbove4G, &PMem, &PMemAbove4G,
+ Attributes,
+ Attributes,
+ 0,
+ (UINT8)PrimaryBus,
+ (UINT8)SubBus,
+ &Io,
+ &Mem,
+ &MemAbove4G,
+ &PMem,
+ &PMemAbove4G,
&RootBridges[*NumberOfRootBridges]
- );
+ );
RootBridges[*NumberOfRootBridges].ResourceAssigned = TRUE;
//
// Increment the index for the next PCI Root Bridge
@@ -601,26 +632,29 @@ PCI_ROOT_BRIDGE * RetrieveRootBridgeInfoFromHob (
IN UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES *PciRootBridgeInfo,
OUT UINTN *NumberOfRootBridges
-)
+ )
{
- PCI_ROOT_BRIDGE *PciRootBridges;
- UINTN Size;
- UINT8 Index;
+ PCI_ROOT_BRIDGE *PciRootBridges;
+ UINTN Size;
+ UINT8 Index;
ASSERT (PciRootBridgeInfo != NULL);
ASSERT (NumberOfRootBridges != NULL);
if (PciRootBridgeInfo == NULL) {
return NULL;
}
+
if (PciRootBridgeInfo->Count == 0) {
return NULL;
}
- Size = PciRootBridgeInfo->Count * sizeof (PCI_ROOT_BRIDGE);
- PciRootBridges = (PCI_ROOT_BRIDGE *) AllocatePool (Size);
+
+ Size = PciRootBridgeInfo->Count * sizeof (PCI_ROOT_BRIDGE);
+ PciRootBridges = (PCI_ROOT_BRIDGE *)AllocatePool (Size);
ASSERT (PciRootBridges != NULL);
if (PciRootBridges == NULL) {
return NULL;
}
+
ZeroMem (PciRootBridges, PciRootBridgeInfo->Count * sizeof (PCI_ROOT_BRIDGE));
//
@@ -634,13 +668,13 @@ RetrieveRootBridgeInfoFromHob ( PciRootBridges[Index].NoExtendedConfigSpace = PciRootBridgeInfo->RootBridge[Index].NoExtendedConfigSpace;
PciRootBridges[Index].ResourceAssigned = PciRootBridgeInfo->ResourceAssigned;
PciRootBridges[Index].AllocationAttributes = PciRootBridgeInfo->RootBridge[Index].AllocationAttributes;
- PciRootBridges[Index].DevicePath = CreateRootBridgeDevicePath(PciRootBridgeInfo->RootBridge[Index].HID, PciRootBridgeInfo->RootBridge[Index].UID);
- CopyMem(&PciRootBridges[Index].Bus, &PciRootBridgeInfo->RootBridge[Index].Bus, sizeof(UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE));
- CopyMem(&PciRootBridges[Index].Io, &PciRootBridgeInfo->RootBridge[Index].Io, sizeof(UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE));
- CopyMem(&PciRootBridges[Index].Mem, &PciRootBridgeInfo->RootBridge[Index].Mem, sizeof(UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE));
- CopyMem(&PciRootBridges[Index].MemAbove4G, &PciRootBridgeInfo->RootBridge[Index].MemAbove4G, sizeof(UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE));
- CopyMem(&PciRootBridges[Index].PMem, &PciRootBridgeInfo->RootBridge[Index].PMem, sizeof(UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE));
- CopyMem(&PciRootBridges[Index].PMemAbove4G, &PciRootBridgeInfo->RootBridge[Index].PMemAbove4G, sizeof(UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE));
+ PciRootBridges[Index].DevicePath = CreateRootBridgeDevicePath (PciRootBridgeInfo->RootBridge[Index].HID, PciRootBridgeInfo->RootBridge[Index].UID);
+ CopyMem (&PciRootBridges[Index].Bus, &PciRootBridgeInfo->RootBridge[Index].Bus, sizeof (UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE));
+ CopyMem (&PciRootBridges[Index].Io, &PciRootBridgeInfo->RootBridge[Index].Io, sizeof (UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE));
+ CopyMem (&PciRootBridges[Index].Mem, &PciRootBridgeInfo->RootBridge[Index].Mem, sizeof (UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE));
+ CopyMem (&PciRootBridges[Index].MemAbove4G, &PciRootBridgeInfo->RootBridge[Index].MemAbove4G, sizeof (UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE));
+ CopyMem (&PciRootBridges[Index].PMem, &PciRootBridgeInfo->RootBridge[Index].PMem, sizeof (UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE));
+ CopyMem (&PciRootBridges[Index].PMemAbove4G, &PciRootBridgeInfo->RootBridge[Index].PMemAbove4G, sizeof (UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE));
}
*NumberOfRootBridges = PciRootBridgeInfo->Count;
diff --git a/UefiPayloadPkg/Library/PciSegmentInfoLibAcpiBoardInfo/PciSegmentInfoLibAcpiBoardInfo.c b/UefiPayloadPkg/Library/PciSegmentInfoLibAcpiBoardInfo/PciSegmentInfoLibAcpiBoardInfo.c index d37c91cc9f..6953cfdfbe 100644 --- a/UefiPayloadPkg/Library/PciSegmentInfoLibAcpiBoardInfo/PciSegmentInfoLibAcpiBoardInfo.c +++ b/UefiPayloadPkg/Library/PciSegmentInfoLibAcpiBoardInfo/PciSegmentInfoLibAcpiBoardInfo.c @@ -14,7 +14,7 @@ #include <Library/PciSegmentInfoLib.h>
#include <Library/DebugLib.h>
-STATIC PCI_SEGMENT_INFO mPciSegment0 = {
+STATIC PCI_SEGMENT_INFO mPciSegment0 = {
0, // Segment number
0, // To be fixed later
0, // Start bus number
@@ -51,9 +51,10 @@ GetPciSegmentInfo ( GuidHob = GetFirstGuidHob (&gUefiAcpiBoardInfoGuid);
ASSERT (GuidHob != NULL);
- AcpiBoardInfo = (ACPI_BOARD_INFO *) GET_GUID_HOB_DATA (GuidHob);
+ AcpiBoardInfo = (ACPI_BOARD_INFO *)GET_GUID_HOB_DATA (GuidHob);
mPciSegment0.BaseAddress = AcpiBoardInfo->PcieBaseAddress;
}
+
*Count = 1;
return &mPciSegment0;
}
diff --git a/UefiPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManager.c b/UefiPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManager.c index dd91fcb29d..a8ead775ea 100644 --- a/UefiPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManager.c +++ b/UefiPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManager.c @@ -24,22 +24,22 @@ InstallReadyToLock ( VOID
)
{
- EFI_STATUS Status;
- EFI_HANDLE Handle;
- EFI_SMM_ACCESS2_PROTOCOL *SmmAccess;
+ EFI_STATUS Status;
+ EFI_HANDLE Handle;
+ EFI_SMM_ACCESS2_PROTOCOL *SmmAccess;
- DEBUG((DEBUG_INFO,"InstallReadyToLock entering......\n"));
+ DEBUG ((DEBUG_INFO, "InstallReadyToLock entering......\n"));
//
// Inform the SMM infrastructure that we're entering BDS and may run 3rd party code hereafter
// Since PI1.2.1, we need signal EndOfDxe as ExitPmAuth
//
EfiEventGroupSignal (&gEfiEndOfDxeEventGroupGuid);
- DEBUG((DEBUG_INFO,"All EndOfDxe callbacks have returned successfully\n"));
+ DEBUG ((DEBUG_INFO, "All EndOfDxe callbacks have returned successfully\n"));
//
// Install DxeSmmReadyToLock protocol in order to lock SMM
//
- Status = gBS->LocateProtocol (&gEfiSmmAccess2ProtocolGuid, NULL, (VOID **) &SmmAccess);
+ Status = gBS->LocateProtocol (&gEfiSmmAccess2ProtocolGuid, NULL, (VOID **)&SmmAccess);
if (!EFI_ERROR (Status)) {
Handle = NULL;
Status = gBS->InstallProtocolInterface (
@@ -51,7 +51,7 @@ InstallReadyToLock ( ASSERT_EFI_ERROR (Status);
}
- DEBUG((DEBUG_INFO,"InstallReadyToLock end\n"));
+ DEBUG ((DEBUG_INFO, "InstallReadyToLock end\n"));
return;
}
@@ -70,12 +70,12 @@ InstallReadyToLock ( **/
INTN
PlatformFindLoadOption (
- IN CONST EFI_BOOT_MANAGER_LOAD_OPTION *Key,
- IN CONST EFI_BOOT_MANAGER_LOAD_OPTION *Array,
- IN UINTN Count
-)
+ IN CONST EFI_BOOT_MANAGER_LOAD_OPTION *Key,
+ IN CONST EFI_BOOT_MANAGER_LOAD_OPTION *Array,
+ IN UINTN Count
+ )
{
- UINTN Index;
+ UINTN Index;
for (Index = 0; Index < Count; Index++) {
if ((Key->OptionType == Array[Index].OptionType) &&
@@ -83,8 +83,9 @@ PlatformFindLoadOption ( (StrCmp (Key->Description, Array[Index].Description) == 0) &&
(CompareMem (Key->FilePath, Array[Index].FilePath, GetDevicePathSize (Key->FilePath)) == 0) &&
(Key->OptionalDataSize == Array[Index].OptionalDataSize) &&
- (CompareMem (Key->OptionalData, Array[Index].OptionalData, Key->OptionalDataSize) == 0)) {
- return (INTN) Index;
+ (CompareMem (Key->OptionalData, Array[Index].OptionalData, Key->OptionalDataSize) == 0))
+ {
+ return (INTN)Index;
}
}
@@ -100,28 +101,28 @@ PlatformFindLoadOption ( **/
VOID
PlatformRegisterFvBootOption (
- EFI_GUID *FileGuid,
- CHAR16 *Description,
- UINT32 Attributes
-)
+ EFI_GUID *FileGuid,
+ CHAR16 *Description,
+ UINT32 Attributes
+ )
{
- EFI_STATUS Status;
- UINTN OptionIndex;
- EFI_BOOT_MANAGER_LOAD_OPTION NewOption;
- EFI_BOOT_MANAGER_LOAD_OPTION *BootOptions;
- UINTN BootOptionCount;
- MEDIA_FW_VOL_FILEPATH_DEVICE_PATH FileNode;
- EFI_LOADED_IMAGE_PROTOCOL *LoadedImage;
- EFI_DEVICE_PATH_PROTOCOL *DevicePath;
-
- Status = gBS->HandleProtocol (gImageHandle, &gEfiLoadedImageProtocolGuid, (VOID **) &LoadedImage);
+ EFI_STATUS Status;
+ UINTN OptionIndex;
+ EFI_BOOT_MANAGER_LOAD_OPTION NewOption;
+ EFI_BOOT_MANAGER_LOAD_OPTION *BootOptions;
+ UINTN BootOptionCount;
+ MEDIA_FW_VOL_FILEPATH_DEVICE_PATH FileNode;
+ EFI_LOADED_IMAGE_PROTOCOL *LoadedImage;
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;
+
+ Status = gBS->HandleProtocol (gImageHandle, &gEfiLoadedImageProtocolGuid, (VOID **)&LoadedImage);
ASSERT_EFI_ERROR (Status);
EfiInitializeFwVolDevicepathNode (&FileNode, FileGuid);
DevicePath = AppendDevicePathNode (
DevicePathFromHandle (LoadedImage->DeviceHandle),
- (EFI_DEVICE_PATH_PROTOCOL *) &FileNode
- );
+ (EFI_DEVICE_PATH_PROTOCOL *)&FileNode
+ );
Status = EfiBootManagerInitializeLoadOption (
&NewOption,
@@ -132,16 +133,17 @@ PlatformRegisterFvBootOption ( DevicePath,
NULL,
0
- );
+ );
if (!EFI_ERROR (Status)) {
BootOptions = EfiBootManagerGetLoadOptions (&BootOptionCount, LoadOptionTypeBoot);
OptionIndex = PlatformFindLoadOption (&NewOption, BootOptions, BootOptionCount);
if (OptionIndex == -1) {
- Status = EfiBootManagerAddLoadOptionVariable (&NewOption, (UINTN) -1);
+ Status = EfiBootManagerAddLoadOptionVariable (&NewOption, (UINTN)-1);
ASSERT_EFI_ERROR (Status);
}
+
EfiBootManagerFreeLoadOption (&NewOption);
EfiBootManagerFreeLoadOptions (BootOptions, BootOptionCount);
}
@@ -159,20 +161,21 @@ VOID EFIAPI
PlatformBootManagerBeforeConsole (
VOID
-)
+ )
{
- EFI_INPUT_KEY Enter;
- EFI_INPUT_KEY F2;
- EFI_INPUT_KEY Down;
- EFI_BOOT_MANAGER_LOAD_OPTION BootOption;
- EFI_STATUS Status;
+ EFI_INPUT_KEY Enter;
+ EFI_INPUT_KEY F2;
+ EFI_INPUT_KEY Down;
+ EFI_BOOT_MANAGER_LOAD_OPTION BootOption;
+ EFI_STATUS Status;
- Status = gBS->LocateProtocol (&gUniversalPayloadPlatformBootManagerOverrideProtocolGuid, NULL, (VOID **) &mUniversalPayloadPlatformBootManagerOverrideInstance);
+ Status = gBS->LocateProtocol (&gUniversalPayloadPlatformBootManagerOverrideProtocolGuid, NULL, (VOID **)&mUniversalPayloadPlatformBootManagerOverrideInstance);
if (EFI_ERROR (Status)) {
mUniversalPayloadPlatformBootManagerOverrideInstance = NULL;
}
- if (mUniversalPayloadPlatformBootManagerOverrideInstance != NULL){
- mUniversalPayloadPlatformBootManagerOverrideInstance->BeforeConsole();
+
+ if (mUniversalPayloadPlatformBootManagerOverrideInstance != NULL) {
+ mUniversalPayloadPlatformBootManagerOverrideInstance->BeforeConsole ();
return;
}
@@ -189,7 +192,7 @@ PlatformBootManagerBeforeConsole ( F2.ScanCode = SCAN_F2;
F2.UnicodeChar = CHAR_NULL;
EfiBootManagerGetBootManagerMenu (&BootOption);
- EfiBootManagerAddKeyOptionVariable (NULL, (UINT16) BootOption.OptionNumber, 0, &F2, NULL);
+ EfiBootManagerAddKeyOptionVariable (NULL, (UINT16)BootOption.OptionNumber, 0, &F2, NULL);
//
// Also add Down key to Boot Manager Menu since some serial terminals don't support F2 key.
@@ -197,7 +200,7 @@ PlatformBootManagerBeforeConsole ( Down.ScanCode = SCAN_DOWN;
Down.UnicodeChar = CHAR_NULL;
EfiBootManagerGetBootManagerMenu (&BootOption);
- EfiBootManagerAddKeyOptionVariable (NULL, (UINT16) BootOption.OptionNumber, 0, &Down, NULL);
+ EfiBootManagerAddKeyOptionVariable (NULL, (UINT16)BootOption.OptionNumber, 0, &Down, NULL);
//
// Install ready to lock.
@@ -227,15 +230,16 @@ VOID EFIAPI
PlatformBootManagerAfterConsole (
VOID
-)
+ )
{
EFI_GRAPHICS_OUTPUT_BLT_PIXEL Black;
EFI_GRAPHICS_OUTPUT_BLT_PIXEL White;
- if (mUniversalPayloadPlatformBootManagerOverrideInstance != NULL){
- mUniversalPayloadPlatformBootManagerOverrideInstance->AfterConsole();
+ if (mUniversalPayloadPlatformBootManagerOverrideInstance != NULL) {
+ mUniversalPayloadPlatformBootManagerOverrideInstance->AfterConsole ();
return;
}
+
Black.Blue = Black.Green = Black.Red = Black.Reserved = 0;
White.Blue = White.Green = White.Red = White.Reserved = 0xFF;
@@ -252,8 +256,7 @@ PlatformBootManagerAfterConsole ( L"F2 or Down to enter Boot Manager Menu.\n"
L"ENTER to boot directly.\n"
L"\n"
- );
-
+ );
}
/**
@@ -264,12 +267,13 @@ PlatformBootManagerAfterConsole ( VOID
EFIAPI
PlatformBootManagerWaitCallback (
- UINT16 TimeoutRemain
-)
+ UINT16 TimeoutRemain
+ )
{
- if (mUniversalPayloadPlatformBootManagerOverrideInstance != NULL){
+ if (mUniversalPayloadPlatformBootManagerOverrideInstance != NULL) {
mUniversalPayloadPlatformBootManagerOverrideInstance->WaitCallback (TimeoutRemain);
}
+
return;
}
@@ -286,9 +290,10 @@ PlatformBootManagerUnableToBoot ( VOID
)
{
- if (mUniversalPayloadPlatformBootManagerOverrideInstance != NULL){
- mUniversalPayloadPlatformBootManagerOverrideInstance->UnableToBoot();
+ if (mUniversalPayloadPlatformBootManagerOverrideInstance != NULL) {
+ mUniversalPayloadPlatformBootManagerOverrideInstance->UnableToBoot ();
}
+
return;
}
@@ -307,7 +312,7 @@ EFIAPI PlatformBootManagerLibConstructor (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
-)
+ )
{
EFI_STATUS Status;
UINTN Size;
@@ -324,16 +329,18 @@ PlatformBootManagerLibConstructor ( return EFI_SUCCESS;
}
- GenericHeader = (UNIVERSAL_PAYLOAD_GENERIC_HEADER *) GET_GUID_HOB_DATA (GuidHob);
+ GenericHeader = (UNIVERSAL_PAYLOAD_GENERIC_HEADER *)GET_GUID_HOB_DATA (GuidHob);
if ((sizeof (UNIVERSAL_PAYLOAD_GENERIC_HEADER) > GET_GUID_HOB_DATA_SIZE (GuidHob)) || (GenericHeader->Length > GET_GUID_HOB_DATA_SIZE (GuidHob))) {
return EFI_NOT_FOUND;
}
+
if (GenericHeader->Revision == UNIVERSAL_PAYLOAD_BOOT_MANAGER_MENU_REVISION) {
- BootManagerMenuFile = (UNIVERSAL_PAYLOAD_BOOT_MANAGER_MENU *) GET_GUID_HOB_DATA (GuidHob);
+ BootManagerMenuFile = (UNIVERSAL_PAYLOAD_BOOT_MANAGER_MENU *)GET_GUID_HOB_DATA (GuidHob);
if (BootManagerMenuFile->Header.Length < UNIVERSAL_PAYLOAD_SIZEOF_THROUGH_FIELD (UNIVERSAL_PAYLOAD_BOOT_MANAGER_MENU, FileName)) {
return EFI_NOT_FOUND;
}
- Size = sizeof (BootManagerMenuFile->FileName);
+
+ Size = sizeof (BootManagerMenuFile->FileName);
Status = PcdSetPtrS (PcdBootManagerMenuFile, &Size, &BootManagerMenuFile->FileName);
ASSERT_EFI_ERROR (Status);
} else {
diff --git a/UefiPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManager.h b/UefiPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManager.h index c781610c6c..5614aadafb 100644 --- a/UefiPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManager.h +++ b/UefiPayloadPkg/Library/PlatformBootManagerLib/PlatformBootManager.h @@ -29,8 +29,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include <Protocol/SmmAccess2.h>
typedef struct {
- EFI_DEVICE_PATH_PROTOCOL *DevicePath;
- UINTN ConnectType;
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;
+ UINTN ConnectType;
} PLATFORM_CONSOLE_CONNECT_ENTRY;
extern PLATFORM_CONSOLE_CONNECT_ENTRY gPlatformConsole[];
@@ -42,42 +42,42 @@ extern PLATFORM_CONSOLE_CONNECT_ENTRY gPlatformConsole[]; { END_DEVICE_PATH_LENGTH, 0 },\
}
-#define CONSOLE_OUT BIT0
-#define CONSOLE_IN BIT1
-#define STD_ERROR BIT2
+#define CONSOLE_OUT BIT0
+#define CONSOLE_IN BIT1
+#define STD_ERROR BIT2
-#define CLASS_HID 3
-#define SUBCLASS_BOOT 1
-#define PROTOCOL_KEYBOARD 1
+#define CLASS_HID 3
+#define SUBCLASS_BOOT 1
+#define PROTOCOL_KEYBOARD 1
typedef struct {
- USB_CLASS_DEVICE_PATH UsbClass;
- EFI_DEVICE_PATH_PROTOCOL End;
+ USB_CLASS_DEVICE_PATH UsbClass;
+ EFI_DEVICE_PATH_PROTOCOL End;
} USB_CLASS_FORMAT_DEVICE_PATH;
typedef struct {
- VENDOR_DEVICE_PATH VendorDevicePath;
- UINT32 Instance;
+ VENDOR_DEVICE_PATH VendorDevicePath;
+ UINT32 Instance;
} WIN_NT_VENDOR_DEVICE_PATH_NODE;
//
// Below is the platform console device path
//
typedef struct {
- VENDOR_DEVICE_PATH NtBus;
- WIN_NT_VENDOR_DEVICE_PATH_NODE SerialDevice;
- UART_DEVICE_PATH Uart;
- VENDOR_DEVICE_PATH TerminalType;
- EFI_DEVICE_PATH_PROTOCOL End;
+ VENDOR_DEVICE_PATH NtBus;
+ WIN_NT_VENDOR_DEVICE_PATH_NODE SerialDevice;
+ UART_DEVICE_PATH Uart;
+ VENDOR_DEVICE_PATH TerminalType;
+ EFI_DEVICE_PATH_PROTOCOL End;
} NT_ISA_SERIAL_DEVICE_PATH;
typedef struct {
- VENDOR_DEVICE_PATH NtBus;
- WIN_NT_VENDOR_DEVICE_PATH_NODE NtGopDevice;
- EFI_DEVICE_PATH_PROTOCOL End;
+ VENDOR_DEVICE_PATH NtBus;
+ WIN_NT_VENDOR_DEVICE_PATH_NODE NtGopDevice;
+ EFI_DEVICE_PATH_PROTOCOL End;
} NT_PLATFORM_GOP_DEVICE_PATH;
-extern USB_CLASS_FORMAT_DEVICE_PATH gUsbClassKeyboardDevicePath;
+extern USB_CLASS_FORMAT_DEVICE_PATH gUsbClassKeyboardDevicePath;
/**
Use SystemTable Conout to stop video based Simple Text Out consoles from going
@@ -92,7 +92,7 @@ extern USB_CLASS_FORMAT_DEVICE_PATH gUsbClassKeyboardDevicePath; EFI_STATUS
PlatformBootManagerEnableQuietBoot (
IN EFI_GUID *LogoFile
-);
+ );
/**
Use SystemTable Conout to turn on video based Simple Text Out consoles. The
@@ -104,7 +104,7 @@ PlatformBootManagerEnableQuietBoot ( EFI_STATUS
PlatformBootManagerDisableQuietBoot (
VOID
-);
+ );
/**
Show progress bar with title above it. It only works in Graphics mode.
@@ -121,12 +121,12 @@ PlatformBootManagerDisableQuietBoot ( **/
EFI_STATUS
PlatformBootManagerShowProgress (
- IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL TitleForeground,
- IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL TitleBackground,
- IN CHAR16 *Title,
- IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL ProgressColor,
- IN UINTN Progress,
- IN UINTN PreviousValue
-);
+ IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL TitleForeground,
+ IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL TitleBackground,
+ IN CHAR16 *Title,
+ IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL ProgressColor,
+ IN UINTN Progress,
+ IN UINTN PreviousValue
+ );
#endif // _PLATFORM_BOOT_MANAGER_H
diff --git a/UefiPayloadPkg/Library/PlatformBootManagerLib/PlatformConsole.c b/UefiPayloadPkg/Library/PlatformBootManagerLib/PlatformConsole.c index a27cc552ab..c93c7c99b5 100644 --- a/UefiPayloadPkg/Library/PlatformBootManagerLib/PlatformConsole.c +++ b/UefiPayloadPkg/Library/PlatformBootManagerLib/PlatformConsole.c @@ -90,11 +90,11 @@ SPDX-License-Identifier: BSD-2-Clause-Patent DEVICE_PATH_MESSAGING_PC_ANSI \
}
-ACPI_HID_DEVICE_PATH gPnpPs2KeyboardDeviceNode = gPnpPs2Keyboard;
-ACPI_HID_DEVICE_PATH gPnp16550ComPortDeviceNode = gPnp16550ComPort;
-UART_DEVICE_PATH gUartDeviceNode = gUart;
-VENDOR_DEVICE_PATH gTerminalTypeDeviceNode = gPcAnsiTerminal;
-VENDOR_DEVICE_PATH gUartDeviceVendorNode = gUartVendor;
+ACPI_HID_DEVICE_PATH gPnpPs2KeyboardDeviceNode = gPnpPs2Keyboard;
+ACPI_HID_DEVICE_PATH gPnp16550ComPortDeviceNode = gPnp16550ComPort;
+UART_DEVICE_PATH gUartDeviceNode = gUart;
+VENDOR_DEVICE_PATH gTerminalTypeDeviceNode = gPcAnsiTerminal;
+VENDOR_DEVICE_PATH gUartDeviceVendorNode = gUartVendor;
//
// Predefined platform root bridge
@@ -104,12 +104,12 @@ PLATFORM_ROOT_BRIDGE_DEVICE_PATH gPlatformRootBridge0 = { gEndEntire
};
-EFI_DEVICE_PATH_PROTOCOL *gPlatformRootBridges[] = {
- (EFI_DEVICE_PATH_PROTOCOL *) &gPlatformRootBridge0,
+EFI_DEVICE_PATH_PROTOCOL *gPlatformRootBridges[] = {
+ (EFI_DEVICE_PATH_PROTOCOL *)&gPlatformRootBridge0,
NULL
};
-BOOLEAN mDetectVgaOnly;
+BOOLEAN mDetectVgaOnly;
/**
Add IsaKeyboard to ConIn; add IsaSerial to ConOut, ConIn, ErrOut.
@@ -124,22 +124,23 @@ BOOLEAN mDetectVgaOnly; **/
EFI_STATUS
PrepareLpcBridgeDevicePath (
- IN EFI_HANDLE DeviceHandle
-)
+ IN EFI_HANDLE DeviceHandle
+ )
{
EFI_STATUS Status;
EFI_DEVICE_PATH_PROTOCOL *DevicePath;
EFI_DEVICE_PATH_PROTOCOL *TempDevicePath;
DevicePath = NULL;
- Status = gBS->HandleProtocol (
- DeviceHandle,
- &gEfiDevicePathProtocolGuid,
- (VOID*)&DevicePath
- );
+ Status = gBS->HandleProtocol (
+ DeviceHandle,
+ &gEfiDevicePathProtocolGuid,
+ (VOID *)&DevicePath
+ );
if (EFI_ERROR (Status)) {
return Status;
}
+
TempDevicePath = DevicePath;
//
@@ -175,19 +176,19 @@ PrepareLpcBridgeDevicePath ( **/
EFI_STATUS
GetGopDevicePath (
- IN EFI_DEVICE_PATH_PROTOCOL *PciDevicePath,
- OUT EFI_DEVICE_PATH_PROTOCOL **GopDevicePath
-)
+ IN EFI_DEVICE_PATH_PROTOCOL *PciDevicePath,
+ OUT EFI_DEVICE_PATH_PROTOCOL **GopDevicePath
+ )
{
- UINTN Index;
- EFI_STATUS Status;
- EFI_HANDLE PciDeviceHandle;
- EFI_DEVICE_PATH_PROTOCOL *TempDevicePath;
- EFI_DEVICE_PATH_PROTOCOL *TempPciDevicePath;
- UINTN GopHandleCount;
- EFI_HANDLE *GopHandleBuffer;
-
- if (PciDevicePath == NULL || GopDevicePath == NULL) {
+ UINTN Index;
+ EFI_STATUS Status;
+ EFI_HANDLE PciDeviceHandle;
+ EFI_DEVICE_PATH_PROTOCOL *TempDevicePath;
+ EFI_DEVICE_PATH_PROTOCOL *TempPciDevicePath;
+ UINTN GopHandleCount;
+ EFI_HANDLE *GopHandleBuffer;
+
+ if ((PciDevicePath == NULL) || (GopDevicePath == NULL)) {
return EFI_INVALID_PARAMETER;
}
@@ -198,10 +199,10 @@ GetGopDevicePath ( TempPciDevicePath = PciDevicePath;
Status = gBS->LocateDevicePath (
- &gEfiDevicePathProtocolGuid,
- &TempPciDevicePath,
- &PciDeviceHandle
- );
+ &gEfiDevicePathProtocolGuid,
+ &TempPciDevicePath,
+ &PciDeviceHandle
+ );
if (EFI_ERROR (Status)) {
return Status;
}
@@ -209,26 +210,28 @@ GetGopDevicePath ( gBS->ConnectController (PciDeviceHandle, NULL, NULL, FALSE);
Status = gBS->LocateHandleBuffer (
- ByProtocol,
- &gEfiGraphicsOutputProtocolGuid,
- NULL,
- &GopHandleCount,
- &GopHandleBuffer
- );
+ ByProtocol,
+ &gEfiGraphicsOutputProtocolGuid,
+ NULL,
+ &GopHandleCount,
+ &GopHandleBuffer
+ );
if (!EFI_ERROR (Status)) {
//
// Add all the child handles as possible Console Device
//
for (Index = 0; Index < GopHandleCount; Index++) {
- Status = gBS->HandleProtocol (GopHandleBuffer[Index], &gEfiDevicePathProtocolGuid, (VOID*)&TempDevicePath);
+ Status = gBS->HandleProtocol (GopHandleBuffer[Index], &gEfiDevicePathProtocolGuid, (VOID *)&TempDevicePath);
if (EFI_ERROR (Status)) {
continue;
}
+
if (CompareMem (
PciDevicePath,
TempDevicePath,
GetDevicePathSize (PciDevicePath) - END_DEVICE_PATH_LENGTH
- ) == 0) {
+ ) == 0)
+ {
//
// In current implementation, we only enable one of the child handles
// as console device, i.e. sotre one of the child handle's device
@@ -245,6 +248,7 @@ GetGopDevicePath ( EfiBootManagerUpdateConsoleVariable (ConOut, TempDevicePath, NULL);
}
}
+
gBS->FreePool (GopHandleBuffer);
}
@@ -262,19 +266,19 @@ GetGopDevicePath ( **/
EFI_STATUS
PreparePciVgaDevicePath (
- IN EFI_HANDLE DeviceHandle
-)
+ IN EFI_HANDLE DeviceHandle
+ )
{
EFI_STATUS Status;
EFI_DEVICE_PATH_PROTOCOL *DevicePath;
EFI_DEVICE_PATH_PROTOCOL *GopDevicePath;
DevicePath = NULL;
- Status = gBS->HandleProtocol (
- DeviceHandle,
- &gEfiDevicePathProtocolGuid,
- (VOID*)&DevicePath
- );
+ Status = gBS->HandleProtocol (
+ DeviceHandle,
+ &gEfiDevicePathProtocolGuid,
+ (VOID *)&DevicePath
+ );
if (EFI_ERROR (Status)) {
return Status;
}
@@ -298,18 +302,18 @@ PreparePciVgaDevicePath ( **/
EFI_STATUS
PreparePciSerialDevicePath (
- IN EFI_HANDLE DeviceHandle
-)
+ IN EFI_HANDLE DeviceHandle
+ )
{
EFI_STATUS Status;
EFI_DEVICE_PATH_PROTOCOL *DevicePath;
DevicePath = NULL;
- Status = gBS->HandleProtocol (
- DeviceHandle,
- &gEfiDevicePathProtocolGuid,
- (VOID*)&DevicePath
- );
+ Status = gBS->HandleProtocol (
+ DeviceHandle,
+ &gEfiDevicePathProtocolGuid,
+ (VOID *)&DevicePath
+ );
if (EFI_ERROR (Status)) {
return Status;
}
@@ -318,13 +322,12 @@ PreparePciSerialDevicePath ( DevicePath = AppendDevicePathNode (DevicePath, (EFI_DEVICE_PATH_PROTOCOL *)&gTerminalTypeDeviceNode);
EfiBootManagerUpdateConsoleVariable (ConOut, DevicePath, NULL);
- EfiBootManagerUpdateConsoleVariable (ConIn, DevicePath, NULL);
+ EfiBootManagerUpdateConsoleVariable (ConIn, DevicePath, NULL);
EfiBootManagerUpdateConsoleVariable (ErrOut, DevicePath, NULL);
return EFI_SUCCESS;
}
-
/**
For every PCI instance execute a callback function.
@@ -341,26 +344,26 @@ VisitAllInstancesOfProtocol ( IN EFI_GUID *Id,
IN PROTOCOL_INSTANCE_CALLBACK CallBackFunction,
IN VOID *Context
-)
+ )
{
- EFI_STATUS Status;
- UINTN HandleCount;
- EFI_HANDLE *HandleBuffer;
- UINTN Index;
- VOID *Instance;
+ EFI_STATUS Status;
+ UINTN HandleCount;
+ EFI_HANDLE *HandleBuffer;
+ UINTN Index;
+ VOID *Instance;
//
// Start to check all the PciIo to find all possible device
//
- HandleCount = 0;
+ HandleCount = 0;
HandleBuffer = NULL;
- Status = gBS->LocateHandleBuffer (
- ByProtocol,
- Id,
- NULL,
- &HandleCount,
- &HandleBuffer
- );
+ Status = gBS->LocateHandleBuffer (
+ ByProtocol,
+ Id,
+ NULL,
+ &HandleCount,
+ &HandleBuffer
+ );
if (EFI_ERROR (Status)) {
return Status;
}
@@ -371,11 +374,11 @@ VisitAllInstancesOfProtocol ( continue;
}
- Status = (*CallBackFunction) (
- HandleBuffer[Index],
- Instance,
- Context
- );
+ Status = (*CallBackFunction)(
+ HandleBuffer[Index],
+ Instance,
+ Context
+ );
}
gBS->FreePool (HandleBuffer);
@@ -383,7 +386,6 @@ VisitAllInstancesOfProtocol ( return EFI_SUCCESS;
}
-
/**
For every PCI instance execute a callback function.
@@ -400,37 +402,35 @@ VisitingAPciInstance ( IN EFI_HANDLE Handle,
IN VOID *Instance,
IN VOID *Context
-)
+ )
{
- EFI_STATUS Status;
- EFI_PCI_IO_PROTOCOL *PciIo;
- PCI_TYPE00 Pci;
+ EFI_STATUS Status;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ PCI_TYPE00 Pci;
- PciIo = (EFI_PCI_IO_PROTOCOL*) Instance;
+ PciIo = (EFI_PCI_IO_PROTOCOL *)Instance;
//
// Check for all PCI device
//
Status = PciIo->Pci.Read (
- PciIo,
- EfiPciIoWidthUint32,
- 0,
- sizeof (Pci) / sizeof (UINT32),
- &Pci
- );
+ PciIo,
+ EfiPciIoWidthUint32,
+ 0,
+ sizeof (Pci) / sizeof (UINT32),
+ &Pci
+ );
if (EFI_ERROR (Status)) {
return Status;
}
- return (*(VISIT_PCI_INSTANCE_CALLBACK)(UINTN) Context) (
- Handle,
- PciIo,
- &Pci
- );
-
+ return (*(VISIT_PCI_INSTANCE_CALLBACK)(UINTN)Context)(
+ Handle,
+ PciIo,
+ &Pci
+ );
}
-
/**
For every PCI instance execute a callback function.
@@ -442,17 +442,16 @@ VisitingAPciInstance ( EFI_STATUS
EFIAPI
VisitAllPciInstances (
- IN VISIT_PCI_INSTANCE_CALLBACK CallBackFunction
-)
+ IN VISIT_PCI_INSTANCE_CALLBACK CallBackFunction
+ )
{
return VisitAllInstancesOfProtocol (
&gEfiPciIoProtocolGuid,
VisitingAPciInstance,
- (VOID*)(UINTN) CallBackFunction
- );
+ (VOID *)(UINTN)CallBackFunction
+ );
}
-
/**
Do platform specific PCI Device check and add them to
ConOut, ConIn, ErrOut.
@@ -471,16 +470,16 @@ DetectAndPreparePlatformPciDevicePath ( IN EFI_HANDLE Handle,
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN PCI_TYPE00 *Pci
-)
+ )
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
Status = PciIo->Attributes (
- PciIo,
- EfiPciIoAttributeOperationEnable,
- EFI_PCI_DEVICE_ENABLE,
- NULL
- );
+ PciIo,
+ EfiPciIoAttributeOperationEnable,
+ EFI_PCI_DEVICE_ENABLE,
+ NULL
+ );
ASSERT_EFI_ERROR (Status);
if (!mDetectVgaOnly) {
@@ -491,7 +490,8 @@ DetectAndPreparePlatformPciDevicePath ( ((IS_PCI_ISA_PDECODE (Pci)) &&
(Pci->Hdr.VendorId == 0x8086)
)
- ) {
+ )
+ {
//
// Add IsaKeyboard to ConIn,
// add IsaSerial to ConOut, ConIn, ErrOut
@@ -500,6 +500,7 @@ DetectAndPreparePlatformPciDevicePath ( PrepareLpcBridgeDevicePath (Handle);
return EFI_SUCCESS;
}
+
//
// Here we decide which Serial device to enable in PCI bus
//
@@ -528,7 +529,6 @@ DetectAndPreparePlatformPciDevicePath ( return Status;
}
-
/**
Do platform specific PCI Device check and add them to ConOut, ConIn, ErrOut
@@ -540,21 +540,20 @@ DetectAndPreparePlatformPciDevicePath ( **/
EFI_STATUS
DetectAndPreparePlatformPciDevicePaths (
- BOOLEAN DetectVgaOnly
-)
+ BOOLEAN DetectVgaOnly
+ )
{
mDetectVgaOnly = DetectVgaOnly;
EfiBootManagerUpdateConsoleVariable (
ConIn,
- (EFI_DEVICE_PATH_PROTOCOL *) &gUsbClassKeyboardDevicePath,
+ (EFI_DEVICE_PATH_PROTOCOL *)&gUsbClassKeyboardDevicePath,
NULL
);
return VisitAllPciInstances (DetectAndPreparePlatformPciDevicePath);
}
-
/**
The function will connect root bridge
@@ -564,19 +563,19 @@ DetectAndPreparePlatformPciDevicePaths ( EFI_STATUS
ConnectRootBridge (
VOID
-)
+ )
{
- EFI_STATUS Status;
- EFI_HANDLE RootHandle;
+ EFI_STATUS Status;
+ EFI_HANDLE RootHandle;
//
// Make all the PCI_IO protocols on PCI Seg 0 show up
//
Status = gBS->LocateDevicePath (
- &gEfiDevicePathProtocolGuid,
- &gPlatformRootBridges[0],
- &RootHandle
- );
+ &gEfiDevicePathProtocolGuid,
+ &gPlatformRootBridges[0],
+ &RootHandle
+ );
if (EFI_ERROR (Status)) {
return Status;
}
@@ -598,7 +597,7 @@ VOID EFIAPI
PlatformConsoleInit (
VOID
-)
+ )
{
gUartDeviceNode.BaudRate = PcdGet64 (PcdUartDefaultBaudRate);
gUartDeviceNode.DataBits = PcdGet8 (PcdUartDefaultDataBits);
@@ -611,5 +610,4 @@ PlatformConsoleInit ( // Do platform specific PCI Device check and add them to ConOut, ConIn, ErrOut
//
DetectAndPreparePlatformPciDevicePaths (FALSE);
-
}
diff --git a/UefiPayloadPkg/Library/PlatformBootManagerLib/PlatformConsole.h b/UefiPayloadPkg/Library/PlatformBootManagerLib/PlatformConsole.h index e9d0eb00ee..a13f4b8b59 100644 --- a/UefiPayloadPkg/Library/PlatformBootManagerLib/PlatformConsole.h +++ b/UefiPayloadPkg/Library/PlatformBootManagerLib/PlatformConsole.h @@ -20,8 +20,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include <Library/DevicePathLib.h>
#include <Protocol/PciIo.h>
-#define IS_PCI_ISA_PDECODE(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA_PDECODE, 0)
-#define IS_PCI_16550SERIAL(_p) IS_CLASS3 (_p, PCI_CLASS_SCC, PCI_SUBCLASS_SERIAL, PCI_IF_16550)
+#define IS_PCI_ISA_PDECODE(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA_PDECODE, 0)
+#define IS_PCI_16550SERIAL(_p) IS_CLASS3 (_p, PCI_CLASS_SCC, PCI_SUBCLASS_SERIAL, PCI_IF_16550)
//
// Type definitions
@@ -31,8 +31,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent // Platform Root Bridge
//
typedef struct {
- ACPI_HID_DEVICE_PATH PciRootBridge;
- EFI_DEVICE_PATH_PROTOCOL End;
+ ACPI_HID_DEVICE_PATH PciRootBridge;
+ EFI_DEVICE_PATH_PROTOCOL End;
} PLATFORM_ROOT_BRIDGE_DEVICE_PATH;
typedef
@@ -41,7 +41,7 @@ EFI_STATUS IN EFI_HANDLE Handle,
IN VOID *Instance,
IN VOID *Context
-);
+ );
/**
@param[in] Handle - Handle of PCI device instance
@@ -54,7 +54,7 @@ EFI_STATUS IN EFI_HANDLE Handle,
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN PCI_TYPE00 *Pci
-);
+ );
/**
Platform console init. Include the platform firmware vendor, revision
@@ -65,6 +65,6 @@ VOID EFIAPI
PlatformConsoleInit (
VOID
-);
+ );
#endif
diff --git a/UefiPayloadPkg/Library/PlatformBootManagerLib/PlatformData.c b/UefiPayloadPkg/Library/PlatformBootManagerLib/PlatformData.c index 892a7f01be..960f0dbf49 100644 --- a/UefiPayloadPkg/Library/PlatformBootManagerLib/PlatformData.c +++ b/UefiPayloadPkg/Library/PlatformBootManagerLib/PlatformData.c @@ -11,22 +11,21 @@ SPDX-License-Identifier: BSD-2-Clause-Patent ///
/// Predefined platform default console device path
///
-GLOBAL_REMOVE_IF_UNREFERENCED PLATFORM_CONSOLE_CONNECT_ENTRY gPlatformConsole[] = {
+GLOBAL_REMOVE_IF_UNREFERENCED PLATFORM_CONSOLE_CONNECT_ENTRY gPlatformConsole[] = {
{
NULL,
0
}
};
-
-GLOBAL_REMOVE_IF_UNREFERENCED USB_CLASS_FORMAT_DEVICE_PATH gUsbClassKeyboardDevicePath = {
+GLOBAL_REMOVE_IF_UNREFERENCED USB_CLASS_FORMAT_DEVICE_PATH gUsbClassKeyboardDevicePath = {
{
{
MESSAGING_DEVICE_PATH,
MSG_USB_CLASS_DP,
{
- (UINT8) (sizeof (USB_CLASS_DEVICE_PATH)),
- (UINT8) ((sizeof (USB_CLASS_DEVICE_PATH)) >> 8)
+ (UINT8)(sizeof (USB_CLASS_DEVICE_PATH)),
+ (UINT8)((sizeof (USB_CLASS_DEVICE_PATH)) >> 8)
}
},
0xffff, // VendorId
diff --git a/UefiPayloadPkg/Library/PlatformHookLib/PlatformHookLib.c b/UefiPayloadPkg/Library/PlatformHookLib/PlatformHookLib.c index 004fcd8b7c..60a17b8fc2 100644 --- a/UefiPayloadPkg/Library/PlatformHookLib/PlatformHookLib.c +++ b/UefiPayloadPkg/Library/PlatformHookLib/PlatformHookLib.c @@ -13,7 +13,6 @@ #include <Library/PcdLib.h>
#include <Library/HobLib.h>
-
/** Library Constructor
@retval RETURN_SUCCESS Success.
@@ -57,13 +56,13 @@ PlatformHookSerialPortInitialize ( return EFI_NOT_FOUND;
}
- GenericHeader = (UNIVERSAL_PAYLOAD_GENERIC_HEADER *) GET_GUID_HOB_DATA (GuidHob);
+ GenericHeader = (UNIVERSAL_PAYLOAD_GENERIC_HEADER *)GET_GUID_HOB_DATA (GuidHob);
if ((sizeof (UNIVERSAL_PAYLOAD_GENERIC_HEADER) > GET_GUID_HOB_DATA_SIZE (GuidHob)) || (GenericHeader->Length > GET_GUID_HOB_DATA_SIZE (GuidHob))) {
return EFI_NOT_FOUND;
}
if (GenericHeader->Revision == UNIVERSAL_PAYLOAD_SERIAL_PORT_INFO_REVISION) {
- SerialPortInfo = (UNIVERSAL_PAYLOAD_SERIAL_PORT_INFO *) GET_GUID_HOB_DATA (GuidHob);
+ SerialPortInfo = (UNIVERSAL_PAYLOAD_SERIAL_PORT_INFO *)GET_GUID_HOB_DATA (GuidHob);
if (GenericHeader->Length < UNIVERSAL_PAYLOAD_SIZEOF_THROUGH_FIELD (UNIVERSAL_PAYLOAD_SERIAL_PORT_INFO, RegisterBase)) {
//
// Return if can't find the Serial Port Info Hob with enough length
@@ -75,14 +74,17 @@ PlatformHookSerialPortInitialize ( if (RETURN_ERROR (Status)) {
return Status;
}
+
Status = PcdSet64S (PcdSerialRegisterBase, SerialPortInfo->RegisterBase);
if (RETURN_ERROR (Status)) {
return Status;
}
+
Status = PcdSet32S (PcdSerialRegisterStride, SerialPortInfo->RegisterStride);
if (RETURN_ERROR (Status)) {
return Status;
}
+
Status = PcdSet32S (PcdSerialBaudRate, SerialPortInfo->BaudRate);
if (RETURN_ERROR (Status)) {
return Status;
diff --git a/UefiPayloadPkg/Library/PlatformSupportLibNull/PlatformSupportLibNull.c b/UefiPayloadPkg/Library/PlatformSupportLibNull/PlatformSupportLibNull.c index a1b129814e..7c68606009 100644 --- a/UefiPayloadPkg/Library/PlatformSupportLibNull/PlatformSupportLibNull.c +++ b/UefiPayloadPkg/Library/PlatformSupportLibNull/PlatformSupportLibNull.c @@ -26,4 +26,3 @@ ParsePlatformInfo ( {
return EFI_SUCCESS;
}
-
diff --git a/UefiPayloadPkg/Library/ResetSystemLib/ResetSystemLib.c b/UefiPayloadPkg/Library/ResetSystemLib/ResetSystemLib.c index b35a4cc1d9..1f2882069f 100644 --- a/UefiPayloadPkg/Library/ResetSystemLib/ResetSystemLib.c +++ b/UefiPayloadPkg/Library/ResetSystemLib/ResetSystemLib.c @@ -14,7 +14,7 @@ #include <Library/BaseMemoryLib.h>
#include <Guid/AcpiBoardInfoGuid.h>
-ACPI_BOARD_INFO mAcpiBoardInfo;
+ACPI_BOARD_INFO mAcpiBoardInfo;
/**
The constructor function to initialize mAcpiBoardInfo.
@@ -92,23 +92,23 @@ ResetShutdown ( VOID
)
{
- UINTN PmCtrlReg;
+ UINTN PmCtrlReg;
//
// GPE0_EN should be disabled to avoid any GPI waking up the system from S5
//
- IoWrite16 ((UINTN)mAcpiBoardInfo.PmGpeEnBase, 0);
+ IoWrite16 ((UINTN)mAcpiBoardInfo.PmGpeEnBase, 0);
//
// Clear Power Button Status
//
- IoWrite16((UINTN) mAcpiBoardInfo.PmEvtBase, BIT8);
+ IoWrite16 ((UINTN)mAcpiBoardInfo.PmEvtBase, BIT8);
//
// Transform system into S5 sleep state
//
PmCtrlReg = (UINTN)mAcpiBoardInfo.PmCtrlRegBase;
- IoAndThenOr16 (PmCtrlReg, (UINT16) ~0x3c00, (UINT16) (7 << 10));
+ IoAndThenOr16 (PmCtrlReg, (UINT16) ~0x3c00, (UINT16)(7 << 10));
IoOr16 (PmCtrlReg, BIT13);
CpuDeadLoop ();
@@ -129,8 +129,8 @@ ResetShutdown ( VOID
EFIAPI
ResetPlatformSpecific (
- IN UINTN DataSize,
- IN VOID *ResetData
+ IN UINTN DataSize,
+ IN VOID *ResetData
)
{
ResetCold ();
diff --git a/UefiPayloadPkg/Library/SblParseLib/SblParseLib.c b/UefiPayloadPkg/Library/SblParseLib/SblParseLib.c index e524e1b5f6..d88238bfdc 100644 --- a/UefiPayloadPkg/Library/SblParseLib/SblParseLib.c +++ b/UefiPayloadPkg/Library/SblParseLib/SblParseLib.c @@ -33,19 +33,19 @@ GetParameterBase ( VOID
)
{
- EFI_HOB_HANDOFF_INFO_TABLE *HandoffTable;
+ EFI_HOB_HANDOFF_INFO_TABLE *HandoffTable;
- HandoffTable = (EFI_HOB_HANDOFF_INFO_TABLE *)(UINTN) GET_BOOTLOADER_PARAMETER ();
+ HandoffTable = (EFI_HOB_HANDOFF_INFO_TABLE *)(UINTN)GET_BOOTLOADER_PARAMETER ();
if ((HandoffTable->Header.HobType == EFI_HOB_TYPE_HANDOFF) &&
- (HandoffTable->Header.HobLength == sizeof (EFI_HOB_HANDOFF_INFO_TABLE)) &&
- (HandoffTable->Header.Reserved == 0)) {
+ (HandoffTable->Header.HobLength == sizeof (EFI_HOB_HANDOFF_INFO_TABLE)) &&
+ (HandoffTable->Header.Reserved == 0))
+ {
return (VOID *)HandoffTable;
}
return NULL;
}
-
/**
This function retrieves a GUIDed HOB data from Slim Bootloader.
@@ -60,11 +60,11 @@ GetParameterBase ( **/
VOID *
GetGuidHobDataFromSbl (
- IN EFI_GUID *Guid
+ IN EFI_GUID *Guid
)
{
- UINT8 *GuidHob;
- CONST VOID *HobList;
+ UINT8 *GuidHob;
+ CONST VOID *HobList;
HobList = GetParameterBase ();
ASSERT (HobList != NULL);
@@ -89,14 +89,14 @@ GetGuidHobDataFromSbl ( RETURN_STATUS
EFIAPI
ParseMemoryInfo (
- IN BL_MEM_INFO_CALLBACK MemInfoCallback,
- IN VOID *Params
+ IN BL_MEM_INFO_CALLBACK MemInfoCallback,
+ IN VOID *Params
)
{
- MEMORY_MAP_INFO *MemoryMapInfo;
- UINTN Idx;
+ MEMORY_MAP_INFO *MemoryMapInfo;
+ UINTN Idx;
- MemoryMapInfo = (MEMORY_MAP_INFO *) GetGuidHobDataFromSbl (&gLoaderMemoryMapInfoGuid);
+ MemoryMapInfo = (MEMORY_MAP_INFO *)GetGuidHobDataFromSbl (&gLoaderMemoryMapInfoGuid);
if (MemoryMapInfo == NULL) {
ASSERT (FALSE);
return RETURN_NOT_FOUND;
@@ -121,10 +121,10 @@ ParseMemoryInfo ( RETURN_STATUS
EFIAPI
ParseSmbiosTable (
- OUT UNIVERSAL_PAYLOAD_SMBIOS_TABLE *SmbiosTable
+ OUT UNIVERSAL_PAYLOAD_SMBIOS_TABLE *SmbiosTable
)
{
- UNIVERSAL_PAYLOAD_SMBIOS_TABLE *TableInfo;
+ UNIVERSAL_PAYLOAD_SMBIOS_TABLE *TableInfo;
TableInfo = (UNIVERSAL_PAYLOAD_SMBIOS_TABLE *)GetGuidHobDataFromSbl (&gUniversalPayloadSmbiosTableGuid);
if (TableInfo == NULL) {
@@ -137,7 +137,6 @@ ParseSmbiosTable ( return RETURN_SUCCESS;
}
-
/**
Acquire ACPI table from slim bootloader.
@@ -150,10 +149,10 @@ ParseSmbiosTable ( RETURN_STATUS
EFIAPI
ParseAcpiTableInfo (
- OUT UNIVERSAL_PAYLOAD_ACPI_TABLE *AcpiTableHob
+ OUT UNIVERSAL_PAYLOAD_ACPI_TABLE *AcpiTableHob
)
{
- UNIVERSAL_PAYLOAD_ACPI_TABLE *TableInfo;
+ UNIVERSAL_PAYLOAD_ACPI_TABLE *TableInfo;
TableInfo = (UNIVERSAL_PAYLOAD_ACPI_TABLE *)GetGuidHobDataFromSbl (&gUniversalPayloadAcpiTableGuid);
if (TableInfo == NULL) {
@@ -178,12 +177,12 @@ ParseAcpiTableInfo ( RETURN_STATUS
EFIAPI
ParseSerialInfo (
- OUT SERIAL_PORT_INFO *SerialPortInfo
+ OUT SERIAL_PORT_INFO *SerialPortInfo
)
{
- SERIAL_PORT_INFO *BlSerialInfo;
+ SERIAL_PORT_INFO *BlSerialInfo;
- BlSerialInfo = (SERIAL_PORT_INFO *) GetGuidHobDataFromSbl (&gUefiSerialPortInfoGuid);
+ BlSerialInfo = (SERIAL_PORT_INFO *)GetGuidHobDataFromSbl (&gUefiSerialPortInfoGuid);
if (BlSerialInfo == NULL) {
ASSERT (FALSE);
return RETURN_NOT_FOUND;
@@ -194,7 +193,6 @@ ParseSerialInfo ( return RETURN_SUCCESS;
}
-
/**
Find the video frame buffer information
@@ -207,12 +205,12 @@ ParseSerialInfo ( RETURN_STATUS
EFIAPI
ParseGfxInfo (
- OUT EFI_PEI_GRAPHICS_INFO_HOB *GfxInfo
+ OUT EFI_PEI_GRAPHICS_INFO_HOB *GfxInfo
)
{
- EFI_PEI_GRAPHICS_INFO_HOB *BlGfxInfo;
+ EFI_PEI_GRAPHICS_INFO_HOB *BlGfxInfo;
- BlGfxInfo = (EFI_PEI_GRAPHICS_INFO_HOB *) GetGuidHobDataFromSbl (&gEfiGraphicsInfoHobGuid);
+ BlGfxInfo = (EFI_PEI_GRAPHICS_INFO_HOB *)GetGuidHobDataFromSbl (&gEfiGraphicsInfoHobGuid);
if (BlGfxInfo == NULL) {
return RETURN_NOT_FOUND;
}
@@ -234,12 +232,12 @@ ParseGfxInfo ( RETURN_STATUS
EFIAPI
ParseGfxDeviceInfo (
- OUT EFI_PEI_GRAPHICS_DEVICE_INFO_HOB *GfxDeviceInfo
+ OUT EFI_PEI_GRAPHICS_DEVICE_INFO_HOB *GfxDeviceInfo
)
{
- EFI_PEI_GRAPHICS_DEVICE_INFO_HOB *BlGfxDeviceInfo;
+ EFI_PEI_GRAPHICS_DEVICE_INFO_HOB *BlGfxDeviceInfo;
- BlGfxDeviceInfo = (EFI_PEI_GRAPHICS_DEVICE_INFO_HOB *) GetGuidHobDataFromSbl (&gEfiGraphicsDeviceInfoHobGuid);
+ BlGfxDeviceInfo = (EFI_PEI_GRAPHICS_DEVICE_INFO_HOB *)GetGuidHobDataFromSbl (&gEfiGraphicsDeviceInfoHobGuid);
if (BlGfxDeviceInfo == NULL) {
return RETURN_NOT_FOUND;
}
@@ -263,22 +261,22 @@ ParseMiscInfo ( VOID
)
{
- RETURN_STATUS Status;
- UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES *BlRootBridgesHob;
- UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES *PldRootBridgesHob;
-
- Status = RETURN_NOT_FOUND;
- BlRootBridgesHob = (UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES *) GetGuidHobDataFromSbl (
- &gUniversalPayloadPciRootBridgeInfoGuid
- );
+ RETURN_STATUS Status;
+ UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES *BlRootBridgesHob;
+ UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES *PldRootBridgesHob;
+
+ Status = RETURN_NOT_FOUND;
+ BlRootBridgesHob = (UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES *)GetGuidHobDataFromSbl (
+ &gUniversalPayloadPciRootBridgeInfoGuid
+ );
if (BlRootBridgesHob != NULL) {
//
// Migrate bootloader root bridge info hob from bootloader to payload.
//
PldRootBridgesHob = BuildGuidHob (
- &gUniversalPayloadPciRootBridgeInfoGuid,
- BlRootBridgesHob->Header.Length
- );
+ &gUniversalPayloadPciRootBridgeInfoGuid,
+ BlRootBridgesHob->Header.Length
+ );
ASSERT (PldRootBridgesHob != NULL);
if (PldRootBridgesHob != NULL) {
CopyMem (PldRootBridgesHob, BlRootBridgesHob, BlRootBridgesHob->Header.Length);
@@ -291,4 +289,3 @@ ParseMiscInfo ( return Status;
}
-
diff --git a/UefiPayloadPkg/Library/SpiFlashLib/PchSpi.c b/UefiPayloadPkg/Library/SpiFlashLib/PchSpi.c index 1dafce19cb..18f4a0ba3f 100644 --- a/UefiPayloadPkg/Library/SpiFlashLib/PchSpi.c +++ b/UefiPayloadPkg/Library/SpiFlashLib/PchSpi.c @@ -16,7 +16,7 @@ **/
UINT32
AcquireSpiBar0 (
- IN UINTN PchSpiBase
+ IN UINTN PchSpiBase
)
{
return MmioRead32 (PchSpiBase + R_SPI_BASE) & ~(B_SPI_BAR0_MASK);
@@ -30,13 +30,11 @@ AcquireSpiBar0 ( **/
VOID
ReleaseSpiBar0 (
- IN UINTN PchSpiBase
+ IN UINTN PchSpiBase
)
{
}
-
-
/**
This function is to enable/disable BIOS Write Protect in SMM phase.
@@ -45,22 +43,22 @@ ReleaseSpiBar0 ( **/
VOID
CpuSmmDisableBiosWriteProtect (
- IN BOOLEAN EnableSmmSts
+ IN BOOLEAN EnableSmmSts
)
{
- UINT32 Data32;
+ UINT32 Data32;
- if(EnableSmmSts){
+ if (EnableSmmSts) {
//
// Disable BIOS Write Protect in SMM phase.
//
- Data32 = MmioRead32 ((UINTN) (0xFED30880)) | (UINT32) (BIT0);
+ Data32 = MmioRead32 ((UINTN)(0xFED30880)) | (UINT32)(BIT0);
AsmWriteMsr32 (0x000001FE, Data32);
} else {
//
// Enable BIOS Write Protect in SMM phase
//
- Data32 = MmioRead32 ((UINTN) (0xFED30880)) & (UINT32) (~BIT0);
+ Data32 = MmioRead32 ((UINTN)(0xFED30880)) & (UINT32)(~BIT0);
AsmWriteMsr32 (0x000001FE, Data32);
}
@@ -70,7 +68,6 @@ CpuSmmDisableBiosWriteProtect ( Data32 = MmioRead32 (0xFED30880);
}
-
/**
This function is a hook for Spi to disable BIOS Write Protect.
@@ -84,11 +81,10 @@ CpuSmmDisableBiosWriteProtect ( EFI_STATUS
EFIAPI
DisableBiosWriteProtect (
- IN UINTN PchSpiBase,
- IN UINT8 CpuSmmBwp
+ IN UINTN PchSpiBase,
+ IN UINT8 CpuSmmBwp
)
{
-
//
// Write clear BC_SYNC_SS prior to change WPD from 0 to 1.
//
@@ -116,15 +112,14 @@ DisableBiosWriteProtect ( VOID
EFIAPI
EnableBiosWriteProtect (
- IN UINTN PchSpiBase,
- IN UINT8 CpuSmmBwp
+ IN UINTN PchSpiBase,
+ IN UINT8 CpuSmmBwp
)
{
-
//
// Disable the access to the BIOS space for write cycles
//
- MmioAnd8 (PchSpiBase + R_SPI_BCR, (UINT8) (~B_SPI_BCR_BIOSWE));
+ MmioAnd8 (PchSpiBase + R_SPI_BCR, (UINT8)(~B_SPI_BCR_BIOSWE));
if (CpuSmmBwp != 0) {
CpuSmmDisableBiosWriteProtect (FALSE);
@@ -142,16 +137,18 @@ EnableBiosWriteProtect ( **/
UINT8
SaveAndDisableSpiPrefetchCache (
- IN UINTN PchSpiBase
+ IN UINTN PchSpiBase
)
{
- UINT8 BiosCtlSave;
+ UINT8 BiosCtlSave;
BiosCtlSave = MmioRead8 (PchSpiBase + R_SPI_BCR) & B_SPI_BCR_SRC;
- MmioAndThenOr32 (PchSpiBase + R_SPI_BCR, \
- (UINT32) (~B_SPI_BCR_SRC), \
- (UINT32) (V_SPI_BCR_SRC_PREF_DIS_CACHE_DIS << B_SPI_BCR_SRC));
+ MmioAndThenOr32 (
+ PchSpiBase + R_SPI_BCR, \
+ (UINT32)(~B_SPI_BCR_SRC), \
+ (UINT32)(V_SPI_BCR_SRC_PREF_DIS_CACHE_DIS << B_SPI_BCR_SRC)
+ );
return BiosCtlSave;
}
@@ -165,8 +162,8 @@ SaveAndDisableSpiPrefetchCache ( **/
VOID
SetSpiBiosControlRegister (
- IN UINTN PchSpiBase,
- IN UINT8 BiosCtlValue
+ IN UINTN PchSpiBase,
+ IN UINT8 BiosCtlValue
)
{
MmioAndThenOr8 (PchSpiBase + R_SPI_BCR, (UINT8) ~B_SPI_BCR_SRC, BiosCtlValue);
diff --git a/UefiPayloadPkg/Library/SpiFlashLib/RegsSpi.h b/UefiPayloadPkg/Library/SpiFlashLib/RegsSpi.h index 5f22623675..b741904143 100644 --- a/UefiPayloadPkg/Library/SpiFlashLib/RegsSpi.h +++ b/UefiPayloadPkg/Library/SpiFlashLib/RegsSpi.h @@ -9,121 +9,112 @@ #ifndef REGS_SPI_H_
#define REGS_SPI_H_
-#define R_SPI_BASE 0x10 ///< 32-bit Memory Base Address Register
-#define B_SPI_BAR0_MASK 0x0FFF
-#define R_SPI_BCR 0xDC ///< BIOS Control Register
-#define B_SPI_BCR_SRC (BIT3 | BIT2) ///< SPI Read Configuration (SRC)
-#define V_SPI_BCR_SRC_PREF_DIS_CACHE_DIS 0x04 ///< Prefetch Disable, Cache Disable
-#define B_SPI_BCR_SYNC_SS BIT8
-#define B_SPI_BCR_BIOSWE BIT0 ///< Write Protect Disable (WPD)
+#define R_SPI_BASE 0x10 ///< 32-bit Memory Base Address Register
+#define B_SPI_BAR0_MASK 0x0FFF
+#define R_SPI_BCR 0xDC ///< BIOS Control Register
+#define B_SPI_BCR_SRC (BIT3 | BIT2) ///< SPI Read Configuration (SRC)
+#define V_SPI_BCR_SRC_PREF_DIS_CACHE_DIS 0x04 ///< Prefetch Disable, Cache Disable
+#define B_SPI_BCR_SYNC_SS BIT8
+#define B_SPI_BCR_BIOSWE BIT0 ///< Write Protect Disable (WPD)
///
/// SPI Host Interface Registers
-#define R_SPI_HSFS 0x04 ///< Hardware Sequencing Flash Status and Control Register(32bits)
-#define B_SPI_HSFS_FDBC_MASK 0x3F000000 ///< Flash Data Byte Count ( <= 64), Count = (Value in this field) + 1.
-#define N_SPI_HSFS_FDBC 24
-#define B_SPI_HSFS_CYCLE_MASK 0x001E0000 ///< Flash Cycle.
-#define N_SPI_HSFS_CYCLE 17
-#define V_SPI_HSFS_CYCLE_READ 0 ///< Flash Cycle Read
-#define V_SPI_HSFS_CYCLE_WRITE 2 ///< Flash Cycle Write
-#define V_SPI_HSFS_CYCLE_4K_ERASE 3 ///< Flash Cycle 4K Block Erase
-#define V_SPI_HSFS_CYCLE_64K_ERASE 4 ///< Flash Cycle 64K Sector Erase
-#define V_SPI_HSFS_CYCLE_READ_SFDP 5 ///< Flash Cycle Read SFDP
-#define V_SPI_HSFS_CYCLE_READ_JEDEC_ID 6 ///< Flash Cycle Read JEDEC ID
-#define V_SPI_HSFS_CYCLE_WRITE_STATUS 7 ///< Flash Cycle Write Status
-#define V_SPI_HSFS_CYCLE_READ_STATUS 8 ///< Flash Cycle Read Status
-#define B_SPI_HSFS_CYCLE_FGO BIT16 ///< Flash Cycle Go.
-#define B_SPI_HSFS_FDV BIT14 ///< Flash Descriptor Valid
-#define B_SPI_HSFS_SCIP BIT5 ///< SPI Cycle in Progress
-#define B_SPI_HSFS_FCERR BIT1 ///< Flash Cycle Error
-#define B_SPI_HSFS_FDONE BIT0 ///< Flash Cycle Done
-
-
-#define R_SPI_FADDR 0x08 ///< SPI Flash Address
-#define B_SPI_FADDR_MASK 0x07FFFFFF ///< SPI Flash Address Mask (0~26bit)
-
-
-#define R_SPI_FDATA00 0x10 ///< SPI Data 00 (32 bits)
-
-#define R_SPI_FRAP 0x50 ///< SPI Flash Regions Access Permissions Register
-#define B_SPI_FRAP_BRWA_PLATFORM BIT12 //< Region write access for Region4 PlatformData
-#define B_SPI_FRAP_BRWA_GBE BIT11 //< Region write access for Region3 GbE
-#define B_SPI_FRAP_BRWA_SEC BIT10 ///< Region Write Access for Region2 SEC
-#define B_SPI_FRAP_BRWA_BIOS BIT9 ///< Region Write Access for Region1 BIOS
-#define B_SPI_FRAP_BRWA_FLASHD BIT8 ///< Region Write Access for Region0 Flash Descriptor
-#define B_SPI_FRAP_BRRA_PLATFORM BIT4 ///< Region read access for Region4 PlatformData
-#define B_SPI_FRAP_BRRA_GBE BIT3 ///< Region read access for Region3 GbE
-#define B_SPI_FRAP_BRRA_SEC BIT2 ///< Region Read Access for Region2 SEC
-#define B_SPI_FRAP_BRRA_BIOS BIT1 ///< Region Read Access for Region1 BIOS
-#define B_SPI_FRAP_BRRA_FLASHD BIT0 ///< Region Read Access for Region0 Flash Descriptor
-
-
-#define R_SPI_FREG0_FLASHD 0x54 ///< Flash Region 0 (Flash Descriptor) (32bits)
-#define B_SPI_FREG0_LIMIT_MASK 0x7FFF0000 ///< Size, [30:16] here represents limit[26:12]
-#define N_SPI_FREG0_LIMIT 4 ///< Bit 30:16 identifies address bits [26:12]
-#define B_SPI_FREG0_BASE_MASK 0x00007FFF ///< Base, [14:0] here represents base [26:12]
-#define N_SPI_FREG0_BASE 12 ///< Bit 14:0 identifies address bits [26:2]
-
-#define R_SPI_FREG1_BIOS 0x58 ///< Flash Region 1 (BIOS) (32bits)
-#define B_SPI_FREG1_LIMIT_MASK 0x7FFF0000 ///< Size, [30:16] here represents limit[26:12]
-#define N_SPI_FREG1_LIMIT 4 ///< Bit 30:16 identifies address bits [26:12]
-#define B_SPI_FREG1_BASE_MASK 0x00007FFF ///< Base, [14:0] here represents base [26:12]
-#define N_SPI_FREG1_BASE 12 ///< Bit 14:0 identifies address bits [26:2]
-
-#define R_SPI_FREG2_SEC 0x5C ///< Flash Region 2 (SEC) (32bits)
-#define B_SPI_FREG2_LIMIT_MASK 0x7FFF0000 ///< Size, [30:16] here represents limit[26:12]
-#define N_SPI_FREG2_LIMIT 4 //< Bit 30:16 identifies address bits [26:12]
-#define B_SPI_FREG2_BASE_MASK 0x00007FFF ///< Base, [14:0] here represents base [26:12]
-#define N_SPI_FREG2_BASE 12 //< Bit 14:0 identifies address bits [26:2]
-
-#define R_SPI_FREG3_GBE 0x60 //< Flash Region 3(GbE)(32bits)
-#define B_SPI_FREG3_LIMIT_MASK 0x7FFF0000 ///< Size, [30:16] here represents limit[26:12]
-#define N_SPI_FREG3_LIMIT 4 //< Bit 30:16 identifies address bits [26:12]
-#define B_SPI_FREG3_BASE_MASK 0x00007FFF ///< Base, [14:0] here represents base [26:12]
-#define N_SPI_FREG3_BASE 12 //< Bit 14:0 identifies address bits [26:2]
-
-#define R_SPI_FREG4_PLATFORM_DATA 0x64 ///< Flash Region 4 (Platform Data) (32bits)
-#define B_SPI_FREG4_LIMIT_MASK 0x7FFF0000 ///< Size, [30:16] here represents limit[26:12]
-#define N_SPI_FREG4_LIMIT 4 ///< Bit 30:16 identifies address bits [26:12]
-#define B_SPI_FREG4_BASE_MASK 0x00007FFF ///< Base, [14:0] here represents base [26:12]
-#define N_SPI_FREG4_BASE 12 ///< Bit 14:0 identifies address bits [26:2]
-
-
-#define S_SPI_FREGX 4 ///< Size of Flash Region register
-#define B_SPI_FREGX_LIMIT_MASK 0x7FFF0000 ///< Flash Region Limit [30:16] represents [26:12], [11:0] are assumed to be FFFh
-#define N_SPI_FREGX_LIMIT 16 ///< Region limit bit position
-#define N_SPI_FREGX_LIMIT_REPR 12 ///< Region limit bit represents position
-#define B_SPI_FREGX_BASE_MASK 0x00007FFF ///< Flash Region Base, [14:0] represents [26:12]
-
-
-#define R_SPI_FDOC 0xB4 ///< Flash Descriptor Observability Control Register (32 bits)
-#define B_SPI_FDOC_FDSS_MASK (BIT14 | BIT13 | BIT12) ///< Flash Descriptor Section Select
-#define V_SPI_FDOC_FDSS_FSDM 0x0000 ///< Flash Signature and Descriptor Map
-#define V_SPI_FDOC_FDSS_COMP 0x1000 ///< Component
-#define B_SPI_FDOC_FDSI_MASK 0x0FFC ///< Flash Descriptor Section Index
-
-#define R_SPI_FDOD 0xB8 ///< Flash Descriptor Observability Data Register (32 bits)
-
-
-#define R_SPI_LVSCC 0xC4 ///<Vendor Specific Component Capabilities for Component 0 (32 bits)
-#define B_SPI_LVSCC_EO_64K BIT29 ///<< 64k Erase valid (EO_64k_valid)
-
-#define R_SPI_UVSCC 0xC8 ///< Vendor Specific Component Capabilities for Component 1 (32 bits)
-
-
-#define R_SPI_FDBAR_FLASH_MAP0 0x14 ///< Flash MAP 0
-#define N_SPI_FDBAR_NC 8 ///<< Number Of Components
-#define B_SPI_FDBAR_NC 0x00000300 ///< Number Of Components
-
-#define R_SPI_FDBAR_FLASH_MAP1 0x18 ///< Flash MAP 1
-#define B_SPI_FDBAR_FPSBA 0x00FF0000 ///< Flash Strap Base Address
-
+#define R_SPI_HSFS 0x04 ///< Hardware Sequencing Flash Status and Control Register(32bits)
+#define B_SPI_HSFS_FDBC_MASK 0x3F000000 ///< Flash Data Byte Count ( <= 64), Count = (Value in this field) + 1.
+#define N_SPI_HSFS_FDBC 24
+#define B_SPI_HSFS_CYCLE_MASK 0x001E0000 ///< Flash Cycle.
+#define N_SPI_HSFS_CYCLE 17
+#define V_SPI_HSFS_CYCLE_READ 0 ///< Flash Cycle Read
+#define V_SPI_HSFS_CYCLE_WRITE 2 ///< Flash Cycle Write
+#define V_SPI_HSFS_CYCLE_4K_ERASE 3 ///< Flash Cycle 4K Block Erase
+#define V_SPI_HSFS_CYCLE_64K_ERASE 4 ///< Flash Cycle 64K Sector Erase
+#define V_SPI_HSFS_CYCLE_READ_SFDP 5 ///< Flash Cycle Read SFDP
+#define V_SPI_HSFS_CYCLE_READ_JEDEC_ID 6 ///< Flash Cycle Read JEDEC ID
+#define V_SPI_HSFS_CYCLE_WRITE_STATUS 7 ///< Flash Cycle Write Status
+#define V_SPI_HSFS_CYCLE_READ_STATUS 8 ///< Flash Cycle Read Status
+#define B_SPI_HSFS_CYCLE_FGO BIT16 ///< Flash Cycle Go.
+#define B_SPI_HSFS_FDV BIT14 ///< Flash Descriptor Valid
+#define B_SPI_HSFS_SCIP BIT5 ///< SPI Cycle in Progress
+#define B_SPI_HSFS_FCERR BIT1 ///< Flash Cycle Error
+#define B_SPI_HSFS_FDONE BIT0 ///< Flash Cycle Done
+
+#define R_SPI_FADDR 0x08 ///< SPI Flash Address
+#define B_SPI_FADDR_MASK 0x07FFFFFF ///< SPI Flash Address Mask (0~26bit)
+
+#define R_SPI_FDATA00 0x10 ///< SPI Data 00 (32 bits)
+
+#define R_SPI_FRAP 0x50 ///< SPI Flash Regions Access Permissions Register
+#define B_SPI_FRAP_BRWA_PLATFORM BIT12 // < Region write access for Region4 PlatformData
+#define B_SPI_FRAP_BRWA_GBE BIT11 // < Region write access for Region3 GbE
+#define B_SPI_FRAP_BRWA_SEC BIT10 ///< Region Write Access for Region2 SEC
+#define B_SPI_FRAP_BRWA_BIOS BIT9 ///< Region Write Access for Region1 BIOS
+#define B_SPI_FRAP_BRWA_FLASHD BIT8 ///< Region Write Access for Region0 Flash Descriptor
+#define B_SPI_FRAP_BRRA_PLATFORM BIT4 ///< Region read access for Region4 PlatformData
+#define B_SPI_FRAP_BRRA_GBE BIT3 ///< Region read access for Region3 GbE
+#define B_SPI_FRAP_BRRA_SEC BIT2 ///< Region Read Access for Region2 SEC
+#define B_SPI_FRAP_BRRA_BIOS BIT1 ///< Region Read Access for Region1 BIOS
+#define B_SPI_FRAP_BRRA_FLASHD BIT0 ///< Region Read Access for Region0 Flash Descriptor
+
+#define R_SPI_FREG0_FLASHD 0x54 ///< Flash Region 0 (Flash Descriptor) (32bits)
+#define B_SPI_FREG0_LIMIT_MASK 0x7FFF0000 ///< Size, [30:16] here represents limit[26:12]
+#define N_SPI_FREG0_LIMIT 4 ///< Bit 30:16 identifies address bits [26:12]
+#define B_SPI_FREG0_BASE_MASK 0x00007FFF ///< Base, [14:0] here represents base [26:12]
+#define N_SPI_FREG0_BASE 12 ///< Bit 14:0 identifies address bits [26:2]
+
+#define R_SPI_FREG1_BIOS 0x58 ///< Flash Region 1 (BIOS) (32bits)
+#define B_SPI_FREG1_LIMIT_MASK 0x7FFF0000 ///< Size, [30:16] here represents limit[26:12]
+#define N_SPI_FREG1_LIMIT 4 ///< Bit 30:16 identifies address bits [26:12]
+#define B_SPI_FREG1_BASE_MASK 0x00007FFF ///< Base, [14:0] here represents base [26:12]
+#define N_SPI_FREG1_BASE 12 ///< Bit 14:0 identifies address bits [26:2]
+
+#define R_SPI_FREG2_SEC 0x5C ///< Flash Region 2 (SEC) (32bits)
+#define B_SPI_FREG2_LIMIT_MASK 0x7FFF0000 ///< Size, [30:16] here represents limit[26:12]
+#define N_SPI_FREG2_LIMIT 4 // < Bit 30:16 identifies address bits [26:12]
+#define B_SPI_FREG2_BASE_MASK 0x00007FFF ///< Base, [14:0] here represents base [26:12]
+#define N_SPI_FREG2_BASE 12 // < Bit 14:0 identifies address bits [26:2]
+
+#define R_SPI_FREG3_GBE 0x60 // < Flash Region 3(GbE)(32bits)
+#define B_SPI_FREG3_LIMIT_MASK 0x7FFF0000 ///< Size, [30:16] here represents limit[26:12]
+#define N_SPI_FREG3_LIMIT 4 // < Bit 30:16 identifies address bits [26:12]
+#define B_SPI_FREG3_BASE_MASK 0x00007FFF ///< Base, [14:0] here represents base [26:12]
+#define N_SPI_FREG3_BASE 12 // < Bit 14:0 identifies address bits [26:2]
+
+#define R_SPI_FREG4_PLATFORM_DATA 0x64 ///< Flash Region 4 (Platform Data) (32bits)
+#define B_SPI_FREG4_LIMIT_MASK 0x7FFF0000 ///< Size, [30:16] here represents limit[26:12]
+#define N_SPI_FREG4_LIMIT 4 ///< Bit 30:16 identifies address bits [26:12]
+#define B_SPI_FREG4_BASE_MASK 0x00007FFF ///< Base, [14:0] here represents base [26:12]
+#define N_SPI_FREG4_BASE 12 ///< Bit 14:0 identifies address bits [26:2]
+
+#define S_SPI_FREGX 4 ///< Size of Flash Region register
+#define B_SPI_FREGX_LIMIT_MASK 0x7FFF0000 ///< Flash Region Limit [30:16] represents [26:12], [11:0] are assumed to be FFFh
+#define N_SPI_FREGX_LIMIT 16 ///< Region limit bit position
+#define N_SPI_FREGX_LIMIT_REPR 12 ///< Region limit bit represents position
+#define B_SPI_FREGX_BASE_MASK 0x00007FFF ///< Flash Region Base, [14:0] represents [26:12]
+
+#define R_SPI_FDOC 0xB4 ///< Flash Descriptor Observability Control Register (32 bits)
+#define B_SPI_FDOC_FDSS_MASK (BIT14 | BIT13 | BIT12) ///< Flash Descriptor Section Select
+#define V_SPI_FDOC_FDSS_FSDM 0x0000 ///< Flash Signature and Descriptor Map
+#define V_SPI_FDOC_FDSS_COMP 0x1000 ///< Component
+#define B_SPI_FDOC_FDSI_MASK 0x0FFC ///< Flash Descriptor Section Index
+
+#define R_SPI_FDOD 0xB8 ///< Flash Descriptor Observability Data Register (32 bits)
+
+#define R_SPI_LVSCC 0xC4 ///< Vendor Specific Component Capabilities for Component 0 (32 bits)
+#define B_SPI_LVSCC_EO_64K BIT29 ///< < 64k Erase valid (EO_64k_valid)
+
+#define R_SPI_UVSCC 0xC8 ///< Vendor Specific Component Capabilities for Component 1 (32 bits)
+
+#define R_SPI_FDBAR_FLASH_MAP0 0x14 ///< Flash MAP 0
+#define N_SPI_FDBAR_NC 8 ///< < Number Of Components
+#define B_SPI_FDBAR_NC 0x00000300 ///< Number Of Components
+
+#define R_SPI_FDBAR_FLASH_MAP1 0x18 ///< Flash MAP 1
+#define B_SPI_FDBAR_FPSBA 0x00FF0000 ///< Flash Strap Base Address
//
// Flash Component Base Address (FCBA) from Flash Region 0
//
-#define R_SPI_FCBA_FLCOMP 0x00 ///< Flash Components Register
-#define B_SPI_FLCOMP_COMP1_MASK 0x0F ///< Flash Component 1 Density
-
+#define R_SPI_FCBA_FLCOMP 0x00 ///< Flash Components Register
+#define B_SPI_FLCOMP_COMP1_MASK 0x0F ///< Flash Component 1 Density
#endif
diff --git a/UefiPayloadPkg/Library/SpiFlashLib/SpiCommon.h b/UefiPayloadPkg/Library/SpiFlashLib/SpiCommon.h index e4f4ad92e1..95e9b9b1e7 100644 --- a/UefiPayloadPkg/Library/SpiFlashLib/SpiCommon.h +++ b/UefiPayloadPkg/Library/SpiFlashLib/SpiCommon.h @@ -28,8 +28,8 @@ /// Wait Time = 6 seconds = 6000000 microseconds
/// Wait Period = 10 microseconds
///
-#define WAIT_TIME 6000000 ///< Wait Time = 6 seconds = 6000000 microseconds
-#define WAIT_PERIOD 10 ///< Wait Period = 10 microseconds
+#define WAIT_TIME 6000000 ///< Wait Time = 6 seconds = 6000000 microseconds
+#define WAIT_PERIOD 10 ///< Wait Period = 10 microseconds
///
/// Flash cycle Type
@@ -60,20 +60,19 @@ typedef enum { #define SC_SPI_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('P', 'S', 'P', 'I')
typedef struct {
- UINTN Signature;
- EFI_HANDLE Handle;
- UINT32 AcpiTmrReg;
- UINTN PchSpiBase;
- UINT16 RegionPermission;
- UINT32 SfdpVscc0Value;
- UINT32 SfdpVscc1Value;
- UINT32 StrapBaseAddress;
- UINT8 NumberOfComponents;
- UINT16 Flags;
- UINT32 Component1StartAddr;
+ UINTN Signature;
+ EFI_HANDLE Handle;
+ UINT32 AcpiTmrReg;
+ UINTN PchSpiBase;
+ UINT16 RegionPermission;
+ UINT32 SfdpVscc0Value;
+ UINT32 SfdpVscc1Value;
+ UINT32 StrapBaseAddress;
+ UINT8 NumberOfComponents;
+ UINT16 Flags;
+ UINT32 Component1StartAddr;
} SPI_INSTANCE;
-
/**
Acquire SPI MMIO BAR
@@ -84,10 +83,9 @@ typedef struct { **/
UINT32
AcquireSpiBar0 (
- IN UINTN PchSpiBase
+ IN UINTN PchSpiBase
);
-
/**
Release SPI MMIO BAR. Do nothing.
@@ -98,10 +96,9 @@ AcquireSpiBar0 ( **/
VOID
ReleaseSpiBar0 (
- IN UINTN PchSpiBase
+ IN UINTN PchSpiBase
);
-
/**
This function is a hook for Spi to disable BIOS Write Protect
@@ -115,8 +112,8 @@ ReleaseSpiBar0 ( EFI_STATUS
EFIAPI
DisableBiosWriteProtect (
- IN UINTN PchSpiBase,
- IN UINT8 CpuSmmBwp
+ IN UINTN PchSpiBase,
+ IN UINT8 CpuSmmBwp
);
/**
@@ -131,11 +128,10 @@ DisableBiosWriteProtect ( VOID
EFIAPI
EnableBiosWriteProtect (
- IN UINTN PchSpiBase,
- IN UINT8 CpuSmmBwp
+ IN UINTN PchSpiBase,
+ IN UINT8 CpuSmmBwp
);
-
/**
This function disables SPI Prefetching and caching,
and returns previous BIOS Control Register value before disabling.
@@ -147,7 +143,7 @@ EnableBiosWriteProtect ( **/
UINT8
SaveAndDisableSpiPrefetchCache (
- IN UINTN PchSpiBase
+ IN UINTN PchSpiBase
);
/**
@@ -161,11 +157,10 @@ SaveAndDisableSpiPrefetchCache ( **/
VOID
SetSpiBiosControlRegister (
- IN UINTN PchSpiBase,
- IN UINT8 BiosCtlValue
+ IN UINTN PchSpiBase,
+ IN UINT8 BiosCtlValue
);
-
/**
This function sends the programmed SPI command to the slave device.
@@ -201,8 +196,8 @@ SendSpiCmd ( **/
BOOLEAN
WaitForSpiCycleComplete (
- IN UINT32 PchSpiBar0,
- IN BOOLEAN ErrorCheck
+ IN UINT32 PchSpiBar0,
+ IN BOOLEAN ErrorCheck
);
#endif
diff --git a/UefiPayloadPkg/Library/SpiFlashLib/SpiFlashLib.c b/UefiPayloadPkg/Library/SpiFlashLib/SpiFlashLib.c index 3f2db14bf3..22639a748c 100644 --- a/UefiPayloadPkg/Library/SpiFlashLib/SpiFlashLib.c +++ b/UefiPayloadPkg/Library/SpiFlashLib/SpiFlashLib.c @@ -7,7 +7,7 @@ **/
#include "SpiCommon.h"
-SPI_INSTANCE *mSpiInstance = NULL;
+SPI_INSTANCE *mSpiInstance = NULL;
/**
Get SPI Instance from library global data..
@@ -17,20 +17,20 @@ SPI_INSTANCE *mSpiInstance = NULL; SPI_INSTANCE *
GetSpiInstance (
VOID
-)
+ )
{
if (mSpiInstance == NULL) {
- mSpiInstance = AllocatePool (sizeof(SPI_INSTANCE));
+ mSpiInstance = AllocatePool (sizeof (SPI_INSTANCE));
if (mSpiInstance == NULL) {
return NULL;
}
- ZeroMem (mSpiInstance, sizeof(SPI_INSTANCE));
+
+ ZeroMem (mSpiInstance, sizeof (SPI_INSTANCE));
}
return mSpiInstance;
}
-
/**
Initialize an SPI library.
@@ -43,11 +43,11 @@ SpiConstructor ( VOID
)
{
- UINT32 ScSpiBar0;
- UINT8 Comp0Density;
- SPI_INSTANCE *SpiInstance;
- EFI_HOB_GUID_TYPE *GuidHob;
- SPI_FLASH_INFO *SpiFlashInfo;
+ UINT32 ScSpiBar0;
+ UINT8 Comp0Density;
+ SPI_INSTANCE *SpiInstance;
+ EFI_HOB_GUID_TYPE *GuidHob;
+ SPI_FLASH_INFO *SpiFlashInfo;
//
// Find SPI flash hob
@@ -57,7 +57,8 @@ SpiConstructor ( ASSERT (FALSE);
return EFI_NOT_FOUND;
}
- SpiFlashInfo = (SPI_FLASH_INFO *) GET_GUID_HOB_DATA (GuidHob);
+
+ SpiFlashInfo = (SPI_FLASH_INFO *)GET_GUID_HOB_DATA (GuidHob);
//
// Initialize the SPI instance
@@ -66,10 +67,11 @@ SpiConstructor ( if (SpiInstance == NULL) {
return EFI_NOT_FOUND;
}
+
DEBUG ((DEBUG_INFO, "SpiInstance = %08X\n", SpiInstance));
- SpiInstance->Signature = SC_SPI_PRIVATE_DATA_SIGNATURE;
- SpiInstance->Handle = NULL;
+ SpiInstance->Signature = SC_SPI_PRIVATE_DATA_SIGNATURE;
+ SpiInstance->Handle = NULL;
//
// Check the SPI address
@@ -77,9 +79,11 @@ SpiConstructor ( if ((SpiFlashInfo->SpiAddress.AddressSpaceId != EFI_ACPI_3_0_PCI_CONFIGURATION_SPACE) ||
(SpiFlashInfo->SpiAddress.RegisterBitWidth != 32) ||
(SpiFlashInfo->SpiAddress.RegisterBitOffset != 0) ||
- (SpiFlashInfo->SpiAddress.AccessSize != EFI_ACPI_3_0_DWORD)){
+ (SpiFlashInfo->SpiAddress.AccessSize != EFI_ACPI_3_0_DWORD))
+ {
DEBUG ((DEBUG_ERROR, "SPI FLASH HOB is not expected. need check the hob or enhance SPI flash driver.\n"));
}
+
SpiInstance->PchSpiBase = (UINT32)(UINTN)SpiFlashInfo->SpiAddress.Address;
SpiInstance->Flags = SpiFlashInfo->Flags;
DEBUG ((DEBUG_INFO, "PchSpiBase at 0x%x\n", SpiInstance->PchSpiBase));
@@ -106,34 +110,34 @@ SpiConstructor ( //
MmioAndThenOr32 (
ScSpiBar0 + R_SPI_FDOC,
- (UINT32) (~(B_SPI_FDOC_FDSS_MASK | B_SPI_FDOC_FDSI_MASK)),
- (UINT32) (V_SPI_FDOC_FDSS_FSDM | R_SPI_FDBAR_FLASH_MAP0)
+ (UINT32)(~(B_SPI_FDOC_FDSS_MASK | B_SPI_FDOC_FDSI_MASK)),
+ (UINT32)(V_SPI_FDOC_FDSS_FSDM | R_SPI_FDBAR_FLASH_MAP0)
);
//
// Copy Zero based Number Of Components
//
- SpiInstance->NumberOfComponents = (UINT8) ((MmioRead16 (ScSpiBar0 + R_SPI_FDOD) & B_SPI_FDBAR_NC) >> N_SPI_FDBAR_NC);
+ SpiInstance->NumberOfComponents = (UINT8)((MmioRead16 (ScSpiBar0 + R_SPI_FDOD) & B_SPI_FDBAR_NC) >> N_SPI_FDBAR_NC);
MmioAndThenOr32 (
ScSpiBar0 + R_SPI_FDOC,
- (UINT32) (~(B_SPI_FDOC_FDSS_MASK | B_SPI_FDOC_FDSI_MASK)),
- (UINT32) (V_SPI_FDOC_FDSS_COMP | R_SPI_FCBA_FLCOMP)
+ (UINT32)(~(B_SPI_FDOC_FDSS_MASK | B_SPI_FDOC_FDSI_MASK)),
+ (UINT32)(V_SPI_FDOC_FDSS_COMP | R_SPI_FCBA_FLCOMP)
);
//
// Copy Component 0 Density
//
- Comp0Density = (UINT8) MmioRead32 (ScSpiBar0 + R_SPI_FDOD) & B_SPI_FLCOMP_COMP1_MASK;
- SpiInstance->Component1StartAddr = (UINT32) (SIZE_512KB << Comp0Density);
+ Comp0Density = (UINT8)MmioRead32 (ScSpiBar0 + R_SPI_FDOD) & B_SPI_FLCOMP_COMP1_MASK;
+ SpiInstance->Component1StartAddr = (UINT32)(SIZE_512KB << Comp0Density);
//
// Select FLASH_MAP1 to get Flash SC Strap Base Address
//
MmioAndThenOr32 (
(ScSpiBar0 + R_SPI_FDOC),
- (UINT32) (~(B_SPI_FDOC_FDSS_MASK | B_SPI_FDOC_FDSI_MASK)),
- (UINT32) (V_SPI_FDOC_FDSS_FSDM | R_SPI_FDBAR_FLASH_MAP1)
+ (UINT32)(~(B_SPI_FDOC_FDSS_MASK | B_SPI_FDOC_FDSI_MASK)),
+ (UINT32)(V_SPI_FDOC_FDSS_FSDM | R_SPI_FDBAR_FLASH_MAP1)
);
SpiInstance->StrapBaseAddress = MmioRead32 (ScSpiBar0 + R_SPI_FDOD) & B_SPI_FDBAR_FPSBA;
@@ -146,7 +150,6 @@ SpiConstructor ( return EFI_SUCCESS;
}
-
/**
Read data from the flash part.
@@ -169,7 +172,7 @@ SpiFlashRead ( OUT UINT8 *Buffer
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
Status = SendSpiCmd (FlashRegionType, FlashCycleRead, Address, ByteCount, Buffer);
return Status;
@@ -196,7 +199,7 @@ SpiFlashWrite ( IN UINT8 *Buffer
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
Status = SendSpiCmd (FlashRegionType, FlashCycleWrite, Address, ByteCount, Buffer);
return Status;
@@ -221,7 +224,7 @@ SpiFlashErase ( IN UINT32 ByteCount
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
Status = SendSpiCmd (FlashRegionType, FlashCycleErase, Address, ByteCount, NULL);
return Status;
@@ -242,14 +245,14 @@ SpiFlashErase ( EFI_STATUS
EFIAPI
SpiFlashReadSfdp (
- IN UINT8 ComponentNumber,
- IN UINT32 ByteCount,
- OUT UINT8 *SfdpData
+ IN UINT8 ComponentNumber,
+ IN UINT32 ByteCount,
+ OUT UINT8 *SfdpData
)
{
- EFI_STATUS Status;
- UINT32 Address;
- SPI_INSTANCE *SpiInstance;
+ EFI_STATUS Status;
+ UINT32 Address;
+ SPI_INSTANCE *SpiInstance;
SpiInstance = GetSpiInstance ();
if (SpiInstance == NULL) {
@@ -285,14 +288,14 @@ SpiFlashReadSfdp ( EFI_STATUS
EFIAPI
SpiFlashReadJedecId (
- IN UINT8 ComponentNumber,
- IN UINT32 ByteCount,
- OUT UINT8 *JedecId
+ IN UINT8 ComponentNumber,
+ IN UINT32 ByteCount,
+ OUT UINT8 *JedecId
)
{
- EFI_STATUS Status;
- UINT32 Address;
- SPI_INSTANCE *SpiInstance;
+ EFI_STATUS Status;
+ UINT32 Address;
+ SPI_INSTANCE *SpiInstance;
SpiInstance = GetSpiInstance ();
if (SpiInstance == NULL) {
@@ -326,11 +329,11 @@ SpiFlashReadJedecId ( EFI_STATUS
EFIAPI
SpiFlashWriteStatus (
- IN UINT32 ByteCount,
- IN UINT8 *StatusValue
+ IN UINT32 ByteCount,
+ IN UINT8 *StatusValue
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
Status = SendSpiCmd (0, FlashCycleWriteStatus, 0, ByteCount, StatusValue);
return Status;
@@ -349,11 +352,11 @@ SpiFlashWriteStatus ( EFI_STATUS
EFIAPI
SpiFlashReadStatus (
- IN UINT32 ByteCount,
- OUT UINT8 *StatusValue
+ IN UINT32 ByteCount,
+ OUT UINT8 *StatusValue
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
Status = SendSpiCmd (0, FlashCycleReadStatus, 0, ByteCount, StatusValue);
return Status;
@@ -374,14 +377,14 @@ SpiFlashReadStatus ( EFI_STATUS
EFIAPI
SpiReadPchSoftStrap (
- IN UINT32 SoftStrapAddr,
- IN UINT32 ByteCount,
- OUT UINT8 *SoftStrapValue
+ IN UINT32 SoftStrapAddr,
+ IN UINT32 ByteCount,
+ OUT UINT8 *SoftStrapValue
)
{
- UINT32 StrapFlashAddr;
- EFI_STATUS Status;
- SPI_INSTANCE *SpiInstance;
+ UINT32 StrapFlashAddr;
+ EFI_STATUS Status;
+ SPI_INSTANCE *SpiInstance;
SpiInstance = GetSpiInstance ();
if (SpiInstance == NULL) {
@@ -421,28 +424,28 @@ SendSpiCmd ( IN OUT UINT8 *Buffer
)
{
- EFI_STATUS Status;
- UINT32 Index;
- UINTN SpiBaseAddress;
- UINT32 ScSpiBar0;
- UINT32 LimitAddress;
- UINT32 HardwareSpiAddr;
- UINT16 PermissionBit;
- UINT32 SpiDataCount;
- UINT32 FlashCycle;
- UINT8 BiosCtlSave;
- SPI_INSTANCE *SpiInstance;
- UINT32 Data32;
+ EFI_STATUS Status;
+ UINT32 Index;
+ UINTN SpiBaseAddress;
+ UINT32 ScSpiBar0;
+ UINT32 LimitAddress;
+ UINT32 HardwareSpiAddr;
+ UINT16 PermissionBit;
+ UINT32 SpiDataCount;
+ UINT32 FlashCycle;
+ UINT8 BiosCtlSave;
+ SPI_INSTANCE *SpiInstance;
+ UINT32 Data32;
SpiInstance = GetSpiInstance ();
if (SpiInstance == NULL) {
return EFI_DEVICE_ERROR;
}
- Status = EFI_SUCCESS;
- SpiBaseAddress = SpiInstance->PchSpiBase;
- ScSpiBar0 = AcquireSpiBar0 (SpiBaseAddress);
- BiosCtlSave = 0;
+ Status = EFI_SUCCESS;
+ SpiBaseAddress = SpiInstance->PchSpiBase;
+ ScSpiBar0 = AcquireSpiBar0 (SpiBaseAddress);
+ BiosCtlSave = 0;
SpiInstance->RegionPermission = MmioRead16 (ScSpiBar0 + R_SPI_FRAP);
//
@@ -453,6 +456,7 @@ SendSpiCmd ( if (EFI_ERROR (Status)) {
goto SendSpiCmdEnd;
}
+
BiosCtlSave = SaveAndDisableSpiPrefetchCache (SpiBaseAddress);
}
@@ -467,76 +471,81 @@ SendSpiCmd ( HardwareSpiAddr = Address;
if ((FlashCycleType == FlashCycleRead) ||
(FlashCycleType == FlashCycleWrite) ||
- (FlashCycleType == FlashCycleErase)) {
-
+ (FlashCycleType == FlashCycleErase))
+ {
switch (FlashRegionType) {
- case FlashRegionDescriptor:
- if (FlashCycleType == FlashCycleRead) {
- PermissionBit = B_SPI_FRAP_BRRA_FLASHD;
- } else {
- PermissionBit = B_SPI_FRAP_BRWA_FLASHD;
- }
- Data32 = MmioRead32 (ScSpiBar0 + R_SPI_FREG0_FLASHD);
- HardwareSpiAddr += (Data32 & B_SPI_FREG0_BASE_MASK) << N_SPI_FREG0_BASE;
- LimitAddress = (Data32 & B_SPI_FREG0_LIMIT_MASK) >> N_SPI_FREG0_LIMIT;
- break;
+ case FlashRegionDescriptor:
+ if (FlashCycleType == FlashCycleRead) {
+ PermissionBit = B_SPI_FRAP_BRRA_FLASHD;
+ } else {
+ PermissionBit = B_SPI_FRAP_BRWA_FLASHD;
+ }
- case FlashRegionBios:
- if (FlashCycleType == FlashCycleRead) {
- PermissionBit = B_SPI_FRAP_BRRA_BIOS;
- } else {
- PermissionBit = B_SPI_FRAP_BRWA_BIOS;
- }
- Data32 = MmioRead32 (ScSpiBar0 + R_SPI_FREG1_BIOS);
- HardwareSpiAddr += (Data32 & B_SPI_FREG1_BASE_MASK) << N_SPI_FREG1_BASE;
- LimitAddress = (Data32 & B_SPI_FREG1_LIMIT_MASK) >> N_SPI_FREG1_LIMIT;
- break;
+ Data32 = MmioRead32 (ScSpiBar0 + R_SPI_FREG0_FLASHD);
+ HardwareSpiAddr += (Data32 & B_SPI_FREG0_BASE_MASK) << N_SPI_FREG0_BASE;
+ LimitAddress = (Data32 & B_SPI_FREG0_LIMIT_MASK) >> N_SPI_FREG0_LIMIT;
+ break;
- case FlashRegionMe:
- if (FlashCycleType == FlashCycleRead) {
- PermissionBit = B_SPI_FRAP_BRRA_SEC;
- } else {
- PermissionBit = B_SPI_FRAP_BRWA_SEC;
- }
- Data32 = MmioRead32 (ScSpiBar0 + R_SPI_FREG2_SEC);
- HardwareSpiAddr += (Data32 & B_SPI_FREG2_BASE_MASK) << N_SPI_FREG2_BASE;
- LimitAddress = (Data32 & B_SPI_FREG2_LIMIT_MASK) >> N_SPI_FREG2_LIMIT;
- break;
+ case FlashRegionBios:
+ if (FlashCycleType == FlashCycleRead) {
+ PermissionBit = B_SPI_FRAP_BRRA_BIOS;
+ } else {
+ PermissionBit = B_SPI_FRAP_BRWA_BIOS;
+ }
- case FlashRegionGbE:
- if (FlashCycleType == FlashCycleRead) {
- PermissionBit = B_SPI_FRAP_BRRA_GBE;
- } else {
- PermissionBit = B_SPI_FRAP_BRWA_GBE;
- }
- Data32 = MmioRead32 (ScSpiBar0 + R_SPI_FREG3_GBE);
- HardwareSpiAddr += (Data32 & B_SPI_FREG3_BASE_MASK) << N_SPI_FREG3_BASE;
- LimitAddress = (Data32 & B_SPI_FREG3_LIMIT_MASK) >> N_SPI_FREG3_LIMIT;
- break;
+ Data32 = MmioRead32 (ScSpiBar0 + R_SPI_FREG1_BIOS);
+ HardwareSpiAddr += (Data32 & B_SPI_FREG1_BASE_MASK) << N_SPI_FREG1_BASE;
+ LimitAddress = (Data32 & B_SPI_FREG1_LIMIT_MASK) >> N_SPI_FREG1_LIMIT;
+ break;
- case FlashRegionPlatformData:
- if (FlashCycleType == FlashCycleRead) {
- PermissionBit = B_SPI_FRAP_BRRA_PLATFORM;
- } else {
- PermissionBit = B_SPI_FRAP_BRWA_PLATFORM;
- }
- Data32 = MmioRead32 (ScSpiBar0 + R_SPI_FREG4_PLATFORM_DATA);
- HardwareSpiAddr += (Data32 & B_SPI_FREG4_BASE_MASK) << N_SPI_FREG4_BASE;
- LimitAddress = (Data32 & B_SPI_FREG4_LIMIT_MASK) >> N_SPI_FREG4_LIMIT;
- break;
+ case FlashRegionMe:
+ if (FlashCycleType == FlashCycleRead) {
+ PermissionBit = B_SPI_FRAP_BRRA_SEC;
+ } else {
+ PermissionBit = B_SPI_FRAP_BRWA_SEC;
+ }
- case FlashRegionAll:
- //
- // FlashRegionAll indicates address is relative to flash device
- // No error checking for this case
- //
- LimitAddress = 0;
- PermissionBit = 0;
- break;
+ Data32 = MmioRead32 (ScSpiBar0 + R_SPI_FREG2_SEC);
+ HardwareSpiAddr += (Data32 & B_SPI_FREG2_BASE_MASK) << N_SPI_FREG2_BASE;
+ LimitAddress = (Data32 & B_SPI_FREG2_LIMIT_MASK) >> N_SPI_FREG2_LIMIT;
+ break;
- default:
- Status = EFI_UNSUPPORTED;
- goto SendSpiCmdEnd;
+ case FlashRegionGbE:
+ if (FlashCycleType == FlashCycleRead) {
+ PermissionBit = B_SPI_FRAP_BRRA_GBE;
+ } else {
+ PermissionBit = B_SPI_FRAP_BRWA_GBE;
+ }
+
+ Data32 = MmioRead32 (ScSpiBar0 + R_SPI_FREG3_GBE);
+ HardwareSpiAddr += (Data32 & B_SPI_FREG3_BASE_MASK) << N_SPI_FREG3_BASE;
+ LimitAddress = (Data32 & B_SPI_FREG3_LIMIT_MASK) >> N_SPI_FREG3_LIMIT;
+ break;
+
+ case FlashRegionPlatformData:
+ if (FlashCycleType == FlashCycleRead) {
+ PermissionBit = B_SPI_FRAP_BRRA_PLATFORM;
+ } else {
+ PermissionBit = B_SPI_FRAP_BRWA_PLATFORM;
+ }
+
+ Data32 = MmioRead32 (ScSpiBar0 + R_SPI_FREG4_PLATFORM_DATA);
+ HardwareSpiAddr += (Data32 & B_SPI_FREG4_BASE_MASK) << N_SPI_FREG4_BASE;
+ LimitAddress = (Data32 & B_SPI_FREG4_LIMIT_MASK) >> N_SPI_FREG4_LIMIT;
+ break;
+
+ case FlashRegionAll:
+ //
+ // FlashRegionAll indicates address is relative to flash device
+ // No error checking for this case
+ //
+ LimitAddress = 0;
+ PermissionBit = 0;
+ break;
+
+ default:
+ Status = EFI_UNSUPPORTED;
+ goto SendSpiCmdEnd;
}
if ((LimitAddress != 0) && (Address > LimitAddress)) {
@@ -559,47 +568,48 @@ SendSpiCmd ( //
FlashCycle = 0;
switch (FlashCycleType) {
- case FlashCycleRead:
- FlashCycle = (UINT32) (V_SPI_HSFS_CYCLE_READ << N_SPI_HSFS_CYCLE);
- break;
+ case FlashCycleRead:
+ FlashCycle = (UINT32)(V_SPI_HSFS_CYCLE_READ << N_SPI_HSFS_CYCLE);
+ break;
- case FlashCycleWrite:
- FlashCycle = (UINT32) (V_SPI_HSFS_CYCLE_WRITE << N_SPI_HSFS_CYCLE);
- break;
+ case FlashCycleWrite:
+ FlashCycle = (UINT32)(V_SPI_HSFS_CYCLE_WRITE << N_SPI_HSFS_CYCLE);
+ break;
- case FlashCycleErase:
- if (((ByteCount % SIZE_4KB) != 0) || ((HardwareSpiAddr % SIZE_4KB) != 0)) {
- DEBUG ((DEBUG_ERROR, "Erase and erase size must be 4KB aligned. \n"));
- ASSERT (FALSE);
- Status = EFI_INVALID_PARAMETER;
- goto SendSpiCmdEnd;
- }
- break;
+ case FlashCycleErase:
+ if (((ByteCount % SIZE_4KB) != 0) || ((HardwareSpiAddr % SIZE_4KB) != 0)) {
+ DEBUG ((DEBUG_ERROR, "Erase and erase size must be 4KB aligned. \n"));
+ ASSERT (FALSE);
+ Status = EFI_INVALID_PARAMETER;
+ goto SendSpiCmdEnd;
+ }
- case FlashCycleReadSfdp:
- FlashCycle = (UINT32) (V_SPI_HSFS_CYCLE_READ_SFDP << N_SPI_HSFS_CYCLE);
- break;
+ break;
- case FlashCycleReadJedecId:
- FlashCycle = (UINT32) (V_SPI_HSFS_CYCLE_READ_JEDEC_ID << N_SPI_HSFS_CYCLE);
- break;
+ case FlashCycleReadSfdp:
+ FlashCycle = (UINT32)(V_SPI_HSFS_CYCLE_READ_SFDP << N_SPI_HSFS_CYCLE);
+ break;
- case FlashCycleWriteStatus:
- FlashCycle = (UINT32) (V_SPI_HSFS_CYCLE_WRITE_STATUS << N_SPI_HSFS_CYCLE);
- break;
+ case FlashCycleReadJedecId:
+ FlashCycle = (UINT32)(V_SPI_HSFS_CYCLE_READ_JEDEC_ID << N_SPI_HSFS_CYCLE);
+ break;
- case FlashCycleReadStatus:
- FlashCycle = (UINT32) (V_SPI_HSFS_CYCLE_READ_STATUS << N_SPI_HSFS_CYCLE);
- break;
+ case FlashCycleWriteStatus:
+ FlashCycle = (UINT32)(V_SPI_HSFS_CYCLE_WRITE_STATUS << N_SPI_HSFS_CYCLE);
+ break;
- default:
- //
- // Unrecognized Operation
- //
- ASSERT (FALSE);
- Status = EFI_INVALID_PARAMETER;
- goto SendSpiCmdEnd;
- break;
+ case FlashCycleReadStatus:
+ FlashCycle = (UINT32)(V_SPI_HSFS_CYCLE_READ_STATUS << N_SPI_HSFS_CYCLE);
+ break;
+
+ default:
+ //
+ // Unrecognized Operation
+ //
+ ASSERT (FALSE);
+ Status = EFI_INVALID_PARAMETER;
+ goto SendSpiCmdEnd;
+ break;
}
do {
@@ -613,8 +623,9 @@ SendSpiCmd ( // per operation
//
if (HardwareSpiAddr + ByteCount > ((HardwareSpiAddr + BIT8) &~(BIT8 - 1))) {
- SpiDataCount = (((UINT32) (HardwareSpiAddr) + BIT8) &~(BIT8 - 1)) - (UINT32) (HardwareSpiAddr);
+ SpiDataCount = (((UINT32)(HardwareSpiAddr) + BIT8) &~(BIT8 - 1)) - (UINT32)(HardwareSpiAddr);
}
+
//
// Calculate the number of bytes to shift in/out during the SPI data cycle.
// Valid settings for the number of bytes during each data portion of the
@@ -630,7 +641,8 @@ SendSpiCmd ( if (FlashCycleType == FlashCycleErase) {
if (((ByteCount / SIZE_64KB) != 0) &&
((ByteCount % SIZE_64KB) == 0) &&
- ((HardwareSpiAddr % SIZE_64KB) == 0)) {
+ ((HardwareSpiAddr % SIZE_64KB) == 0))
+ {
if (HardwareSpiAddr < SpiInstance->Component1StartAddr) {
//
// Check whether Component0 support 64k Erase
@@ -653,10 +665,11 @@ SendSpiCmd ( } else {
SpiDataCount = SIZE_4KB;
}
+
if (SpiDataCount == SIZE_4KB) {
- FlashCycle = (UINT32) (V_SPI_HSFS_CYCLE_4K_ERASE << N_SPI_HSFS_CYCLE);
+ FlashCycle = (UINT32)(V_SPI_HSFS_CYCLE_4K_ERASE << N_SPI_HSFS_CYCLE);
} else {
- FlashCycle = (UINT32) (V_SPI_HSFS_CYCLE_64K_ERASE << N_SPI_HSFS_CYCLE);
+ FlashCycle = (UINT32)(V_SPI_HSFS_CYCLE_64K_ERASE << N_SPI_HSFS_CYCLE);
}
}
@@ -676,7 +689,7 @@ SendSpiCmd ( // Use Dword write if Data Count is 8, 16, 24, 32, 40, 48, 56, 64
//
for (Index = 0; Index < SpiDataCount; Index += sizeof (UINT32)) {
- MmioWrite32 (ScSpiBar0 + R_SPI_FDATA00 + Index, *(UINT32 *) (Buffer + Index));
+ MmioWrite32 (ScSpiBar0 + R_SPI_FDATA00 + Index, *(UINT32 *)(Buffer + Index));
}
}
}
@@ -684,15 +697,15 @@ SendSpiCmd ( //
// Set the Flash Address
//
- MmioWrite32 (ScSpiBar0 + R_SPI_FADDR, (UINT32) (HardwareSpiAddr & B_SPI_FADDR_MASK));
+ MmioWrite32 (ScSpiBar0 + R_SPI_FADDR, (UINT32)(HardwareSpiAddr & B_SPI_FADDR_MASK));
//
// Set Data count, Flash cycle, and Set Go bit to start a cycle
//
MmioAndThenOr32 (
ScSpiBar0 + R_SPI_HSFS,
- (UINT32) (~(B_SPI_HSFS_FDBC_MASK | B_SPI_HSFS_CYCLE_MASK)),
- (UINT32) (((SpiDataCount - 1) << N_SPI_HSFS_FDBC) | FlashCycle | B_SPI_HSFS_CYCLE_FGO)
+ (UINT32)(~(B_SPI_HSFS_FDBC_MASK | B_SPI_HSFS_CYCLE_MASK)),
+ (UINT32)(((SpiDataCount - 1) << N_SPI_HSFS_FDBC) | FlashCycle | B_SPI_HSFS_CYCLE_FGO)
);
//
@@ -709,7 +722,8 @@ SendSpiCmd ( if ((FlashCycleType == FlashCycleRead) ||
(FlashCycleType == FlashCycleReadSfdp) ||
(FlashCycleType == FlashCycleReadJedecId) ||
- (FlashCycleType == FlashCycleReadStatus)) {
+ (FlashCycleType == FlashCycleReadStatus))
+ {
if ((SpiDataCount & 0x07) != 0) {
//
// Use Byte read if Data Count is 0, 1, 2, 3, 4, 5, 6, 7
@@ -722,7 +736,7 @@ SendSpiCmd ( // Use Dword read if Data Count is 8, 16, 24, 32, 40, 48, 56, 64
//
for (Index = 0; Index < SpiDataCount; Index += sizeof (UINT32)) {
- *(UINT32 *) (Buffer + Index) = MmioRead32 (ScSpiBar0 + R_SPI_FDATA00 + Index);
+ *(UINT32 *)(Buffer + Index) = MmioRead32 (ScSpiBar0 + R_SPI_FDATA00 + Index);
}
}
}
@@ -737,7 +751,7 @@ SendSpiCmdEnd: /// Restore the settings for SPI Prefetching and Caching and enable BIOS Write Protect
///
if ((FlashCycleType == FlashCycleWrite) || (FlashCycleType == FlashCycleErase)) {
- EnableBiosWriteProtect (SpiBaseAddress, mSpiInstance->Flags & FLAGS_SPI_DISABLE_SMM_WRITE_PROTECT);
+ EnableBiosWriteProtect (SpiBaseAddress, mSpiInstance->Flags & FLAGS_SPI_DISABLE_SMM_WRITE_PROTECT);
SetSpiBiosControlRegister (SpiBaseAddress, BiosCtlSave);
}
@@ -758,13 +772,13 @@ SendSpiCmdEnd: **/
BOOLEAN
WaitForSpiCycleComplete (
- IN UINT32 ScSpiBar0,
- IN BOOLEAN ErrorCheck
+ IN UINT32 ScSpiBar0,
+ IN BOOLEAN ErrorCheck
)
{
- UINT64 WaitTicks;
- UINT64 WaitCount;
- UINT32 Data32;
+ UINT64 WaitTicks;
+ UINT64 WaitCount;
+ UINT32 Data32;
//
// Convert the wait period allowed into to tick count
@@ -783,8 +797,10 @@ WaitForSpiCycleComplete ( return TRUE;
}
}
- MicroSecondDelay ( WAIT_PERIOD);
+
+ MicroSecondDelay (WAIT_PERIOD);
}
+
return FALSE;
}
@@ -807,32 +823,34 @@ SpiGetRegionAddress ( OUT UINT32 *RegionSize OPTIONAL
)
{
- UINT32 ScSpiBar0;
- UINT32 ReadValue;
- UINT32 Base;
- SPI_INSTANCE *SpiInstance;
+ UINT32 ScSpiBar0;
+ UINT32 ReadValue;
+ UINT32 Base;
+ SPI_INSTANCE *SpiInstance;
if (FlashRegionType >= FlashRegionMax) {
return EFI_INVALID_PARAMETER;
}
- SpiInstance = GetSpiInstance();
+ SpiInstance = GetSpiInstance ();
if (SpiInstance == NULL) {
return EFI_DEVICE_ERROR;
}
if (FlashRegionType == FlashRegionAll) {
if (BaseAddress != NULL) {
- *BaseAddress = 0;
+ *BaseAddress = 0;
}
+
if (RegionSize != NULL) {
- *RegionSize = SpiInstance->Component1StartAddr;
+ *RegionSize = SpiInstance->Component1StartAddr;
}
+
return EFI_SUCCESS;
}
ScSpiBar0 = AcquireSpiBar0 (SpiInstance->PchSpiBase);
- ReadValue = MmioRead32 (ScSpiBar0 + R_SPI_FREG0_FLASHD + S_SPI_FREGX * (UINT32) FlashRegionType);
+ ReadValue = MmioRead32 (ScSpiBar0 + R_SPI_FREG0_FLASHD + S_SPI_FREGX * (UINT32)FlashRegionType);
ReleaseSpiBar0 (SpiInstance->PchSpiBase);
//
@@ -849,7 +867,7 @@ SpiGetRegionAddress ( if (RegionSize != NULL) {
*RegionSize = ((((ReadValue & B_SPI_FREGX_LIMIT_MASK) >> N_SPI_FREGX_LIMIT) + 1) <<
- N_SPI_FREGX_LIMIT_REPR) - Base;
+ N_SPI_FREGX_LIMIT_REPR) - Base;
}
return EFI_SUCCESS;
|