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| author | Shifei Lu <shifeix.a.lu@intel.com> | 2015-06-11 02:16:41 +0000 |
|---|---|---|
| committer | zwei4 <zwei4@Edk2> | 2015-06-11 02:16:41 +0000 |
| commit | 5374d621c509cbdc22beef7f4cd3526b02c93243 (patch) | |
| tree | e01b2a1813fd75be789e52f37fac4f5934ee2fec /Vlv2DeviceRefCodePkg | |
| parent | 6c988d346b10fdc0d36182fc3e56223ab8b3ffec (diff) | |
| download | edk2-5374d621c509cbdc22beef7f4cd3526b02c93243.tar.gz edk2-5374d621c509cbdc22beef7f4cd3526b02c93243.tar.bz2 edk2-5374d621c509cbdc22beef7f4cd3526b02c93243.zip | |
Add definitions for Protected Region 1 register.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Shifei Lu <shifeix.a.lu@intel.com>
Reviewed-by: David Wei <david.wei@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17617 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'Vlv2DeviceRefCodePkg')
| -rw-r--r-- | Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsSpi.h | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsSpi.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsSpi.h index 132c64b837..7062a09b1b 100644 --- a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsSpi.h +++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsSpi.h @@ -1,6 +1,6 @@ /**
-Copyright (c) 2011 - 2014, Intel Corporation. All rights reserved
+Copyright (c) 2011 - 2015, Intel Corporation. All rights reserved
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License that accompanies this distribution.
@@ -62,6 +62,12 @@ Copyright (c) 2011 - 2014, Intel Corporation. All rights reserved #define B_PCH_SPI_PR0_RPE BIT15 // Read Protection Enable
#define B_PCH_SPI_PR0_PRB_MASK 0x00001FFF // Protected Range Base Mask, [12:0] here represents base limit of address [24:12]
+#define R_PCH_SPI_PR1 0x78 // Protected Region 1 Register
+#define B_PCH_SPI_PR1_WPE BIT31 // Write Protection Enable
+#define B_PCH_SPI_PR1_PRL_MASK 0x1FFF0000 // Protected Range Limit Mask, [28:16] here represents upper limit of address [24:12]
+#define B_PCH_SPI_PR1_RPE BIT15 // Read Protection Enable
+#define B_PCH_SPI_PR1_PRB_MASK 0x00001FFF // Protected Range Base Mask, [12:0] here represents base limit of address [24:12]
+
#define R_PCH_SPI_PREOP 0x94 // Prefix Opcode Configuration Register (16 bits)
#define B_PCH_SPI_PREOP1_MASK 0xFF00 // Prefix Opcode 1 Mask
#define B_PCH_SPI_PREOP0_MASK 0x00FF // Prefix Opcode 0 Mask
|