diff options
| -rw-r--r-- | UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 2 | ||||
| -rw-r--r-- | UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm | 6 | ||||
| -rwxr-xr-x | UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 8 | ||||
| -rw-r--r-- | UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 3 | ||||
| -rw-r--r-- | UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm | 6 |
5 files changed, 16 insertions, 9 deletions
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c index 554629536a..b4ed0a56a8 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c @@ -746,7 +746,7 @@ InitSmmS3ResumeState ( SmmS3ResumeState->SmmS3Cr0 = gSmmCr0;
SmmS3ResumeState->SmmS3Cr3 = Cr3;
- SmmS3ResumeState->SmmS3Cr4 = gSmmCr4;
+ SmmS3ResumeState->SmmS3Cr4 = mSmmCr4;
if (sizeof (UINTN) == sizeof (UINT64)) {
SmmS3ResumeState->Signature = SMM_S3_RESUME_SMM_64;
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm index f7bb9b9a82..bd07a6e4f5 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm @@ -23,7 +23,7 @@ extern ASM_PFX(mRebasedFlag) extern ASM_PFX(mSmmRelocationOriginalAddress)
global ASM_PFX(gPatchSmmCr3)
-global ASM_PFX(gSmmCr4)
+global ASM_PFX(gPatchSmmCr4)
global ASM_PFX(gSmmCr0)
global ASM_PFX(gSmmJmpAddr)
global ASM_PFX(gSmmInitStack)
@@ -53,8 +53,8 @@ ASM_PFX(SmmStartup): ASM_PFX(gPatchSmmCr3):
mov cr3, eax
o32 lgdt [cs:ebp + (ASM_PFX(gcSmiInitGdtr) - ASM_PFX(SmmStartup))]
- DB 0x66, 0xb8 ; mov eax, imm32
-ASM_PFX(gSmmCr4): DD 0
+ mov eax, strict dword 0 ; source operand will be patched
+ASM_PFX(gPatchSmmCr4):
mov cr4, eax
mov ecx, 0xc0000080 ; IA32_EFER MSR
rdmsr
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c index c5b67e3dc0..a3fd796dba 100755 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c @@ -125,6 +125,11 @@ UINTN mSmmCpuSmramRangeCount; UINT8 mPhysicalAddressBits;
+//
+// Control register contents saved for SMM S3 resume state initialization.
+//
+UINT32 mSmmCr4;
+
/**
Initialize IDT to setup exception handlers for SMM.
@@ -407,7 +412,8 @@ SmmRelocateBases ( //
gSmmCr0 = (UINT32)AsmReadCr0 ();
PatchInstructionX86 (gPatchSmmCr3, AsmReadCr3 (), 4);
- gSmmCr4 = (UINT32)AsmReadCr4 ();
+ mSmmCr4 = (UINT32)AsmReadCr4 ();
+ PatchInstructionX86 (gPatchSmmCr4, mSmmCr4, 4);
//
// Patch GDTR for SMM base relocation
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h index a01d0d76d6..8202ce6f86 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h @@ -310,7 +310,8 @@ extern CONST UINT8 gcSmmInitTemplate[]; extern CONST UINT16 gcSmmInitSize;
extern UINT32 gSmmCr0;
X86_ASSEMBLY_PATCH_LABEL gPatchSmmCr3;
-extern UINT32 gSmmCr4;
+extern UINT32 mSmmCr4;
+X86_ASSEMBLY_PATCH_LABEL gPatchSmmCr4;
extern UINTN gSmmInitStack;
/**
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm index 2df22a1f6c..971bd11813 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm @@ -23,7 +23,7 @@ extern ASM_PFX(mRebasedFlag) extern ASM_PFX(mSmmRelocationOriginalAddress)
global ASM_PFX(gPatchSmmCr3)
-global ASM_PFX(gSmmCr4)
+global ASM_PFX(gPatchSmmCr4)
global ASM_PFX(gSmmCr0)
global ASM_PFX(gSmmJmpAddr)
global ASM_PFX(gSmmInitStack)
@@ -51,8 +51,8 @@ ASM_PFX(SmmStartup): ASM_PFX(gPatchSmmCr3):
mov cr3, eax
o32 lgdt [cs:ebp + (ASM_PFX(gcSmiInitGdtr) - ASM_PFX(SmmStartup))]
- DB 0x66, 0xb8 ; mov eax, imm32
-ASM_PFX(gSmmCr4): DD 0
+ mov eax, strict dword 0 ; source operand will be patched
+ASM_PFX(gPatchSmmCr4):
or ah, 2 ; enable XMM registers access
mov cr4, eax
mov ecx, 0xc0000080 ; IA32_EFER MSR
|