diff options
| -rw-r--r-- | ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4.c | 10 | ||||
| -rw-r--r-- | ArmPlatformPkg/Drivers/PL34xDmc/PL341Dmc.c | 26 | ||||
| -rw-r--r-- | ArmPlatformPkg/Include/Drivers/PL341Dmc.h | 24 |
3 files changed, 27 insertions, 33 deletions
diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4.c b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4.c index 17d09a605a..644842f6d6 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4.c +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4.c @@ -29,16 +29,14 @@ // DDR2 timings PL341_DMC_CONFIG DDRTimings = { - .base = ARM_VE_DMC_BASE, - .phy_ctrl_base = 0x0, //There is no DDR2 PHY controller on CTA9 test chip .MaxChip = 1, .IsUserCfg = TRUE, .User0Cfg = 0x7C924924, .User2Cfg = (TC_UIOLHXC_VALUE << TC_UIOLHNC_SHIFT) | (TC_UIOLHXC_VALUE << TC_UIOLHPC_SHIFT) | (0x1 << TC_UIOHOCT_SHIFT) | (0x1 << TC_UIOHSTOP_SHIFT), .HasQos = TRUE, - .refresh_prd = 0x3D0, - .cas_latency = 0x8, - .write_latency = 0x3, + .RefreshPeriod = 0x3D0, + .CasLatency = 0x8, + .WriteLatency = 0x3, .t_mrd = 0x2, .t_ras = 0xA, .t_rc = 0xE, @@ -153,6 +151,6 @@ ArmPlatformInitializeSystemMemory ( VOID ) { - PL341DmcInit(&DDRTimings); + PL341DmcInit(ARM_VE_DMC_BASE, &DDRTimings); PL301AxiInit(ARM_VE_FAXI_BASE); } diff --git a/ArmPlatformPkg/Drivers/PL34xDmc/PL341Dmc.c b/ArmPlatformPkg/Drivers/PL34xDmc/PL341Dmc.c index ae94def765..95f59eb661 100644 --- a/ArmPlatformPkg/Drivers/PL34xDmc/PL341Dmc.c +++ b/ArmPlatformPkg/Drivers/PL34xDmc/PL341Dmc.c @@ -12,8 +12,11 @@ *
**/
+#include <Uefi.h>
+
#include <Library/IoLib.h>
#include <Library/DebugLib.h>
+
#include <Drivers/PL341Dmc.h>
// Macros for writing to DDR2 controller.
@@ -27,15 +30,13 @@ // Initialise PL341 Dynamic Memory Controller
VOID
PL341DmcInit (
- IN PL341_DMC_CONFIG *DmcConfig
+ IN UINTN DmcBase,
+ IN PL341_DMC_CONFIG* DmcConfig
)
{
- UINTN DmcBase;
UINTN Index;
UINT32 Chip;
- DmcBase = DmcConfig->base;
-
// Set config mode
DmcWriteReg(DMC_COMMAND_REG, DMC_COMMAND_CONFIGURE);
@@ -67,9 +68,9 @@ PL341DmcInit ( //
// Initialise memory controlller
//
- DmcWriteReg(DMC_REFRESH_PRD_REG, DmcConfig->refresh_prd);
- DmcWriteReg(DMC_CAS_LATENCY_REG, DmcConfig->cas_latency);
- DmcWriteReg(DMC_WRITE_LATENCY_REG, DmcConfig->write_latency);
+ DmcWriteReg(DMC_REFRESH_PRD_REG, DmcConfig->RefreshPeriod);
+ DmcWriteReg(DMC_CAS_LATENCY_REG, DmcConfig->CasLatency);
+ DmcWriteReg(DMC_WRITE_LATENCY_REG, DmcConfig->WriteLatency);
DmcWriteReg(DMC_T_MRD_REG, DmcConfig->t_mrd);
DmcWriteReg(DMC_T_RAS_REG, DmcConfig->t_ras);
DmcWriteReg(DMC_T_RC_REG, DmcConfig->t_rc);
@@ -96,6 +97,9 @@ PL341DmcInit ( // Set PL341 Memory Config 2
DmcWriteReg(DMC_MEMORY_CFG2_REG, DmcConfig->MemoryCfg2);
+ // Set PL341 Memory Config 3
+ DmcWriteReg(DMC_MEMORY_CFG3_REG, DmcConfig->MemoryCfg3);
+
// Set PL341 Chip Select <n>
DmcWriteReg(DMC_CHIP_0_CFG_REG, DmcConfig->ChipCfg0);
DmcWriteReg(DMC_CHIP_1_CFG_REG, DmcConfig->ChipCfg1);
@@ -107,9 +111,6 @@ PL341DmcInit ( DmcReadReg(DMC_STATUS_REG);
}
- // Set PL341 Memory Config 3
- DmcWriteReg(DMC_MEMORY_CFG3_REG, DmcConfig->MemoryCfg3);
-
if (DmcConfig->IsUserCfg) {
//
// Set Test Chip PHY Registers via PL341 User Config Reg
@@ -210,6 +211,11 @@ PL341DmcInit ( // Set (EMR) extended mode register - OCD Exit
DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) | (0x00090000) |
(1 << DDR_MODESET_SHFT) | (DDR_EMR_OCD_NS << DDR_EMR_OCD_SHIFT) | DmcConfig->ExtModeReg);
+
+ // Delay
+ for (Index = 0; Index < 10; Index++) {
+ DmcReadReg(DMC_STATUS_REG);
+ }
}
// Move DDR2 Controller to Ready state by issueing GO command
diff --git a/ArmPlatformPkg/Include/Drivers/PL341Dmc.h b/ArmPlatformPkg/Include/Drivers/PL341Dmc.h index 461ec16cc2..0227ced454 100644 --- a/ArmPlatformPkg/Include/Drivers/PL341Dmc.h +++ b/ArmPlatformPkg/Include/Drivers/PL341Dmc.h @@ -17,16 +17,14 @@ typedef struct { - UINTN base; // base address for the controller - UINTN phy_ctrl_base; // DDR2 Phy control base UINTN HasQos; // has QoS registers UINTN MaxChip; // number of memory chips accessible BOOLEAN IsUserCfg; UINT32 User0Cfg; UINT32 User2Cfg; - UINT32 refresh_prd; - UINT32 cas_latency; - UINT32 write_latency; + UINT32 RefreshPeriod; + UINT32 CasLatency; + UINT32 WriteLatency; UINT32 t_mrd; UINT32 t_ras; UINT32 t_rc; @@ -245,16 +243,6 @@ typedef struct { #define PHY_PTM_REFCLK_DIV_200_400MHz 0x0 #define PHY_PTM_REFCLK_DIV_400_800MHz 0x1 - -// PHY Reset in SCC - -#define SCC_PHY_RST_REG_OFF 0xA0 -#define SCC_REMAP_REG_OFF 0x00 -#define SCC_PHY_RST0_MASK 1 // Active LOW PHY0 reset -#define SCC_PHY_RST0_SHFT 0 // Active LOW PHY0 reset -#define SCC_PHY_RST1_MASK 0x100 // Active LOW PHY1 reset -#define SCC_PHY_RST1_SHFT 8 // Active LOW PHY1 reset - #define TC_UIOLHNC_MASK 0x000003C0 #define TC_UIOLHNC_SHIFT 0x6 #define TC_UIOLHPC_MASK 0x0000003F @@ -331,8 +319,10 @@ typedef struct { #define DDR2_MR_WR_CYCLES_6 (5 << 9) -VOID PL341DmcInit ( - IN PL341_DMC_CONFIG *config +VOID +PL341DmcInit ( + IN UINTN DmcBase, + IN PL341_DMC_CONFIG* DmcConfig ); VOID PL341DmcPhyInit ( |