diff options
Diffstat (limited to 'ArmPkg/Include')
34 files changed, 1066 insertions, 1085 deletions
diff --git a/ArmPkg/Include/AsmMacroIoLib.h b/ArmPkg/Include/AsmMacroIoLib.h index 6c901ac387..2493a15b7b 100644 --- a/ArmPkg/Include/AsmMacroIoLib.h +++ b/ArmPkg/Include/AsmMacroIoLib.h @@ -9,7 +9,6 @@ **/
-
#ifndef ASM_MACRO_IO_LIB_H_
#define ASM_MACRO_IO_LIB_H_
@@ -20,7 +19,7 @@ .p2align 2 ; \
Name:
-#define ASM_FUNC(Name) _ASM_FUNC(ASM_PFX(Name), .text. ## Name)
+#define ASM_FUNC(Name) _ASM_FUNC(ASM_PFX(Name), .text. ## Name)
#define MOV32(Reg, Val) \
movw Reg, #(Val) & 0xffff ; \
diff --git a/ArmPkg/Include/AsmMacroIoLibV8.h b/ArmPkg/Include/AsmMacroIoLibV8.h index 337d9ae016..2c2b1cabd0 100644 --- a/ArmPkg/Include/AsmMacroIoLibV8.h +++ b/ArmPkg/Include/AsmMacroIoLibV8.h @@ -9,7 +9,6 @@ **/
-
#ifndef ASM_MACRO_IO_LIBV8_H_
#define ASM_MACRO_IO_LIBV8_H_
@@ -24,7 +23,6 @@ cbnz SAFE_XREG, 1f ;\
b . ;// We should never get here
-
// CurrentEL : 0xC = EL3; 8 = EL2; 4 = EL1
// This only selects between EL1 and EL2 and EL3, else we die.
// Provide the Macro with a safe temp xreg to use.
@@ -42,7 +40,7 @@ .type Name, %function ; \
Name:
-#define ASM_FUNC(Name) _ASM_FUNC(ASM_PFX(Name), .text. ## Name)
+#define ASM_FUNC(Name) _ASM_FUNC(ASM_PFX(Name), .text. ## Name)
#define MOV32(Reg, Val) \
movz Reg, (Val) >> 16, lsl #16 ; \
diff --git a/ArmPkg/Include/Chipset/AArch64.h b/ArmPkg/Include/Chipset/AArch64.h index 10aeb9a15a..bfd2859f51 100644 --- a/ArmPkg/Include/Chipset/AArch64.h +++ b/ArmPkg/Include/Chipset/AArch64.h @@ -13,108 +13,108 @@ #include <Chipset/AArch64Mmu.h>
// ARM Interrupt ID in Exception Table
-#define ARM_ARCH_EXCEPTION_IRQ EXCEPT_AARCH64_IRQ
+#define ARM_ARCH_EXCEPTION_IRQ EXCEPT_AARCH64_IRQ
// CPACR - Coprocessor Access Control Register definitions
-#define CPACR_TTA_EN (1UL << 28)
-#define CPACR_FPEN_EL1 (1UL << 20)
-#define CPACR_FPEN_FULL (3UL << 20)
-#define CPACR_CP_FULL_ACCESS 0x300000
+#define CPACR_TTA_EN (1UL << 28)
+#define CPACR_FPEN_EL1 (1UL << 20)
+#define CPACR_FPEN_FULL (3UL << 20)
+#define CPACR_CP_FULL_ACCESS 0x300000
// Coprocessor Trap Register (CPTR)
-#define AARCH64_CPTR_TFP (1 << 10)
+#define AARCH64_CPTR_TFP (1 << 10)
// ID_AA64PFR0 - AArch64 Processor Feature Register 0 definitions
-#define AARCH64_PFR0_FP (0xF << 16)
-#define AARCH64_PFR0_GIC (0xF << 24)
+#define AARCH64_PFR0_FP (0xF << 16)
+#define AARCH64_PFR0_GIC (0xF << 24)
// SCR - Secure Configuration Register definitions
-#define SCR_NS (1 << 0)
-#define SCR_IRQ (1 << 1)
-#define SCR_FIQ (1 << 2)
-#define SCR_EA (1 << 3)
-#define SCR_FW (1 << 4)
-#define SCR_AW (1 << 5)
+#define SCR_NS (1 << 0)
+#define SCR_IRQ (1 << 1)
+#define SCR_FIQ (1 << 2)
+#define SCR_EA (1 << 3)
+#define SCR_FW (1 << 4)
+#define SCR_AW (1 << 5)
// MIDR - Main ID Register definitions
-#define ARM_CPU_TYPE_SHIFT 4
-#define ARM_CPU_TYPE_MASK 0xFFF
-#define ARM_CPU_TYPE_AEMV8 0xD0F
-#define ARM_CPU_TYPE_A53 0xD03
-#define ARM_CPU_TYPE_A57 0xD07
-#define ARM_CPU_TYPE_A72 0xD08
-#define ARM_CPU_TYPE_A15 0xC0F
-#define ARM_CPU_TYPE_A9 0xC09
-#define ARM_CPU_TYPE_A7 0xC07
-#define ARM_CPU_TYPE_A5 0xC05
-
-#define ARM_CPU_REV_MASK ((0xF << 20) | (0xF) )
-#define ARM_CPU_REV(rn, pn) ((((rn) & 0xF) << 20) | ((pn) & 0xF))
+#define ARM_CPU_TYPE_SHIFT 4
+#define ARM_CPU_TYPE_MASK 0xFFF
+#define ARM_CPU_TYPE_AEMV8 0xD0F
+#define ARM_CPU_TYPE_A53 0xD03
+#define ARM_CPU_TYPE_A57 0xD07
+#define ARM_CPU_TYPE_A72 0xD08
+#define ARM_CPU_TYPE_A15 0xC0F
+#define ARM_CPU_TYPE_A9 0xC09
+#define ARM_CPU_TYPE_A7 0xC07
+#define ARM_CPU_TYPE_A5 0xC05
+
+#define ARM_CPU_REV_MASK ((0xF << 20) | (0xF) )
+#define ARM_CPU_REV(rn, pn) ((((rn) & 0xF) << 20) | ((pn) & 0xF))
// Hypervisor Configuration Register
-#define ARM_HCR_FMO BIT3
-#define ARM_HCR_IMO BIT4
-#define ARM_HCR_AMO BIT5
-#define ARM_HCR_TSC BIT19
-#define ARM_HCR_TGE BIT27
+#define ARM_HCR_FMO BIT3
+#define ARM_HCR_IMO BIT4
+#define ARM_HCR_AMO BIT5
+#define ARM_HCR_TSC BIT19
+#define ARM_HCR_TGE BIT27
// Exception Syndrome Register
-#define AARCH64_ESR_EC(Ecr) ((0x3F << 26) & (Ecr))
-#define AARCH64_ESR_ISS(Ecr) ((0x1FFFFFF) & (Ecr))
+#define AARCH64_ESR_EC(Ecr) ((0x3F << 26) & (Ecr))
+#define AARCH64_ESR_ISS(Ecr) ((0x1FFFFFF) & (Ecr))
-#define AARCH64_ESR_EC_SMC32 (0x13 << 26)
-#define AARCH64_ESR_EC_SMC64 (0x17 << 26)
+#define AARCH64_ESR_EC_SMC32 (0x13 << 26)
+#define AARCH64_ESR_EC_SMC64 (0x17 << 26)
// AArch64 Exception Level
-#define AARCH64_EL3 0xC
-#define AARCH64_EL2 0x8
-#define AARCH64_EL1 0x4
+#define AARCH64_EL3 0xC
+#define AARCH64_EL2 0x8
+#define AARCH64_EL1 0x4
// Saved Program Status Register definitions
-#define SPSR_A BIT8
-#define SPSR_I BIT7
-#define SPSR_F BIT6
+#define SPSR_A BIT8
+#define SPSR_I BIT7
+#define SPSR_F BIT6
-#define SPSR_AARCH32 BIT4
+#define SPSR_AARCH32 BIT4
-#define SPSR_AARCH32_MODE_USER 0x0
-#define SPSR_AARCH32_MODE_FIQ 0x1
-#define SPSR_AARCH32_MODE_IRQ 0x2
-#define SPSR_AARCH32_MODE_SVC 0x3
-#define SPSR_AARCH32_MODE_ABORT 0x7
-#define SPSR_AARCH32_MODE_UNDEF 0xB
-#define SPSR_AARCH32_MODE_SYS 0xF
+#define SPSR_AARCH32_MODE_USER 0x0
+#define SPSR_AARCH32_MODE_FIQ 0x1
+#define SPSR_AARCH32_MODE_IRQ 0x2
+#define SPSR_AARCH32_MODE_SVC 0x3
+#define SPSR_AARCH32_MODE_ABORT 0x7
+#define SPSR_AARCH32_MODE_UNDEF 0xB
+#define SPSR_AARCH32_MODE_SYS 0xF
// Counter-timer Hypervisor Control register definitions
-#define CNTHCTL_EL2_EL1PCTEN BIT0
-#define CNTHCTL_EL2_EL1PCEN BIT1
+#define CNTHCTL_EL2_EL1PCTEN BIT0
+#define CNTHCTL_EL2_EL1PCEN BIT1
-#define ARM_VECTOR_TABLE_ALIGNMENT ((1 << 11)-1)
+#define ARM_VECTOR_TABLE_ALIGNMENT ((1 << 11)-1)
// Vector table offset definitions
-#define ARM_VECTOR_CUR_SP0_SYNC 0x000
-#define ARM_VECTOR_CUR_SP0_IRQ 0x080
-#define ARM_VECTOR_CUR_SP0_FIQ 0x100
-#define ARM_VECTOR_CUR_SP0_SERR 0x180
-
-#define ARM_VECTOR_CUR_SPX_SYNC 0x200
-#define ARM_VECTOR_CUR_SPX_IRQ 0x280
-#define ARM_VECTOR_CUR_SPX_FIQ 0x300
-#define ARM_VECTOR_CUR_SPX_SERR 0x380
-
-#define ARM_VECTOR_LOW_A64_SYNC 0x400
-#define ARM_VECTOR_LOW_A64_IRQ 0x480
-#define ARM_VECTOR_LOW_A64_FIQ 0x500
-#define ARM_VECTOR_LOW_A64_SERR 0x580
-
-#define ARM_VECTOR_LOW_A32_SYNC 0x600
-#define ARM_VECTOR_LOW_A32_IRQ 0x680
-#define ARM_VECTOR_LOW_A32_FIQ 0x700
-#define ARM_VECTOR_LOW_A32_SERR 0x780
+#define ARM_VECTOR_CUR_SP0_SYNC 0x000
+#define ARM_VECTOR_CUR_SP0_IRQ 0x080
+#define ARM_VECTOR_CUR_SP0_FIQ 0x100
+#define ARM_VECTOR_CUR_SP0_SERR 0x180
+
+#define ARM_VECTOR_CUR_SPX_SYNC 0x200
+#define ARM_VECTOR_CUR_SPX_IRQ 0x280
+#define ARM_VECTOR_CUR_SPX_FIQ 0x300
+#define ARM_VECTOR_CUR_SPX_SERR 0x380
+
+#define ARM_VECTOR_LOW_A64_SYNC 0x400
+#define ARM_VECTOR_LOW_A64_IRQ 0x480
+#define ARM_VECTOR_LOW_A64_FIQ 0x500
+#define ARM_VECTOR_LOW_A64_SERR 0x580
+
+#define ARM_VECTOR_LOW_A32_SYNC 0x600
+#define ARM_VECTOR_LOW_A32_IRQ 0x680
+#define ARM_VECTOR_LOW_A32_FIQ 0x700
+#define ARM_VECTOR_LOW_A32_SERR 0x780
// The ID_AA64MMFR2_EL1 register was added in ARMv8.2. Since we
// build for ARMv8.0, we need to define the register here.
-#define ID_AA64MMFR2_EL1 S3_0_C0_C7_2
+#define ID_AA64MMFR2_EL1 S3_0_C0_C7_2
#define VECTOR_BASE(tbl) \
.section .text.##tbl##,"ax"; \
@@ -151,7 +151,7 @@ ArmReadTpidrurw ( VOID
EFIAPI
ArmWriteTpidrurw (
- UINTN Value
+ UINTN Value
);
UINTN
@@ -163,7 +163,7 @@ ArmGetTCR ( VOID
EFIAPI
ArmSetTCR (
- UINTN Value
+ UINTN Value
);
UINTN
@@ -175,7 +175,7 @@ ArmGetMAIR ( VOID
EFIAPI
ArmSetMAIR (
- UINTN Value
+ UINTN Value
);
VOID
@@ -210,7 +210,7 @@ ArmDisableAllExceptions ( VOID
ArmWriteHcr (
- IN UINTN Hcr
+ IN UINTN Hcr
);
UINTN
@@ -225,7 +225,7 @@ ArmReadCurrentEL ( UINTN
ArmWriteCptr (
- IN UINT64 Cptr
+ IN UINT64 Cptr
);
UINT32
@@ -235,7 +235,7 @@ ArmReadCntHctl ( VOID
ArmWriteCntHctl (
- IN UINT32 CntHctl
+ IN UINT32 CntHctl
);
#endif // AARCH64_H_
diff --git a/ArmPkg/Include/Chipset/AArch64Mmu.h b/ArmPkg/Include/Chipset/AArch64Mmu.h index fe38ba1c50..2ea2cc0a87 100644 --- a/ArmPkg/Include/Chipset/AArch64Mmu.h +++ b/ArmPkg/Include/Chipset/AArch64Mmu.h @@ -12,12 +12,12 @@ //
// Memory Attribute Indirection register Definitions
//
-#define MAIR_ATTR_DEVICE_MEMORY 0x0ULL
-#define MAIR_ATTR_NORMAL_MEMORY_NON_CACHEABLE 0x44ULL
-#define MAIR_ATTR_NORMAL_MEMORY_WRITE_THROUGH 0xBBULL
-#define MAIR_ATTR_NORMAL_MEMORY_WRITE_BACK 0xFFULL
+#define MAIR_ATTR_DEVICE_MEMORY 0x0ULL
+#define MAIR_ATTR_NORMAL_MEMORY_NON_CACHEABLE 0x44ULL
+#define MAIR_ATTR_NORMAL_MEMORY_WRITE_THROUGH 0xBBULL
+#define MAIR_ATTR_NORMAL_MEMORY_WRITE_BACK 0xFFULL
-#define MAIR_ATTR(n,value) ((value) << (((n) >> 2)*8))
+#define MAIR_ATTR(n, value) ((value) << (((n) >> 2)*8))
//
// Long-descriptor Translation Table format
@@ -27,7 +27,7 @@ // The first offset starts at 12bit. There are 4 levels of 9-bit address range from level 3 to level 0
#define TT_ADDRESS_OFFSET_AT_LEVEL(TableLevel) (12 + ((3 - (TableLevel)) * 9))
-#define TT_BLOCK_ENTRY_SIZE_AT_LEVEL(Level) (1ULL << TT_ADDRESS_OFFSET_AT_LEVEL(Level))
+#define TT_BLOCK_ENTRY_SIZE_AT_LEVEL(Level) (1ULL << TT_ADDRESS_OFFSET_AT_LEVEL(Level))
// Get the associated entry in the given Translation Table
#define TT_GET_ENTRY_FOR_ADDRESS(TranslationTable, Level, Address) \
@@ -35,164 +35,161 @@ // Return the smallest address granularity from the table level.
// The first offset starts at 12bit. There are 4 levels of 9-bit address range from level 3 to level 0
-#define TT_ADDRESS_AT_LEVEL(TableLevel) (1ULL << TT_ADDRESS_OFFSET_AT_LEVEL(TableLevel))
+#define TT_ADDRESS_AT_LEVEL(TableLevel) (1ULL << TT_ADDRESS_OFFSET_AT_LEVEL(TableLevel))
#define TT_LAST_BLOCK_ADDRESS(TranslationTable, EntryCount) \
((UINT64*)((EFI_PHYSICAL_ADDRESS)(TranslationTable) + (((EntryCount) - 1) * sizeof(UINT64))))
// There are 512 entries per table when 4K Granularity
-#define TT_ENTRY_COUNT 512
-#define TT_ALIGNMENT_BLOCK_ENTRY BIT12
-#define TT_ALIGNMENT_DESCRIPTION_TABLE BIT12
-
-#define TT_ADDRESS_MASK_BLOCK_ENTRY (0xFFFFFFFFFULL << 12)
-#define TT_ADDRESS_MASK_DESCRIPTION_TABLE (0xFFFFFFFFFULL << 12)
-
-#define TT_TYPE_MASK 0x3
-#define TT_TYPE_TABLE_ENTRY 0x3
-#define TT_TYPE_BLOCK_ENTRY 0x1
-#define TT_TYPE_BLOCK_ENTRY_LEVEL3 0x3
-
-#define TT_ATTR_INDX_MASK (0x7 << 2)
-#define TT_ATTR_INDX_DEVICE_MEMORY (0x0 << 2)
-#define TT_ATTR_INDX_MEMORY_NON_CACHEABLE (0x1 << 2)
-#define TT_ATTR_INDX_MEMORY_WRITE_THROUGH (0x2 << 2)
-#define TT_ATTR_INDX_MEMORY_WRITE_BACK (0x3 << 2)
-
-#define TT_AP_MASK (0x3UL << 6)
-#define TT_AP_NO_RW (0x0UL << 6)
-#define TT_AP_RW_RW (0x1UL << 6)
-#define TT_AP_NO_RO (0x2UL << 6)
-#define TT_AP_RO_RO (0x3UL << 6)
-
-#define TT_NS BIT5
-#define TT_AF BIT10
-
-#define TT_SH_NON_SHAREABLE (0x0 << 8)
-#define TT_SH_OUTER_SHAREABLE (0x2 << 8)
-#define TT_SH_INNER_SHAREABLE (0x3 << 8)
-#define TT_SH_MASK (0x3 << 8)
-
-#define TT_PXN_MASK BIT53
-#define TT_UXN_MASK BIT54 // EL1&0
-#define TT_XN_MASK BIT54 // EL2 / EL3
-
-#define TT_ATTRIBUTES_MASK ((0xFFFULL << 52) | (0x3FFULL << 2))
-
-#define TT_TABLE_PXN BIT59
-#define TT_TABLE_UXN BIT60 // EL1&0
-#define TT_TABLE_XN BIT60 // EL2 / EL3
-#define TT_TABLE_NS BIT63
-
-#define TT_TABLE_AP_MASK (BIT62 | BIT61)
-#define TT_TABLE_AP_NO_PERMISSION (0x0ULL << 61)
-#define TT_TABLE_AP_EL0_NO_ACCESS (0x1ULL << 61)
-#define TT_TABLE_AP_NO_WRITE_ACCESS (0x2ULL << 61)
+#define TT_ENTRY_COUNT 512
+#define TT_ALIGNMENT_BLOCK_ENTRY BIT12
+#define TT_ALIGNMENT_DESCRIPTION_TABLE BIT12
+
+#define TT_ADDRESS_MASK_BLOCK_ENTRY (0xFFFFFFFFFULL << 12)
+#define TT_ADDRESS_MASK_DESCRIPTION_TABLE (0xFFFFFFFFFULL << 12)
+
+#define TT_TYPE_MASK 0x3
+#define TT_TYPE_TABLE_ENTRY 0x3
+#define TT_TYPE_BLOCK_ENTRY 0x1
+#define TT_TYPE_BLOCK_ENTRY_LEVEL3 0x3
+
+#define TT_ATTR_INDX_MASK (0x7 << 2)
+#define TT_ATTR_INDX_DEVICE_MEMORY (0x0 << 2)
+#define TT_ATTR_INDX_MEMORY_NON_CACHEABLE (0x1 << 2)
+#define TT_ATTR_INDX_MEMORY_WRITE_THROUGH (0x2 << 2)
+#define TT_ATTR_INDX_MEMORY_WRITE_BACK (0x3 << 2)
+
+#define TT_AP_MASK (0x3UL << 6)
+#define TT_AP_NO_RW (0x0UL << 6)
+#define TT_AP_RW_RW (0x1UL << 6)
+#define TT_AP_NO_RO (0x2UL << 6)
+#define TT_AP_RO_RO (0x3UL << 6)
+
+#define TT_NS BIT5
+#define TT_AF BIT10
+
+#define TT_SH_NON_SHAREABLE (0x0 << 8)
+#define TT_SH_OUTER_SHAREABLE (0x2 << 8)
+#define TT_SH_INNER_SHAREABLE (0x3 << 8)
+#define TT_SH_MASK (0x3 << 8)
+
+#define TT_PXN_MASK BIT53
+#define TT_UXN_MASK BIT54 // EL1&0
+#define TT_XN_MASK BIT54 // EL2 / EL3
+
+#define TT_ATTRIBUTES_MASK ((0xFFFULL << 52) | (0x3FFULL << 2))
+
+#define TT_TABLE_PXN BIT59
+#define TT_TABLE_UXN BIT60 // EL1&0
+#define TT_TABLE_XN BIT60 // EL2 / EL3
+#define TT_TABLE_NS BIT63
+
+#define TT_TABLE_AP_MASK (BIT62 | BIT61)
+#define TT_TABLE_AP_NO_PERMISSION (0x0ULL << 61)
+#define TT_TABLE_AP_EL0_NO_ACCESS (0x1ULL << 61)
+#define TT_TABLE_AP_NO_WRITE_ACCESS (0x2ULL << 61)
//
// Translation Control Register
//
-#define TCR_T0SZ_MASK 0x3FUL
-
-#define TCR_PS_4GB (0UL << 16)
-#define TCR_PS_64GB (1UL << 16)
-#define TCR_PS_1TB (2UL << 16)
-#define TCR_PS_4TB (3UL << 16)
-#define TCR_PS_16TB (4UL << 16)
-#define TCR_PS_256TB (5UL << 16)
-
-#define TCR_TG0_4KB (0UL << 14)
-#define TCR_TG1_4KB (2UL << 30)
-
-#define TCR_IPS_4GB (0ULL << 32)
-#define TCR_IPS_64GB (1ULL << 32)
-#define TCR_IPS_1TB (2ULL << 32)
-#define TCR_IPS_4TB (3ULL << 32)
-#define TCR_IPS_16TB (4ULL << 32)
-#define TCR_IPS_256TB (5ULL << 32)
-
-#define TCR_EPD1 (1UL << 23)
-
-#define TTBR_ASID_FIELD (48)
-#define TTBR_ASID_MASK (0xFF << TTBR_ASID_FIELD)
-#define TTBR_BADDR_MASK (0xFFFFFFFFFFFF ) // The width of this field depends on the values in TxSZ. Addr occupies bottom 48bits
-
-#define TCR_EL1_T0SZ_FIELD (0)
-#define TCR_EL1_EPD0_FIELD (7)
-#define TCR_EL1_IRGN0_FIELD (8)
-#define TCR_EL1_ORGN0_FIELD (10)
-#define TCR_EL1_SH0_FIELD (12)
-#define TCR_EL1_TG0_FIELD (14)
-#define TCR_EL1_T1SZ_FIELD (16)
-#define TCR_EL1_A1_FIELD (22)
-#define TCR_EL1_EPD1_FIELD (23)
-#define TCR_EL1_IRGN1_FIELD (24)
-#define TCR_EL1_ORGN1_FIELD (26)
-#define TCR_EL1_SH1_FIELD (28)
-#define TCR_EL1_TG1_FIELD (30)
-#define TCR_EL1_IPS_FIELD (32)
-#define TCR_EL1_AS_FIELD (36)
-#define TCR_EL1_TBI0_FIELD (37)
-#define TCR_EL1_TBI1_FIELD (38)
-#define TCR_EL1_T0SZ_MASK (0x1FUL << TCR_EL1_T0SZ_FIELD)
-#define TCR_EL1_EPD0_MASK (0x01UL << TCR_EL1_EPD0_FIELD)
-#define TCR_EL1_IRGN0_MASK (0x03UL << TCR_EL1_IRGN0_FIELD)
-#define TCR_EL1_ORGN0_MASK (0x03UL << TCR_EL1_ORGN0_FIELD)
-#define TCR_EL1_SH0_MASK (0x03UL << TCR_EL1_SH0_FIELD)
-#define TCR_EL1_TG0_MASK (0x01UL << TCR_EL1_TG0_FIELD)
-#define TCR_EL1_T1SZ_MASK (0x1FUL << TCR_EL1_T1SZ_FIELD)
-#define TCR_EL1_A1_MASK (0x01UL << TCR_EL1_A1_FIELD)
-#define TCR_EL1_EPD1_MASK (0x01UL << TCR_EL1_EPD1_FIELD)
-#define TCR_EL1_IRGN1_MASK (0x03UL << TCR_EL1_IRGN1_FIELD)
-#define TCR_EL1_ORGN1_MASK (0x03UL << TCR_EL1_ORGN1_FIELD)
-#define TCR_EL1_SH1_MASK (0x03UL << TCR_EL1_SH1_FIELD)
-#define TCR_EL1_TG1_MASK (0x01UL << TCR_EL1_TG1_FIELD)
-#define TCR_EL1_IPS_MASK (0x07UL << TCR_EL1_IPS_FIELD)
-#define TCR_EL1_AS_MASK (0x01UL << TCR_EL1_AS_FIELD)
-#define TCR_EL1_TBI0_MASK (0x01UL << TCR_EL1_TBI0_FIELD)
-#define TCR_EL1_TBI1_MASK (0x01UL << TCR_EL1_TBI1_FIELD)
-
-
-#define TCR_EL23_T0SZ_FIELD (0)
-#define TCR_EL23_IRGN0_FIELD (8)
-#define TCR_EL23_ORGN0_FIELD (10)
-#define TCR_EL23_SH0_FIELD (12)
-#define TCR_EL23_TG0_FIELD (14)
-#define TCR_EL23_PS_FIELD (16)
-#define TCR_EL23_T0SZ_MASK (0x1FUL << TCR_EL23_T0SZ_FIELD)
-#define TCR_EL23_IRGN0_MASK (0x03UL << TCR_EL23_IRGN0_FIELD)
-#define TCR_EL23_ORGN0_MASK (0x03UL << TCR_EL23_ORGN0_FIELD)
-#define TCR_EL23_SH0_MASK (0x03UL << TCR_EL23_SH0_FIELD)
-#define TCR_EL23_TG0_MASK (0x01UL << TCR_EL23_TG0_FIELD)
-#define TCR_EL23_PS_MASK (0x07UL << TCR_EL23_PS_FIELD)
-
-
-#define TCR_RGN_OUTER_NON_CACHEABLE (0x0UL << 10)
-#define TCR_RGN_OUTER_WRITE_BACK_ALLOC (0x1UL << 10)
-#define TCR_RGN_OUTER_WRITE_THROUGH (0x2UL << 10)
-#define TCR_RGN_OUTER_WRITE_BACK_NO_ALLOC (0x3UL << 10)
-
-#define TCR_RGN_INNER_NON_CACHEABLE (0x0UL << 8)
-#define TCR_RGN_INNER_WRITE_BACK_ALLOC (0x1UL << 8)
-#define TCR_RGN_INNER_WRITE_THROUGH (0x2UL << 8)
-#define TCR_RGN_INNER_WRITE_BACK_NO_ALLOC (0x3UL << 8)
-
-#define TCR_SH_NON_SHAREABLE (0x0UL << 12)
-#define TCR_SH_OUTER_SHAREABLE (0x2UL << 12)
-#define TCR_SH_INNER_SHAREABLE (0x3UL << 12)
-
-#define TCR_PASZ_32BITS_4GB (0x0UL)
-#define TCR_PASZ_36BITS_64GB (0x1UL)
-#define TCR_PASZ_40BITS_1TB (0x2UL)
-#define TCR_PASZ_42BITS_4TB (0x3UL)
-#define TCR_PASZ_44BITS_16TB (0x4UL)
-#define TCR_PASZ_48BITS_256TB (0x5UL)
+#define TCR_T0SZ_MASK 0x3FUL
+
+#define TCR_PS_4GB (0UL << 16)
+#define TCR_PS_64GB (1UL << 16)
+#define TCR_PS_1TB (2UL << 16)
+#define TCR_PS_4TB (3UL << 16)
+#define TCR_PS_16TB (4UL << 16)
+#define TCR_PS_256TB (5UL << 16)
+
+#define TCR_TG0_4KB (0UL << 14)
+#define TCR_TG1_4KB (2UL << 30)
+
+#define TCR_IPS_4GB (0ULL << 32)
+#define TCR_IPS_64GB (1ULL << 32)
+#define TCR_IPS_1TB (2ULL << 32)
+#define TCR_IPS_4TB (3ULL << 32)
+#define TCR_IPS_16TB (4ULL << 32)
+#define TCR_IPS_256TB (5ULL << 32)
+
+#define TCR_EPD1 (1UL << 23)
+
+#define TTBR_ASID_FIELD (48)
+#define TTBR_ASID_MASK (0xFF << TTBR_ASID_FIELD)
+#define TTBR_BADDR_MASK (0xFFFFFFFFFFFF ) // The width of this field depends on the values in TxSZ. Addr occupies bottom 48bits
+
+#define TCR_EL1_T0SZ_FIELD (0)
+#define TCR_EL1_EPD0_FIELD (7)
+#define TCR_EL1_IRGN0_FIELD (8)
+#define TCR_EL1_ORGN0_FIELD (10)
+#define TCR_EL1_SH0_FIELD (12)
+#define TCR_EL1_TG0_FIELD (14)
+#define TCR_EL1_T1SZ_FIELD (16)
+#define TCR_EL1_A1_FIELD (22)
+#define TCR_EL1_EPD1_FIELD (23)
+#define TCR_EL1_IRGN1_FIELD (24)
+#define TCR_EL1_ORGN1_FIELD (26)
+#define TCR_EL1_SH1_FIELD (28)
+#define TCR_EL1_TG1_FIELD (30)
+#define TCR_EL1_IPS_FIELD (32)
+#define TCR_EL1_AS_FIELD (36)
+#define TCR_EL1_TBI0_FIELD (37)
+#define TCR_EL1_TBI1_FIELD (38)
+#define TCR_EL1_T0SZ_MASK (0x1FUL << TCR_EL1_T0SZ_FIELD)
+#define TCR_EL1_EPD0_MASK (0x01UL << TCR_EL1_EPD0_FIELD)
+#define TCR_EL1_IRGN0_MASK (0x03UL << TCR_EL1_IRGN0_FIELD)
+#define TCR_EL1_ORGN0_MASK (0x03UL << TCR_EL1_ORGN0_FIELD)
+#define TCR_EL1_SH0_MASK (0x03UL << TCR_EL1_SH0_FIELD)
+#define TCR_EL1_TG0_MASK (0x01UL << TCR_EL1_TG0_FIELD)
+#define TCR_EL1_T1SZ_MASK (0x1FUL << TCR_EL1_T1SZ_FIELD)
+#define TCR_EL1_A1_MASK (0x01UL << TCR_EL1_A1_FIELD)
+#define TCR_EL1_EPD1_MASK (0x01UL << TCR_EL1_EPD1_FIELD)
+#define TCR_EL1_IRGN1_MASK (0x03UL << TCR_EL1_IRGN1_FIELD)
+#define TCR_EL1_ORGN1_MASK (0x03UL << TCR_EL1_ORGN1_FIELD)
+#define TCR_EL1_SH1_MASK (0x03UL << TCR_EL1_SH1_FIELD)
+#define TCR_EL1_TG1_MASK (0x01UL << TCR_EL1_TG1_FIELD)
+#define TCR_EL1_IPS_MASK (0x07UL << TCR_EL1_IPS_FIELD)
+#define TCR_EL1_AS_MASK (0x01UL << TCR_EL1_AS_FIELD)
+#define TCR_EL1_TBI0_MASK (0x01UL << TCR_EL1_TBI0_FIELD)
+#define TCR_EL1_TBI1_MASK (0x01UL << TCR_EL1_TBI1_FIELD)
+
+#define TCR_EL23_T0SZ_FIELD (0)
+#define TCR_EL23_IRGN0_FIELD (8)
+#define TCR_EL23_ORGN0_FIELD (10)
+#define TCR_EL23_SH0_FIELD (12)
+#define TCR_EL23_TG0_FIELD (14)
+#define TCR_EL23_PS_FIELD (16)
+#define TCR_EL23_T0SZ_MASK (0x1FUL << TCR_EL23_T0SZ_FIELD)
+#define TCR_EL23_IRGN0_MASK (0x03UL << TCR_EL23_IRGN0_FIELD)
+#define TCR_EL23_ORGN0_MASK (0x03UL << TCR_EL23_ORGN0_FIELD)
+#define TCR_EL23_SH0_MASK (0x03UL << TCR_EL23_SH0_FIELD)
+#define TCR_EL23_TG0_MASK (0x01UL << TCR_EL23_TG0_FIELD)
+#define TCR_EL23_PS_MASK (0x07UL << TCR_EL23_PS_FIELD)
+
+#define TCR_RGN_OUTER_NON_CACHEABLE (0x0UL << 10)
+#define TCR_RGN_OUTER_WRITE_BACK_ALLOC (0x1UL << 10)
+#define TCR_RGN_OUTER_WRITE_THROUGH (0x2UL << 10)
+#define TCR_RGN_OUTER_WRITE_BACK_NO_ALLOC (0x3UL << 10)
+
+#define TCR_RGN_INNER_NON_CACHEABLE (0x0UL << 8)
+#define TCR_RGN_INNER_WRITE_BACK_ALLOC (0x1UL << 8)
+#define TCR_RGN_INNER_WRITE_THROUGH (0x2UL << 8)
+#define TCR_RGN_INNER_WRITE_BACK_NO_ALLOC (0x3UL << 8)
+
+#define TCR_SH_NON_SHAREABLE (0x0UL << 12)
+#define TCR_SH_OUTER_SHAREABLE (0x2UL << 12)
+#define TCR_SH_INNER_SHAREABLE (0x3UL << 12)
+
+#define TCR_PASZ_32BITS_4GB (0x0UL)
+#define TCR_PASZ_36BITS_64GB (0x1UL)
+#define TCR_PASZ_40BITS_1TB (0x2UL)
+#define TCR_PASZ_42BITS_4TB (0x3UL)
+#define TCR_PASZ_44BITS_16TB (0x4UL)
+#define TCR_PASZ_48BITS_256TB (0x5UL)
// The value written to the T*SZ fields are defined as 2^(64-T*SZ). So a 39Bit
// Virtual address range for 512GB of virtual space sets T*SZ to 25
-#define INPUT_ADDRESS_SIZE_TO_TXSZ(a) (64 - a)
+#define INPUT_ADDRESS_SIZE_TO_TXSZ(a) (64 - a)
// Uses LPAE Page Table format
#endif // AARCH64_MMU_H_
-
diff --git a/ArmPkg/Include/Chipset/ArmCortexA5x.h b/ArmPkg/Include/Chipset/ArmCortexA5x.h index e597eee947..cc8b23b964 100644 --- a/ArmPkg/Include/Chipset/ArmCortexA5x.h +++ b/ArmPkg/Include/Chipset/ArmCortexA5x.h @@ -12,7 +12,7 @@ //
// Cortex A5x feature bit definitions
//
-#define A5X_FEATURE_SMP (1 << 6)
+#define A5X_FEATURE_SMP (1 << 6)
//
// Helper functions to access CPU Extended Control Register
@@ -26,19 +26,19 @@ ArmReadCpuExCr ( VOID
EFIAPI
ArmWriteCpuExCr (
- IN UINT64 Val
+ IN UINT64 Val
);
VOID
EFIAPI
ArmSetCpuExCrBit (
- IN UINT64 Bits
+ IN UINT64 Bits
);
VOID
EFIAPI
ArmUnsetCpuExCrBit (
- IN UINT64 Bits
+ IN UINT64 Bits
);
#endif // ARM_CORTEX_A5X_H_
diff --git a/ArmPkg/Include/Chipset/ArmCortexA9.h b/ArmPkg/Include/Chipset/ArmCortexA9.h index cb937ebc8c..a89aeebd4a 100644 --- a/ArmPkg/Include/Chipset/ArmCortexA9.h +++ b/ArmPkg/Include/Chipset/ArmCortexA9.h @@ -26,28 +26,27 @@ //
// Cortex A9 Watchdog
//
-#define ARM_A9_WATCHDOG_REGION 0x600
+#define ARM_A9_WATCHDOG_REGION 0x600
-#define ARM_A9_WATCHDOG_LOAD_REGISTER 0x20
-#define ARM_A9_WATCHDOG_CONTROL_REGISTER 0x28
+#define ARM_A9_WATCHDOG_LOAD_REGISTER 0x20
+#define ARM_A9_WATCHDOG_CONTROL_REGISTER 0x28
-#define ARM_A9_WATCHDOG_WATCHDOG_MODE (1 << 3)
-#define ARM_A9_WATCHDOG_TIMER_MODE (0 << 3)
-#define ARM_A9_WATCHDOG_SINGLE_SHOT (0 << 1)
-#define ARM_A9_WATCHDOG_AUTORELOAD (1 << 1)
-#define ARM_A9_WATCHDOG_ENABLE 1
+#define ARM_A9_WATCHDOG_WATCHDOG_MODE (1 << 3)
+#define ARM_A9_WATCHDOG_TIMER_MODE (0 << 3)
+#define ARM_A9_WATCHDOG_SINGLE_SHOT (0 << 1)
+#define ARM_A9_WATCHDOG_AUTORELOAD (1 << 1)
+#define ARM_A9_WATCHDOG_ENABLE 1
//
// SCU register offsets & masks
//
-#define A9_SCU_CONTROL_OFFSET 0x0
-#define A9_SCU_CONFIG_OFFSET 0x4
-#define A9_SCU_INVALL_OFFSET 0xC
-#define A9_SCU_FILT_START_OFFSET 0x40
-#define A9_SCU_FILT_END_OFFSET 0x44
-#define A9_SCU_SACR_OFFSET 0x50
-#define A9_SCU_SSACR_OFFSET 0x54
-
+#define A9_SCU_CONTROL_OFFSET 0x0
+#define A9_SCU_CONFIG_OFFSET 0x4
+#define A9_SCU_INVALL_OFFSET 0xC
+#define A9_SCU_FILT_START_OFFSET 0x40
+#define A9_SCU_FILT_END_OFFSET 0x44
+#define A9_SCU_SACR_OFFSET 0x50
+#define A9_SCU_SSACR_OFFSET 0x54
UINTN
EFIAPI
@@ -56,4 +55,3 @@ ArmGetScuBaseAddress ( );
#endif // ARM_CORTEX_A9_H_
-
diff --git a/ArmPkg/Include/Chipset/ArmV7.h b/ArmPkg/Include/Chipset/ArmV7.h index 6b20b988e3..94620c087d 100644 --- a/ArmPkg/Include/Chipset/ArmV7.h +++ b/ArmPkg/Include/Chipset/ArmV7.h @@ -13,19 +13,19 @@ #include <Chipset/ArmV7Mmu.h>
// ARM Interrupt ID in Exception Table
-#define ARM_ARCH_EXCEPTION_IRQ EXCEPT_ARM_IRQ
+#define ARM_ARCH_EXCEPTION_IRQ EXCEPT_ARM_IRQ
// ID_PFR1 - ARM Processor Feature Register 1 definitions
-#define ARM_PFR1_SEC (0xFUL << 4)
-#define ARM_PFR1_TIMER (0xFUL << 16)
-#define ARM_PFR1_GIC (0xFUL << 28)
+#define ARM_PFR1_SEC (0xFUL << 4)
+#define ARM_PFR1_TIMER (0xFUL << 16)
+#define ARM_PFR1_GIC (0xFUL << 28)
// Domain Access Control Register
-#define DOMAIN_ACCESS_CONTROL_MASK(a) (3UL << (2 * (a)))
-#define DOMAIN_ACCESS_CONTROL_NONE(a) (0UL << (2 * (a)))
-#define DOMAIN_ACCESS_CONTROL_CLIENT(a) (1UL << (2 * (a)))
-#define DOMAIN_ACCESS_CONTROL_RESERVED(a) (2UL << (2 * (a)))
-#define DOMAIN_ACCESS_CONTROL_MANAGER(a) (3UL << (2 * (a)))
+#define DOMAIN_ACCESS_CONTROL_MASK(a) (3UL << (2 * (a)))
+#define DOMAIN_ACCESS_CONTROL_NONE(a) (0UL << (2 * (a)))
+#define DOMAIN_ACCESS_CONTROL_CLIENT(a) (1UL << (2 * (a)))
+#define DOMAIN_ACCESS_CONTROL_RESERVED(a) (2UL << (2 * (a)))
+#define DOMAIN_ACCESS_CONTROL_MANAGER(a) (3UL << (2 * (a)))
// CPSR - Coprocessor Status Register definitions
#define CPSR_MODE_USER 0x10
@@ -41,48 +41,47 @@ #define CPSR_IRQ (1 << 7)
#define CPSR_FIQ (1 << 6)
-
// CPACR - Coprocessor Access Control Register definitions
-#define CPACR_CP_DENIED(cp) 0x00
-#define CPACR_CP_PRIV(cp) ((0x1 << ((cp) << 1)) & 0x0FFFFFFF)
-#define CPACR_CP_FULL(cp) ((0x3 << ((cp) << 1)) & 0x0FFFFFFF)
-#define CPACR_ASEDIS (1 << 31)
-#define CPACR_D32DIS (1 << 30)
-#define CPACR_CP_FULL_ACCESS 0x0FFFFFFF
+#define CPACR_CP_DENIED(cp) 0x00
+#define CPACR_CP_PRIV(cp) ((0x1 << ((cp) << 1)) & 0x0FFFFFFF)
+#define CPACR_CP_FULL(cp) ((0x3 << ((cp) << 1)) & 0x0FFFFFFF)
+#define CPACR_ASEDIS (1 << 31)
+#define CPACR_D32DIS (1 << 30)
+#define CPACR_CP_FULL_ACCESS 0x0FFFFFFF
// NSACR - Non-Secure Access Control Register definitions
-#define NSACR_CP(cp) ((1 << (cp)) & 0x3FFF)
-#define NSACR_NSD32DIS (1 << 14)
-#define NSACR_NSASEDIS (1 << 15)
-#define NSACR_PLE (1 << 16)
-#define NSACR_TL (1 << 17)
-#define NSACR_NS_SMP (1 << 18)
-#define NSACR_RFR (1 << 19)
+#define NSACR_CP(cp) ((1 << (cp)) & 0x3FFF)
+#define NSACR_NSD32DIS (1 << 14)
+#define NSACR_NSASEDIS (1 << 15)
+#define NSACR_PLE (1 << 16)
+#define NSACR_TL (1 << 17)
+#define NSACR_NS_SMP (1 << 18)
+#define NSACR_RFR (1 << 19)
// SCR - Secure Configuration Register definitions
-#define SCR_NS (1 << 0)
-#define SCR_IRQ (1 << 1)
-#define SCR_FIQ (1 << 2)
-#define SCR_EA (1 << 3)
-#define SCR_FW (1 << 4)
-#define SCR_AW (1 << 5)
+#define SCR_NS (1 << 0)
+#define SCR_IRQ (1 << 1)
+#define SCR_FIQ (1 << 2)
+#define SCR_EA (1 << 3)
+#define SCR_FW (1 << 4)
+#define SCR_AW (1 << 5)
// MIDR - Main ID Register definitions
-#define ARM_CPU_TYPE_SHIFT 4
-#define ARM_CPU_TYPE_MASK 0xFFF
-#define ARM_CPU_TYPE_AEMV8 0xD0F
-#define ARM_CPU_TYPE_A53 0xD03
-#define ARM_CPU_TYPE_A57 0xD07
-#define ARM_CPU_TYPE_A15 0xC0F
-#define ARM_CPU_TYPE_A12 0xC0D
-#define ARM_CPU_TYPE_A9 0xC09
-#define ARM_CPU_TYPE_A7 0xC07
-#define ARM_CPU_TYPE_A5 0xC05
-
-#define ARM_CPU_REV_MASK ((0xF << 20) | (0xF) )
-#define ARM_CPU_REV(rn, pn) ((((rn) & 0xF) << 20) | ((pn) & 0xF))
-
-#define ARM_VECTOR_TABLE_ALIGNMENT ((1 << 5)-1)
+#define ARM_CPU_TYPE_SHIFT 4
+#define ARM_CPU_TYPE_MASK 0xFFF
+#define ARM_CPU_TYPE_AEMV8 0xD0F
+#define ARM_CPU_TYPE_A53 0xD03
+#define ARM_CPU_TYPE_A57 0xD07
+#define ARM_CPU_TYPE_A15 0xC0F
+#define ARM_CPU_TYPE_A12 0xC0D
+#define ARM_CPU_TYPE_A9 0xC09
+#define ARM_CPU_TYPE_A7 0xC07
+#define ARM_CPU_TYPE_A5 0xC05
+
+#define ARM_CPU_REV_MASK ((0xF << 20) | (0xF) )
+#define ARM_CPU_REV(rn, pn) ((((rn) & 0xF) << 20) | ((pn) & 0xF))
+
+#define ARM_VECTOR_TABLE_ALIGNMENT ((1 << 5)-1)
VOID
EFIAPI
@@ -105,7 +104,7 @@ ArmReadTpidrurw ( VOID
EFIAPI
ArmWriteTpidrurw (
- UINTN Value
+ UINTN Value
);
UINT32
@@ -117,7 +116,7 @@ ArmReadNsacr ( VOID
EFIAPI
ArmWriteNsacr (
- IN UINT32 Nsacr
+ IN UINT32 Nsacr
);
#endif // ARM_V7_H_
diff --git a/ArmPkg/Include/Chipset/ArmV7Mmu.h b/ArmPkg/Include/Chipset/ArmV7Mmu.h index 87c443df3f..db99527d6e 100644 --- a/ArmPkg/Include/Chipset/ArmV7Mmu.h +++ b/ArmPkg/Include/Chipset/ArmV7Mmu.h @@ -9,183 +9,182 @@ #ifndef ARMV7_MMU_H_
#define ARMV7_MMU_H_
-#define TTBR_NOT_OUTER_SHAREABLE BIT5
-#define TTBR_RGN_OUTER_NON_CACHEABLE 0
-#define TTBR_RGN_OUTER_WRITE_BACK_ALLOC BIT3
-#define TTBR_RGN_OUTER_WRITE_THROUGH BIT4
-#define TTBR_RGN_OUTER_WRITE_BACK_NO_ALLOC (BIT3|BIT4)
-#define TTBR_SHAREABLE BIT1
-#define TTBR_NON_SHAREABLE 0
-#define TTBR_INNER_CACHEABLE BIT0
-#define TTBR_INNER_NON_CACHEABLE 0
-#define TTBR_RGN_INNER_NON_CACHEABLE 0
-#define TTBR_RGN_INNER_WRITE_BACK_ALLOC BIT6
-#define TTBR_RGN_INNER_WRITE_THROUGH BIT0
-#define TTBR_RGN_INNER_WRITE_BACK_NO_ALLOC (BIT0|BIT6)
-
-#define TTBR_WRITE_THROUGH ( TTBR_RGN_OUTER_WRITE_THROUGH | TTBR_INNER_CACHEABLE | TTBR_SHAREABLE)
-#define TTBR_WRITE_BACK_NO_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_NO_ALLOC | TTBR_INNER_CACHEABLE | TTBR_SHAREABLE)
-#define TTBR_NON_CACHEABLE ( TTBR_RGN_OUTER_NON_CACHEABLE | TTBR_INNER_NON_CACHEABLE )
-#define TTBR_WRITE_BACK_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_ALLOC | TTBR_INNER_CACHEABLE | TTBR_SHAREABLE)
-
-#define TTBR_MP_WRITE_THROUGH ( TTBR_RGN_OUTER_WRITE_THROUGH | TTBR_RGN_INNER_WRITE_THROUGH | TTBR_SHAREABLE)
-#define TTBR_MP_WRITE_BACK_NO_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_NO_ALLOC | TTBR_RGN_INNER_WRITE_BACK_NO_ALLOC | TTBR_SHAREABLE)
-#define TTBR_MP_NON_CACHEABLE ( TTBR_RGN_OUTER_NON_CACHEABLE | TTBR_RGN_INNER_NON_CACHEABLE )
-#define TTBR_MP_WRITE_BACK_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_ALLOC | TTBR_RGN_INNER_WRITE_BACK_ALLOC | TTBR_SHAREABLE)
-
-
-#define TRANSLATION_TABLE_SECTION_COUNT 4096
-#define TRANSLATION_TABLE_SECTION_SIZE (sizeof(UINT32) * TRANSLATION_TABLE_SECTION_COUNT)
-#define TRANSLATION_TABLE_SECTION_ALIGNMENT (sizeof(UINT32) * TRANSLATION_TABLE_SECTION_COUNT)
-#define TRANSLATION_TABLE_SECTION_ALIGNMENT_MASK (TRANSLATION_TABLE_SECTION_ALIGNMENT - 1)
-
-#define TRANSLATION_TABLE_PAGE_COUNT 256
-#define TRANSLATION_TABLE_PAGE_SIZE (sizeof(UINT32) * TRANSLATION_TABLE_PAGE_COUNT)
-#define TRANSLATION_TABLE_PAGE_ALIGNMENT (sizeof(UINT32) * TRANSLATION_TABLE_PAGE_COUNT)
-#define TRANSLATION_TABLE_PAGE_ALIGNMENT_MASK (TRANSLATION_TABLE_PAGE_ALIGNMENT - 1)
-
-#define TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(table, address) ((UINT32 *)(table) + (((UINTN)(address)) >> 20))
+#define TTBR_NOT_OUTER_SHAREABLE BIT5
+#define TTBR_RGN_OUTER_NON_CACHEABLE 0
+#define TTBR_RGN_OUTER_WRITE_BACK_ALLOC BIT3
+#define TTBR_RGN_OUTER_WRITE_THROUGH BIT4
+#define TTBR_RGN_OUTER_WRITE_BACK_NO_ALLOC (BIT3|BIT4)
+#define TTBR_SHAREABLE BIT1
+#define TTBR_NON_SHAREABLE 0
+#define TTBR_INNER_CACHEABLE BIT0
+#define TTBR_INNER_NON_CACHEABLE 0
+#define TTBR_RGN_INNER_NON_CACHEABLE 0
+#define TTBR_RGN_INNER_WRITE_BACK_ALLOC BIT6
+#define TTBR_RGN_INNER_WRITE_THROUGH BIT0
+#define TTBR_RGN_INNER_WRITE_BACK_NO_ALLOC (BIT0|BIT6)
+
+#define TTBR_WRITE_THROUGH ( TTBR_RGN_OUTER_WRITE_THROUGH | TTBR_INNER_CACHEABLE | TTBR_SHAREABLE)
+#define TTBR_WRITE_BACK_NO_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_NO_ALLOC | TTBR_INNER_CACHEABLE | TTBR_SHAREABLE)
+#define TTBR_NON_CACHEABLE ( TTBR_RGN_OUTER_NON_CACHEABLE | TTBR_INNER_NON_CACHEABLE )
+#define TTBR_WRITE_BACK_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_ALLOC | TTBR_INNER_CACHEABLE | TTBR_SHAREABLE)
+
+#define TTBR_MP_WRITE_THROUGH ( TTBR_RGN_OUTER_WRITE_THROUGH | TTBR_RGN_INNER_WRITE_THROUGH | TTBR_SHAREABLE)
+#define TTBR_MP_WRITE_BACK_NO_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_NO_ALLOC | TTBR_RGN_INNER_WRITE_BACK_NO_ALLOC | TTBR_SHAREABLE)
+#define TTBR_MP_NON_CACHEABLE ( TTBR_RGN_OUTER_NON_CACHEABLE | TTBR_RGN_INNER_NON_CACHEABLE )
+#define TTBR_MP_WRITE_BACK_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_ALLOC | TTBR_RGN_INNER_WRITE_BACK_ALLOC | TTBR_SHAREABLE)
+
+#define TRANSLATION_TABLE_SECTION_COUNT 4096
+#define TRANSLATION_TABLE_SECTION_SIZE (sizeof(UINT32) * TRANSLATION_TABLE_SECTION_COUNT)
+#define TRANSLATION_TABLE_SECTION_ALIGNMENT (sizeof(UINT32) * TRANSLATION_TABLE_SECTION_COUNT)
+#define TRANSLATION_TABLE_SECTION_ALIGNMENT_MASK (TRANSLATION_TABLE_SECTION_ALIGNMENT - 1)
+
+#define TRANSLATION_TABLE_PAGE_COUNT 256
+#define TRANSLATION_TABLE_PAGE_SIZE (sizeof(UINT32) * TRANSLATION_TABLE_PAGE_COUNT)
+#define TRANSLATION_TABLE_PAGE_ALIGNMENT (sizeof(UINT32) * TRANSLATION_TABLE_PAGE_COUNT)
+#define TRANSLATION_TABLE_PAGE_ALIGNMENT_MASK (TRANSLATION_TABLE_PAGE_ALIGNMENT - 1)
+
+#define TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(table, address) ((UINT32 *)(table) + (((UINTN)(address)) >> 20))
// Translation table descriptor types
-#define TT_DESCRIPTOR_SECTION_TYPE_MASK ((1UL << 18) | (3UL << 0))
-#define TT_DESCRIPTOR_SECTION_TYPE_FAULT (0UL << 0)
-#define TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE (1UL << 0)
-#define TT_DESCRIPTOR_SECTION_TYPE_SECTION ((0UL << 18) | (2UL << 0))
-#define TT_DESCRIPTOR_SECTION_TYPE_SUPERSECTION ((1UL << 18) | (2UL << 0))
-#define TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(Desc) (((Desc) & 3UL) == TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE)
+#define TT_DESCRIPTOR_SECTION_TYPE_MASK ((1UL << 18) | (3UL << 0))
+#define TT_DESCRIPTOR_SECTION_TYPE_FAULT (0UL << 0)
+#define TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE (1UL << 0)
+#define TT_DESCRIPTOR_SECTION_TYPE_SECTION ((0UL << 18) | (2UL << 0))
+#define TT_DESCRIPTOR_SECTION_TYPE_SUPERSECTION ((1UL << 18) | (2UL << 0))
+#define TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(Desc) (((Desc) & 3UL) == TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE)
// Translation table descriptor types
-#define TT_DESCRIPTOR_PAGE_TYPE_MASK (3UL << 0)
-#define TT_DESCRIPTOR_PAGE_TYPE_FAULT (0UL << 0)
-#define TT_DESCRIPTOR_PAGE_TYPE_PAGE (2UL << 0)
-#define TT_DESCRIPTOR_PAGE_TYPE_PAGE_XN (3UL << 0)
-#define TT_DESCRIPTOR_PAGE_TYPE_LARGEPAGE (1UL << 0)
+#define TT_DESCRIPTOR_PAGE_TYPE_MASK (3UL << 0)
+#define TT_DESCRIPTOR_PAGE_TYPE_FAULT (0UL << 0)
+#define TT_DESCRIPTOR_PAGE_TYPE_PAGE (2UL << 0)
+#define TT_DESCRIPTOR_PAGE_TYPE_PAGE_XN (3UL << 0)
+#define TT_DESCRIPTOR_PAGE_TYPE_LARGEPAGE (1UL << 0)
// Section descriptor definitions
-#define TT_DESCRIPTOR_SECTION_SIZE (0x00100000)
-
-#define TT_DESCRIPTOR_SECTION_NS_MASK (1UL << 19)
-#define TT_DESCRIPTOR_SECTION_NS (1UL << 19)
-
-#define TT_DESCRIPTOR_SECTION_NG_MASK (1UL << 17)
-#define TT_DESCRIPTOR_SECTION_NG_GLOBAL (0UL << 17)
-#define TT_DESCRIPTOR_SECTION_NG_LOCAL (1UL << 17)
-
-#define TT_DESCRIPTOR_PAGE_NG_MASK (1UL << 11)
-#define TT_DESCRIPTOR_PAGE_NG_GLOBAL (0UL << 11)
-#define TT_DESCRIPTOR_PAGE_NG_LOCAL (1UL << 11)
-
-#define TT_DESCRIPTOR_SECTION_S_MASK (1UL << 16)
-#define TT_DESCRIPTOR_SECTION_S_NOT_SHARED (0UL << 16)
-#define TT_DESCRIPTOR_SECTION_S_SHARED (1UL << 16)
-
-#define TT_DESCRIPTOR_PAGE_S_MASK (1UL << 10)
-#define TT_DESCRIPTOR_PAGE_S_NOT_SHARED (0UL << 10)
-#define TT_DESCRIPTOR_PAGE_S_SHARED (1UL << 10)
-
-#define TT_DESCRIPTOR_SECTION_AP_MASK ((1UL << 15) | (3UL << 10))
-#define TT_DESCRIPTOR_SECTION_AP_NO_NO ((0UL << 15) | (0UL << 10))
-#define TT_DESCRIPTOR_SECTION_AP_RW_NO ((0UL << 15) | (1UL << 10))
-#define TT_DESCRIPTOR_SECTION_AP_RW_RO ((0UL << 15) | (2UL << 10))
-#define TT_DESCRIPTOR_SECTION_AP_RW_RW ((0UL << 15) | (3UL << 10))
-#define TT_DESCRIPTOR_SECTION_AP_RO_NO ((1UL << 15) | (1UL << 10))
-#define TT_DESCRIPTOR_SECTION_AP_RO_RO ((1UL << 15) | (3UL << 10))
-
-#define TT_DESCRIPTOR_PAGE_AP_MASK ((1UL << 9) | (3UL << 4))
-#define TT_DESCRIPTOR_PAGE_AP_NO_NO ((0UL << 9) | (0UL << 4))
-#define TT_DESCRIPTOR_PAGE_AP_RW_NO ((0UL << 9) | (1UL << 4))
-#define TT_DESCRIPTOR_PAGE_AP_RW_RO ((0UL << 9) | (2UL << 4))
-#define TT_DESCRIPTOR_PAGE_AP_RW_RW ((0UL << 9) | (3UL << 4))
-#define TT_DESCRIPTOR_PAGE_AP_RO_NO ((1UL << 9) | (1UL << 4))
-#define TT_DESCRIPTOR_PAGE_AP_RO_RO ((1UL << 9) | (3UL << 4))
-
-#define TT_DESCRIPTOR_SECTION_XN_MASK (0x1UL << 4)
-#define TT_DESCRIPTOR_PAGE_XN_MASK (0x1UL << 0)
-#define TT_DESCRIPTOR_LARGEPAGE_XN_MASK (0x1UL << 15)
-
-#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK ((3UL << 12) | (1UL << 3) | (1UL << 2))
-#define TT_DESCRIPTOR_SECTION_CACHEABLE_MASK (1UL << 3)
-#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED ((0UL << 12) | (0UL << 3) | (0UL << 2))
-#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_SHAREABLE_DEVICE ((0UL << 12) | (0UL << 3) | (1UL << 2))
-#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC ((0UL << 12) | (1UL << 3) | (0UL << 2))
-#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_NO_ALLOC ((0UL << 12) | (1UL << 3) | (1UL << 2))
-#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE ((1UL << 12) | (0UL << 3) | (0UL << 2))
-#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC ((1UL << 12) | (1UL << 3) | (1UL << 2))
-#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_SHAREABLE_DEVICE ((2UL << 12) | (0UL << 3) | (0UL << 2))
-
-#define TT_DESCRIPTOR_PAGE_SIZE (0x00001000)
-
-#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK ((3UL << 6) | (1UL << 3) | (1UL << 2))
+#define TT_DESCRIPTOR_SECTION_SIZE (0x00100000)
+
+#define TT_DESCRIPTOR_SECTION_NS_MASK (1UL << 19)
+#define TT_DESCRIPTOR_SECTION_NS (1UL << 19)
+
+#define TT_DESCRIPTOR_SECTION_NG_MASK (1UL << 17)
+#define TT_DESCRIPTOR_SECTION_NG_GLOBAL (0UL << 17)
+#define TT_DESCRIPTOR_SECTION_NG_LOCAL (1UL << 17)
+
+#define TT_DESCRIPTOR_PAGE_NG_MASK (1UL << 11)
+#define TT_DESCRIPTOR_PAGE_NG_GLOBAL (0UL << 11)
+#define TT_DESCRIPTOR_PAGE_NG_LOCAL (1UL << 11)
+
+#define TT_DESCRIPTOR_SECTION_S_MASK (1UL << 16)
+#define TT_DESCRIPTOR_SECTION_S_NOT_SHARED (0UL << 16)
+#define TT_DESCRIPTOR_SECTION_S_SHARED (1UL << 16)
+
+#define TT_DESCRIPTOR_PAGE_S_MASK (1UL << 10)
+#define TT_DESCRIPTOR_PAGE_S_NOT_SHARED (0UL << 10)
+#define TT_DESCRIPTOR_PAGE_S_SHARED (1UL << 10)
+
+#define TT_DESCRIPTOR_SECTION_AP_MASK ((1UL << 15) | (3UL << 10))
+#define TT_DESCRIPTOR_SECTION_AP_NO_NO ((0UL << 15) | (0UL << 10))
+#define TT_DESCRIPTOR_SECTION_AP_RW_NO ((0UL << 15) | (1UL << 10))
+#define TT_DESCRIPTOR_SECTION_AP_RW_RO ((0UL << 15) | (2UL << 10))
+#define TT_DESCRIPTOR_SECTION_AP_RW_RW ((0UL << 15) | (3UL << 10))
+#define TT_DESCRIPTOR_SECTION_AP_RO_NO ((1UL << 15) | (1UL << 10))
+#define TT_DESCRIPTOR_SECTION_AP_RO_RO ((1UL << 15) | (3UL << 10))
+
+#define TT_DESCRIPTOR_PAGE_AP_MASK ((1UL << 9) | (3UL << 4))
+#define TT_DESCRIPTOR_PAGE_AP_NO_NO ((0UL << 9) | (0UL << 4))
+#define TT_DESCRIPTOR_PAGE_AP_RW_NO ((0UL << 9) | (1UL << 4))
+#define TT_DESCRIPTOR_PAGE_AP_RW_RO ((0UL << 9) | (2UL << 4))
+#define TT_DESCRIPTOR_PAGE_AP_RW_RW ((0UL << 9) | (3UL << 4))
+#define TT_DESCRIPTOR_PAGE_AP_RO_NO ((1UL << 9) | (1UL << 4))
+#define TT_DESCRIPTOR_PAGE_AP_RO_RO ((1UL << 9) | (3UL << 4))
+
+#define TT_DESCRIPTOR_SECTION_XN_MASK (0x1UL << 4)
+#define TT_DESCRIPTOR_PAGE_XN_MASK (0x1UL << 0)
+#define TT_DESCRIPTOR_LARGEPAGE_XN_MASK (0x1UL << 15)
+
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK ((3UL << 12) | (1UL << 3) | (1UL << 2))
+#define TT_DESCRIPTOR_SECTION_CACHEABLE_MASK (1UL << 3)
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED ((0UL << 12) | (0UL << 3) | (0UL << 2))
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_SHAREABLE_DEVICE ((0UL << 12) | (0UL << 3) | (1UL << 2))
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC ((0UL << 12) | (1UL << 3) | (0UL << 2))
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_NO_ALLOC ((0UL << 12) | (1UL << 3) | (1UL << 2))
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE ((1UL << 12) | (0UL << 3) | (0UL << 2))
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC ((1UL << 12) | (1UL << 3) | (1UL << 2))
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_SHAREABLE_DEVICE ((2UL << 12) | (0UL << 3) | (0UL << 2))
+
+#define TT_DESCRIPTOR_PAGE_SIZE (0x00001000)
+
+#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK ((3UL << 6) | (1UL << 3) | (1UL << 2))
#define TT_DESCRIPTOR_PAGE_CACHEABLE_MASK (1UL << 3)
-#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED ((0UL << 6) | (0UL << 3) | (0UL << 2))
-#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_SHAREABLE_DEVICE ((0UL << 6) | (0UL << 3) | (1UL << 2))
-#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC ((0UL << 6) | (1UL << 3) | (0UL << 2))
-#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_NO_ALLOC ((0UL << 6) | (1UL << 3) | (1UL << 2))
-#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE ((1UL << 6) | (0UL << 3) | (0UL << 2))
-#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_ALLOC ((1UL << 6) | (1UL << 3) | (1UL << 2))
-#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_SHAREABLE_DEVICE ((2UL << 6) | (0UL << 3) | (0UL << 2))
-
-#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_MASK ((3UL << 12) | (1UL << 3) | (1UL << 2))
-#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_STRONGLY_ORDERED ((0UL << 12) | (0UL << 3) | (0UL << 2))
-#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_SHAREABLE_DEVICE ((0UL << 12) | (0UL << 3) | (1UL << 2))
-#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC ((0UL << 12) | (1UL << 3) | (0UL << 2))
-#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_WRITE_BACK_NO_ALLOC ((0UL << 12) | (1UL << 3) | (1UL << 2))
-#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_NON_CACHEABLE ((1UL << 12) | (0UL << 3) | (0UL << 2))
-#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_WRITE_BACK_ALLOC ((1UL << 12) | (1UL << 3) | (1UL << 2))
-#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_NON_SHAREABLE_DEVICE ((2UL << 12) | (0UL << 3) | (0UL << 2))
-
-#define TT_DESCRIPTOR_CONVERT_TO_PAGE_AP(Desc) ((((Desc) & TT_DESCRIPTOR_SECTION_AP_MASK) >> 6) & TT_DESCRIPTOR_PAGE_AP_MASK)
-#define TT_DESCRIPTOR_CONVERT_TO_PAGE_NG(Desc) ((((Desc) & TT_DESCRIPTOR_SECTION_NG_MASK) >> 6) & TT_DESCRIPTOR_PAGE_NG_MASK)
-#define TT_DESCRIPTOR_CONVERT_TO_PAGE_S(Desc) ((((Desc) & TT_DESCRIPTOR_SECTION_S_MASK) >> 6) & TT_DESCRIPTOR_PAGE_S_MASK)
-#define TT_DESCRIPTOR_CONVERT_TO_PAGE_XN(Desc,IsLargePage) ((IsLargePage)? \
+#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED ((0UL << 6) | (0UL << 3) | (0UL << 2))
+#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_SHAREABLE_DEVICE ((0UL << 6) | (0UL << 3) | (1UL << 2))
+#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC ((0UL << 6) | (1UL << 3) | (0UL << 2))
+#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_NO_ALLOC ((0UL << 6) | (1UL << 3) | (1UL << 2))
+#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE ((1UL << 6) | (0UL << 3) | (0UL << 2))
+#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_ALLOC ((1UL << 6) | (1UL << 3) | (1UL << 2))
+#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_SHAREABLE_DEVICE ((2UL << 6) | (0UL << 3) | (0UL << 2))
+
+#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_MASK ((3UL << 12) | (1UL << 3) | (1UL << 2))
+#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_STRONGLY_ORDERED ((0UL << 12) | (0UL << 3) | (0UL << 2))
+#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_SHAREABLE_DEVICE ((0UL << 12) | (0UL << 3) | (1UL << 2))
+#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC ((0UL << 12) | (1UL << 3) | (0UL << 2))
+#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_WRITE_BACK_NO_ALLOC ((0UL << 12) | (1UL << 3) | (1UL << 2))
+#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_NON_CACHEABLE ((1UL << 12) | (0UL << 3) | (0UL << 2))
+#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_WRITE_BACK_ALLOC ((1UL << 12) | (1UL << 3) | (1UL << 2))
+#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_NON_SHAREABLE_DEVICE ((2UL << 12) | (0UL << 3) | (0UL << 2))
+
+#define TT_DESCRIPTOR_CONVERT_TO_PAGE_AP(Desc) ((((Desc) & TT_DESCRIPTOR_SECTION_AP_MASK) >> 6) & TT_DESCRIPTOR_PAGE_AP_MASK)
+#define TT_DESCRIPTOR_CONVERT_TO_PAGE_NG(Desc) ((((Desc) & TT_DESCRIPTOR_SECTION_NG_MASK) >> 6) & TT_DESCRIPTOR_PAGE_NG_MASK)
+#define TT_DESCRIPTOR_CONVERT_TO_PAGE_S(Desc) ((((Desc) & TT_DESCRIPTOR_SECTION_S_MASK) >> 6) & TT_DESCRIPTOR_PAGE_S_MASK)
+#define TT_DESCRIPTOR_CONVERT_TO_PAGE_XN(Desc, IsLargePage) ((IsLargePage)?\
((((Desc) & TT_DESCRIPTOR_SECTION_XN_MASK) << 11) & TT_DESCRIPTOR_LARGEPAGE_XN_MASK): \
((((Desc) & TT_DESCRIPTOR_SECTION_XN_MASK) >> 4) & TT_DESCRIPTOR_PAGE_XN_MASK))
-#define TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY(Desc,IsLargePage) (IsLargePage? \
+#define TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY(Desc, IsLargePage) (IsLargePage? \
(((Desc) & TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK) & TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_MASK): \
(((((Desc) & (0x3 << 12)) >> 6) | (Desc & (0x3 << 2)))))
-#define TT_DESCRIPTOR_CONVERT_TO_SECTION_AP(Desc) ((((Desc) & TT_DESCRIPTOR_PAGE_AP_MASK) << 6) & TT_DESCRIPTOR_SECTION_AP_MASK)
+#define TT_DESCRIPTOR_CONVERT_TO_SECTION_AP(Desc) ((((Desc) & TT_DESCRIPTOR_PAGE_AP_MASK) << 6) & TT_DESCRIPTOR_SECTION_AP_MASK)
-#define TT_DESCRIPTOR_CONVERT_TO_SECTION_CACHE_POLICY(Desc,IsLargePage) (IsLargePage? \
+#define TT_DESCRIPTOR_CONVERT_TO_SECTION_CACHE_POLICY(Desc, IsLargePage) (IsLargePage? \
(((Desc) & TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_MASK) & TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK): \
(((((Desc) & (0x3 << 6)) << 6) | (Desc & (0x3 << 2)))))
-#define TT_DESCRIPTOR_SECTION_ATTRIBUTE_MASK (TT_DESCRIPTOR_SECTION_NS_MASK | TT_DESCRIPTOR_SECTION_NG_MASK | \
+#define TT_DESCRIPTOR_SECTION_ATTRIBUTE_MASK (TT_DESCRIPTOR_SECTION_NS_MASK | TT_DESCRIPTOR_SECTION_NG_MASK | \
TT_DESCRIPTOR_SECTION_S_MASK | TT_DESCRIPTOR_SECTION_AP_MASK | \
TT_DESCRIPTOR_SECTION_XN_MASK | TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK)
-#define TT_DESCRIPTOR_PAGE_ATTRIBUTE_MASK (TT_DESCRIPTOR_PAGE_NG_MASK | TT_DESCRIPTOR_PAGE_S_MASK | \
+#define TT_DESCRIPTOR_PAGE_ATTRIBUTE_MASK (TT_DESCRIPTOR_PAGE_NG_MASK | TT_DESCRIPTOR_PAGE_S_MASK | \
TT_DESCRIPTOR_PAGE_AP_MASK | TT_DESCRIPTOR_PAGE_XN_MASK | \
TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK)
-#define TT_DESCRIPTOR_SECTION_DOMAIN_MASK (0x0FUL << 5)
-#define TT_DESCRIPTOR_SECTION_DOMAIN(a) (((a) & 0x0FUL) << 5)
+#define TT_DESCRIPTOR_SECTION_DOMAIN_MASK (0x0FUL << 5)
+#define TT_DESCRIPTOR_SECTION_DOMAIN(a) (((a) & 0x0FUL) << 5)
-#define TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK (0xFFF00000)
-#define TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK (0xFFFFFC00)
-#define TT_DESCRIPTOR_SECTION_BASE_ADDRESS(a) ((a) & TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK)
-#define TT_DESCRIPTOR_SECTION_BASE_SHIFT 20
+#define TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK (0xFFF00000)
+#define TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK (0xFFFFFC00)
+#define TT_DESCRIPTOR_SECTION_BASE_ADDRESS(a) ((a) & TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK)
+#define TT_DESCRIPTOR_SECTION_BASE_SHIFT 20
-#define TT_DESCRIPTOR_PAGE_BASE_ADDRESS_MASK (0xFFFFF000)
-#define TT_DESCRIPTOR_PAGE_INDEX_MASK (0x000FF000)
-#define TT_DESCRIPTOR_PAGE_BASE_ADDRESS(a) ((a) & TT_DESCRIPTOR_PAGE_BASE_ADDRESS_MASK)
-#define TT_DESCRIPTOR_PAGE_BASE_SHIFT 12
+#define TT_DESCRIPTOR_PAGE_BASE_ADDRESS_MASK (0xFFFFF000)
+#define TT_DESCRIPTOR_PAGE_INDEX_MASK (0x000FF000)
+#define TT_DESCRIPTOR_PAGE_BASE_ADDRESS(a) ((a) & TT_DESCRIPTOR_PAGE_BASE_ADDRESS_MASK)
+#define TT_DESCRIPTOR_PAGE_BASE_SHIFT 12
-#define TT_DESCRIPTOR_SECTION_WRITE_BACK(NonSecure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \
+#define TT_DESCRIPTOR_SECTION_WRITE_BACK(NonSecure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \
((NonSecure) ? TT_DESCRIPTOR_SECTION_NS : 0) | \
TT_DESCRIPTOR_SECTION_NG_GLOBAL | \
TT_DESCRIPTOR_SECTION_S_SHARED | \
TT_DESCRIPTOR_SECTION_DOMAIN(0) | \
TT_DESCRIPTOR_SECTION_AP_RW_RW | \
TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC)
-#define TT_DESCRIPTOR_SECTION_WRITE_THROUGH(NonSecure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \
+#define TT_DESCRIPTOR_SECTION_WRITE_THROUGH(NonSecure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \
((NonSecure) ? TT_DESCRIPTOR_SECTION_NS : 0) | \
TT_DESCRIPTOR_SECTION_NG_GLOBAL | \
TT_DESCRIPTOR_SECTION_S_SHARED | \
TT_DESCRIPTOR_SECTION_DOMAIN(0) | \
TT_DESCRIPTOR_SECTION_AP_RW_RW | \
TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC)
-#define TT_DESCRIPTOR_SECTION_DEVICE(NonSecure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \
+#define TT_DESCRIPTOR_SECTION_DEVICE(NonSecure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \
((NonSecure) ? TT_DESCRIPTOR_SECTION_NS : 0) | \
TT_DESCRIPTOR_SECTION_NG_GLOBAL | \
TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \
@@ -193,7 +192,7 @@ TT_DESCRIPTOR_SECTION_AP_RW_RW | \
TT_DESCRIPTOR_SECTION_XN_MASK | \
TT_DESCRIPTOR_SECTION_CACHE_POLICY_SHAREABLE_DEVICE)
-#define TT_DESCRIPTOR_SECTION_UNCACHED(NonSecure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \
+#define TT_DESCRIPTOR_SECTION_UNCACHED(NonSecure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \
((NonSecure) ? TT_DESCRIPTOR_SECTION_NS : 0) | \
TT_DESCRIPTOR_SECTION_NG_GLOBAL | \
TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \
@@ -201,33 +200,33 @@ TT_DESCRIPTOR_SECTION_AP_RW_RW | \
TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE)
-#define TT_DESCRIPTOR_PAGE_WRITE_BACK (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \
+#define TT_DESCRIPTOR_PAGE_WRITE_BACK (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \
TT_DESCRIPTOR_PAGE_NG_GLOBAL | \
TT_DESCRIPTOR_PAGE_S_SHARED | \
TT_DESCRIPTOR_PAGE_AP_RW_RW | \
TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_ALLOC)
-#define TT_DESCRIPTOR_PAGE_WRITE_THROUGH (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \
+#define TT_DESCRIPTOR_PAGE_WRITE_THROUGH (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \
TT_DESCRIPTOR_PAGE_NG_GLOBAL | \
TT_DESCRIPTOR_PAGE_S_SHARED | \
TT_DESCRIPTOR_PAGE_AP_RW_RW | \
TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC)
-#define TT_DESCRIPTOR_PAGE_DEVICE (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \
+#define TT_DESCRIPTOR_PAGE_DEVICE (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \
TT_DESCRIPTOR_PAGE_NG_GLOBAL | \
TT_DESCRIPTOR_PAGE_S_NOT_SHARED | \
TT_DESCRIPTOR_PAGE_AP_RW_RW | \
TT_DESCRIPTOR_PAGE_XN_MASK | \
TT_DESCRIPTOR_PAGE_CACHE_POLICY_SHAREABLE_DEVICE)
-#define TT_DESCRIPTOR_PAGE_UNCACHED (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \
+#define TT_DESCRIPTOR_PAGE_UNCACHED (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \
TT_DESCRIPTOR_PAGE_NG_GLOBAL | \
TT_DESCRIPTOR_PAGE_S_NOT_SHARED | \
TT_DESCRIPTOR_PAGE_AP_RW_RW | \
TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE)
// First Level Descriptors
-typedef UINT32 ARM_FIRST_LEVEL_DESCRIPTOR;
+typedef UINT32 ARM_FIRST_LEVEL_DESCRIPTOR;
// Second Level Descriptors
-typedef UINT32 ARM_PAGE_TABLE_ENTRY;
+typedef UINT32 ARM_PAGE_TABLE_ENTRY;
UINT32
ConvertSectionAttributesToPageAttributes (
diff --git a/ArmPkg/Include/Guid/ArmMpCoreInfo.h b/ArmPkg/Include/Guid/ArmMpCoreInfo.h index b810767879..06f9326ca0 100644 --- a/ArmPkg/Include/Guid/ArmMpCoreInfo.h +++ b/ArmPkg/Include/Guid/ArmMpCoreInfo.h @@ -9,52 +9,51 @@ #ifndef ARM_MP_CORE_INFO_GUID_H_
#define ARM_MP_CORE_INFO_GUID_H_
-#define MAX_CPUS_PER_MPCORE_SYSTEM 0x04
-#define SCU_CONFIG_REG_OFFSET 0x04
-#define MPIDR_U_BIT_MASK 0x40000000
+#define MAX_CPUS_PER_MPCORE_SYSTEM 0x04
+#define SCU_CONFIG_REG_OFFSET 0x04
+#define MPIDR_U_BIT_MASK 0x40000000
typedef struct {
- UINT32 ClusterId;
- UINT32 CoreId;
+ UINT32 ClusterId;
+ UINT32 CoreId;
// MP Core Mailbox
- EFI_PHYSICAL_ADDRESS MailboxSetAddress;
- EFI_PHYSICAL_ADDRESS MailboxGetAddress;
- EFI_PHYSICAL_ADDRESS MailboxClearAddress;
- UINT64 MailboxClearValue;
+ EFI_PHYSICAL_ADDRESS MailboxSetAddress;
+ EFI_PHYSICAL_ADDRESS MailboxGetAddress;
+ EFI_PHYSICAL_ADDRESS MailboxClearAddress;
+ UINT64 MailboxClearValue;
} ARM_CORE_INFO;
-typedef struct{
- UINT64 Signature;
- UINT32 Length;
- UINT32 Revision;
- UINT64 OemId;
- UINT64 OemTableId;
- UINTN OemRevision;
- UINTN CreatorId;
- UINTN CreatorRevision;
- EFI_GUID Identifier;
- UINTN DataLen;
+typedef struct {
+ UINT64 Signature;
+ UINT32 Length;
+ UINT32 Revision;
+ UINT64 OemId;
+ UINT64 OemTableId;
+ UINTN OemRevision;
+ UINTN CreatorId;
+ UINTN CreatorRevision;
+ EFI_GUID Identifier;
+ UINTN DataLen;
} ARM_PROCESSOR_TABLE_HEADER;
typedef struct {
- ARM_PROCESSOR_TABLE_HEADER Header;
- UINTN NumberOfEntries;
- ARM_CORE_INFO *ArmCpus;
+ ARM_PROCESSOR_TABLE_HEADER Header;
+ UINTN NumberOfEntries;
+ ARM_CORE_INFO *ArmCpus;
} ARM_PROCESSOR_TABLE;
-
#define ARM_MP_CORE_INFO_GUID \
{ 0xa4ee0728, 0xe5d7, 0x4ac5, {0xb2, 0x1e, 0x65, 0x8e, 0xd8, 0x57, 0xe8, 0x34} }
-#define EFI_ARM_PROCESSOR_TABLE_SIGNATURE SIGNATURE_64 ('C', 'P', 'U', 'T', 'A', 'B', 'L', 'E')
-#define EFI_ARM_PROCESSOR_TABLE_REVISION 0x00010000 //1.0
-#define EFI_ARM_PROCESSOR_TABLE_OEM_ID SIGNATURE_64('A','R','M',' ', 'L', 't', 'd', ' ')
-#define EFI_ARM_PROCESSOR_TABLE_OEM_TABLE_ID SIGNATURE_64('V', 'E', 'R', 'S', 'A', 'T', 'I', 'L')
-#define EFI_ARM_PROCESSOR_TABLE_OEM_REVISION 0x00000001
-#define EFI_ARM_PROCESSOR_TABLE_CREATOR_ID 0xA5A5A5A5
-#define EFI_ARM_PROCESSOR_TABLE_CREATOR_REVISION 0x01000001
+#define EFI_ARM_PROCESSOR_TABLE_SIGNATURE SIGNATURE_64 ('C', 'P', 'U', 'T', 'A', 'B', 'L', 'E')
+#define EFI_ARM_PROCESSOR_TABLE_REVISION 0x00010000// 1.0
+#define EFI_ARM_PROCESSOR_TABLE_OEM_ID SIGNATURE_64('A','R','M',' ', 'L', 't', 'd', ' ')
+#define EFI_ARM_PROCESSOR_TABLE_OEM_TABLE_ID SIGNATURE_64('V', 'E', 'R', 'S', 'A', 'T', 'I', 'L')
+#define EFI_ARM_PROCESSOR_TABLE_OEM_REVISION 0x00000001
+#define EFI_ARM_PROCESSOR_TABLE_CREATOR_ID 0xA5A5A5A5
+#define EFI_ARM_PROCESSOR_TABLE_CREATOR_REVISION 0x01000001
-extern EFI_GUID gArmMpCoreInfoGuid;
+extern EFI_GUID gArmMpCoreInfoGuid;
#endif /* ARM_MP_CORE_INFO_GUID_H_ */
diff --git a/ArmPkg/Include/IndustryStandard/ArmCache.h b/ArmPkg/Include/IndustryStandard/ArmCache.h index f9de46b5bf..27a91fcda2 100644 --- a/ArmPkg/Include/IndustryStandard/ArmCache.h +++ b/ArmPkg/Include/IndustryStandard/ArmCache.h @@ -13,22 +13,21 @@ // The ARM Architecture Reference Manual for ARMv8-A defines up
// to 7 levels of cache, L1 through L7.
-#define MAX_ARM_CACHE_LEVEL 7
+#define MAX_ARM_CACHE_LEVEL 7
/// Defines the structure of the CSSELR (Cache Size Selection) register
typedef union {
struct {
- UINT32 InD :1; ///< Instruction not Data bit
- UINT32 Level :3; ///< Cache level (zero based)
- UINT32 TnD :1; ///< Allocation not Data bit
- UINT32 Reserved :27; ///< Reserved, RES0
- } Bits; ///< Bitfield definition of the register
- UINT32 Data; ///< The entire 32-bit value
+ UINT32 InD : 1; ///< Instruction not Data bit
+ UINT32 Level : 3; ///< Cache level (zero based)
+ UINT32 TnD : 1; ///< Allocation not Data bit
+ UINT32 Reserved : 27; ///< Reserved, RES0
+ } Bits; ///< Bitfield definition of the register
+ UINT32 Data; ///< The entire 32-bit value
} CSSELR_DATA;
/// The cache type values for the InD field of the CSSELR register
-typedef enum
-{
+typedef enum {
/// Select the data or unified cache
CsselrCacheTypeDataOrUnified = 0,
/// Select the instruction cache
@@ -39,35 +38,35 @@ typedef enum /// Defines the structure of the CCSIDR (Current Cache Size ID) register
typedef union {
struct {
- UINT64 LineSize :3; ///< Line size (Log2(Num bytes in cache) - 4)
- UINT64 Associativity :10; ///< Associativity - 1
- UINT64 NumSets :15; ///< Number of sets in the cache -1
- UINT64 Unknown :4; ///< Reserved, UNKNOWN
- UINT64 Reserved :32; ///< Reserved, RES0
+ UINT64 LineSize : 3; ///< Line size (Log2(Num bytes in cache) - 4)
+ UINT64 Associativity : 10; ///< Associativity - 1
+ UINT64 NumSets : 15; ///< Number of sets in the cache -1
+ UINT64 Unknown : 4; ///< Reserved, UNKNOWN
+ UINT64 Reserved : 32; ///< Reserved, RES0
} BitsNonCcidx; ///< Bitfield definition of the register when FEAT_CCIDX is not supported.
struct {
- UINT64 LineSize :3; ///< Line size (Log2(Num bytes in cache) - 4)
- UINT64 Associativity :21; ///< Associativity - 1
- UINT64 Reserved1 :8; ///< Reserved, RES0
- UINT64 NumSets :24; ///< Number of sets in the cache -1
- UINT64 Reserved2 :8; ///< Reserved, RES0
+ UINT64 LineSize : 3; ///< Line size (Log2(Num bytes in cache) - 4)
+ UINT64 Associativity : 21; ///< Associativity - 1
+ UINT64 Reserved1 : 8; ///< Reserved, RES0
+ UINT64 NumSets : 24; ///< Number of sets in the cache -1
+ UINT64 Reserved2 : 8; ///< Reserved, RES0
} BitsCcidxAA64; ///< Bitfield definition of the register when FEAT_IDX is supported.
struct {
- UINT64 LineSize : 3;
- UINT64 Associativity : 21;
- UINT64 Reserved : 8;
- UINT64 Unallocated : 32;
+ UINT64 LineSize : 3;
+ UINT64 Associativity : 21;
+ UINT64 Reserved : 8;
+ UINT64 Unallocated : 32;
} BitsCcidxAA32;
- UINT64 Data; ///< The entire 64-bit value
+ UINT64 Data; ///< The entire 64-bit value
} CCSIDR_DATA;
/// Defines the structure of the AARCH32 CCSIDR2 register.
typedef union {
struct {
- UINT32 NumSets :24; ///< Number of sets in the cache - 1
- UINT32 Reserved :8; ///< Reserved, RES0
- } Bits; ///< Bitfield definition of the register
- UINT32 Data; ///< The entire 32-bit value
+ UINT32 NumSets : 24; ///< Number of sets in the cache - 1
+ UINT32 Reserved : 8; ///< Reserved, RES0
+ } Bits; ///< Bitfield definition of the register
+ UINT32 Data; ///< The entire 32-bit value
} CCSIDR2_DATA;
/** Defines the structure of the CLIDR (Cache Level ID) register.
@@ -77,19 +76,19 @@ typedef union { **/
typedef union {
struct {
- UINT32 Ctype1 : 3; ///< Level 1 cache type
- UINT32 Ctype2 : 3; ///< Level 2 cache type
- UINT32 Ctype3 : 3; ///< Level 3 cache type
- UINT32 Ctype4 : 3; ///< Level 4 cache type
- UINT32 Ctype5 : 3; ///< Level 5 cache type
- UINT32 Ctype6 : 3; ///< Level 6 cache type
- UINT32 Ctype7 : 3; ///< Level 7 cache type
- UINT32 LoUIS : 3; ///< Level of Unification Inner Shareable
- UINT32 LoC : 3; ///< Level of Coherency
- UINT32 LoUU : 3; ///< Level of Unification Uniprocessor
- UINT32 Icb : 3; ///< Inner Cache Boundary
- } Bits; ///< Bitfield definition of the register
- UINT32 Data; ///< The entire 32-bit value
+ UINT32 Ctype1 : 3; ///< Level 1 cache type
+ UINT32 Ctype2 : 3; ///< Level 2 cache type
+ UINT32 Ctype3 : 3; ///< Level 3 cache type
+ UINT32 Ctype4 : 3; ///< Level 4 cache type
+ UINT32 Ctype5 : 3; ///< Level 5 cache type
+ UINT32 Ctype6 : 3; ///< Level 6 cache type
+ UINT32 Ctype7 : 3; ///< Level 7 cache type
+ UINT32 LoUIS : 3; ///< Level of Unification Inner Shareable
+ UINT32 LoC : 3; ///< Level of Coherency
+ UINT32 LoUU : 3; ///< Level of Unification Uniprocessor
+ UINT32 Icb : 3; ///< Inner Cache Boundary
+ } Bits; ///< Bitfield definition of the register
+ UINT32 Data; ///< The entire 32-bit value
} CLIDR_DATA;
/// The cache types reported in the CLIDR register.
@@ -107,6 +106,6 @@ typedef enum { ClidrCacheTypeMax
} CLIDR_CACHE_TYPE;
-#define CLIDR_GET_CACHE_TYPE(x, level) ((x >> (3 * (level))) & 0b111)
+#define CLIDR_GET_CACHE_TYPE(x, level) ((x >> (3 * (level))) & 0b111)
#endif /* ARM_CACHE_H_ */
diff --git a/ArmPkg/Include/IndustryStandard/ArmFfaSvc.h b/ArmPkg/Include/IndustryStandard/ArmFfaSvc.h index ebcb54b28b..4126a4985b 100644 --- a/ArmPkg/Include/IndustryStandard/ArmFfaSvc.h +++ b/ArmPkg/Include/IndustryStandard/ArmFfaSvc.h @@ -16,34 +16,34 @@ #ifndef ARM_FFA_SVC_H_
#define ARM_FFA_SVC_H_
-#define ARM_SVC_ID_FFA_VERSION_AARCH32 0x84000063
-#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH32 0x8400006F
-#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH32 0x84000070
-#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH64 0xC400006F
-#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH64 0xC4000070
+#define ARM_SVC_ID_FFA_VERSION_AARCH32 0x84000063
+#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH32 0x8400006F
+#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH32 0x84000070
+#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH64 0xC400006F
+#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH64 0xC4000070
/* Generic IDs when using AArch32 or AArch64 execution state */
#ifdef MDE_CPU_AARCH64
-#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH64
-#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH64
+#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH64
+#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH64
#endif
#ifdef MDE_CPU_ARM
-#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH32
-#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH32
+#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH32
+#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH32
#endif
-#define SPM_MAJOR_VERSION_FFA 1
-#define SPM_MINOR_VERSION_FFA 0
+#define SPM_MAJOR_VERSION_FFA 1
+#define SPM_MINOR_VERSION_FFA 0
-#define ARM_FFA_SPM_RET_SUCCESS 0
-#define ARM_FFA_SPM_RET_NOT_SUPPORTED -1
-#define ARM_FFA_SPM_RET_INVALID_PARAMETERS -2
-#define ARM_FFA_SPM_RET_NO_MEMORY -3
-#define ARM_FFA_SPM_RET_BUSY -4
-#define ARM_FFA_SPM_RET_INTERRUPTED -5
-#define ARM_FFA_SPM_RET_DENIED -6
-#define ARM_FFA_SPM_RET_RETRY -7
-#define ARM_FFA_SPM_RET_ABORTED -8
+#define ARM_FFA_SPM_RET_SUCCESS 0
+#define ARM_FFA_SPM_RET_NOT_SUPPORTED -1
+#define ARM_FFA_SPM_RET_INVALID_PARAMETERS -2
+#define ARM_FFA_SPM_RET_NO_MEMORY -3
+#define ARM_FFA_SPM_RET_BUSY -4
+#define ARM_FFA_SPM_RET_INTERRUPTED -5
+#define ARM_FFA_SPM_RET_DENIED -6
+#define ARM_FFA_SPM_RET_RETRY -7
+#define ARM_FFA_SPM_RET_ABORTED -8
// For now, the destination id to be used in the FF-A calls
// is being hard-coded. Subsequently, support will be added
@@ -51,6 +51,6 @@ // This is the endpoint id used by the optee os's implementation
// of the spmc.
// https://github.com/OP-TEE/optee_os/blob/master/core/arch/arm/kernel/stmm_sp.c#L66
-#define ARM_FFA_DESTINATION_ENDPOINT_ID 3
+#define ARM_FFA_DESTINATION_ENDPOINT_ID 3
#endif // ARM_FFA_SVC_H_
diff --git a/ArmPkg/Include/IndustryStandard/ArmMmSvc.h b/ArmPkg/Include/IndustryStandard/ArmMmSvc.h index deb3bc99d2..11aa50e3ac 100644 --- a/ArmPkg/Include/IndustryStandard/ArmMmSvc.h +++ b/ArmPkg/Include/IndustryStandard/ArmMmSvc.h @@ -14,49 +14,49 @@ * delegated events and request the Secure partition manager to perform
* privileged operations on its behalf.
*/
-#define ARM_SVC_ID_SPM_VERSION_AARCH32 0x84000060
-#define ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH32 0x84000061
-#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH32 0x84000064
-#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH32 0x84000065
-#define ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH64 0xC4000061
-#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH64 0xC4000064
-#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH64 0xC4000065
+#define ARM_SVC_ID_SPM_VERSION_AARCH32 0x84000060
+#define ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH32 0x84000061
+#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH32 0x84000064
+#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH32 0x84000065
+#define ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH64 0xC4000061
+#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH64 0xC4000064
+#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH64 0xC4000065
/* Generic IDs when using AArch32 or AArch64 execution state */
#ifdef MDE_CPU_AARCH64
-#define ARM_SVC_ID_SP_EVENT_COMPLETE ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH64
-#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH64
-#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH64
+#define ARM_SVC_ID_SP_EVENT_COMPLETE ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH64
+#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH64
+#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH64
#endif
#ifdef MDE_CPU_ARM
-#define ARM_SVC_ID_SP_EVENT_COMPLETE ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH32
-#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH32
-#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH32
+#define ARM_SVC_ID_SP_EVENT_COMPLETE ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH32
+#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH32
+#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH32
#endif
#define SET_MEM_ATTR_DATA_PERM_MASK 0x3
-#define SET_MEM_ATTR_DATA_PERM_SHIFT 0
-#define SET_MEM_ATTR_DATA_PERM_NO_ACCESS 0
-#define SET_MEM_ATTR_DATA_PERM_RW 1
-#define SET_MEM_ATTR_DATA_PERM_RO 3
+#define SET_MEM_ATTR_DATA_PERM_SHIFT 0
+#define SET_MEM_ATTR_DATA_PERM_NO_ACCESS 0
+#define SET_MEM_ATTR_DATA_PERM_RW 1
+#define SET_MEM_ATTR_DATA_PERM_RO 3
#define SET_MEM_ATTR_CODE_PERM_MASK 0x1
-#define SET_MEM_ATTR_CODE_PERM_SHIFT 2
-#define SET_MEM_ATTR_CODE_PERM_X 0
-#define SET_MEM_ATTR_CODE_PERM_XN 1
+#define SET_MEM_ATTR_CODE_PERM_SHIFT 2
+#define SET_MEM_ATTR_CODE_PERM_X 0
+#define SET_MEM_ATTR_CODE_PERM_XN 1
#define SET_MEM_ATTR_MAKE_PERM_REQUEST(d_perm, c_perm) \
((((c_perm) & SET_MEM_ATTR_CODE_PERM_MASK) << SET_MEM_ATTR_CODE_PERM_SHIFT) | \
(( (d_perm) & SET_MEM_ATTR_DATA_PERM_MASK) << SET_MEM_ATTR_DATA_PERM_SHIFT))
/* MM SVC Return error codes */
-#define ARM_SVC_SPM_RET_SUCCESS 0
-#define ARM_SVC_SPM_RET_NOT_SUPPORTED -1
-#define ARM_SVC_SPM_RET_INVALID_PARAMS -2
-#define ARM_SVC_SPM_RET_DENIED -3
-#define ARM_SVC_SPM_RET_NO_MEMORY -5
-
-#define SPM_MAJOR_VERSION 0
-#define SPM_MINOR_VERSION 1
+#define ARM_SVC_SPM_RET_SUCCESS 0
+#define ARM_SVC_SPM_RET_NOT_SUPPORTED -1
+#define ARM_SVC_SPM_RET_INVALID_PARAMS -2
+#define ARM_SVC_SPM_RET_DENIED -3
+#define ARM_SVC_SPM_RET_NO_MEMORY -5
+
+#define SPM_MAJOR_VERSION 0
+#define SPM_MINOR_VERSION 1
#endif // ARM_MM_SVC_H_
diff --git a/ArmPkg/Include/IndustryStandard/ArmStdSmc.h b/ArmPkg/Include/IndustryStandard/ArmStdSmc.h index 9116a291da..655edc21b2 100644 --- a/ArmPkg/Include/IndustryStandard/ArmStdSmc.h +++ b/ArmPkg/Include/IndustryStandard/ArmStdSmc.h @@ -17,64 +17,64 @@ * SMC function IDs for Standard Service queries
*/
-#define ARM_SMC_ID_STD_CALL_COUNT 0x8400ff00
-#define ARM_SMC_ID_STD_UID 0x8400ff01
+#define ARM_SMC_ID_STD_CALL_COUNT 0x8400ff00
+#define ARM_SMC_ID_STD_UID 0x8400ff01
/* 0x8400ff02 is reserved */
-#define ARM_SMC_ID_STD_REVISION 0x8400ff03
+#define ARM_SMC_ID_STD_REVISION 0x8400ff03
/*
* The 'Standard Service Call UID' is supposed to return the Standard
* Service UUID. This is a 128-bit value.
*/
-#define ARM_SMC_STD_UUID0 0x108d905b
-#define ARM_SMC_STD_UUID1 0x47e8f863
-#define ARM_SMC_STD_UUID2 0xfbc02dae
-#define ARM_SMC_STD_UUID3 0xe2f64156
+#define ARM_SMC_STD_UUID0 0x108d905b
+#define ARM_SMC_STD_UUID1 0x47e8f863
+#define ARM_SMC_STD_UUID2 0xfbc02dae
+#define ARM_SMC_STD_UUID3 0xe2f64156
/*
* ARM Standard Service Calls revision numbers
* The current revision is: 0.1
*/
-#define ARM_SMC_STD_REVISION_MAJOR 0x0
-#define ARM_SMC_STD_REVISION_MINOR 0x1
+#define ARM_SMC_STD_REVISION_MAJOR 0x0
+#define ARM_SMC_STD_REVISION_MINOR 0x1
/*
* Management Mode (MM) calls cover a subset of the Standard Service Call range.
* The list below is not exhaustive.
*/
-#define ARM_SMC_ID_MM_VERSION_AARCH32 0x84000040
-#define ARM_SMC_ID_MM_VERSION_AARCH64 0xC4000040
+#define ARM_SMC_ID_MM_VERSION_AARCH32 0x84000040
+#define ARM_SMC_ID_MM_VERSION_AARCH64 0xC4000040
// Request service from secure standalone MM environment
-#define ARM_SMC_ID_MM_COMMUNICATE_AARCH32 0x84000041
-#define ARM_SMC_ID_MM_COMMUNICATE_AARCH64 0xC4000041
+#define ARM_SMC_ID_MM_COMMUNICATE_AARCH32 0x84000041
+#define ARM_SMC_ID_MM_COMMUNICATE_AARCH64 0xC4000041
/* Generic ID when using AArch32 or AArch64 execution state */
#ifdef MDE_CPU_AARCH64
-#define ARM_SMC_ID_MM_COMMUNICATE ARM_SMC_ID_MM_COMMUNICATE_AARCH64
+#define ARM_SMC_ID_MM_COMMUNICATE ARM_SMC_ID_MM_COMMUNICATE_AARCH64
#endif
#ifdef MDE_CPU_ARM
-#define ARM_SMC_ID_MM_COMMUNICATE ARM_SMC_ID_MM_COMMUNICATE_AARCH32
+#define ARM_SMC_ID_MM_COMMUNICATE ARM_SMC_ID_MM_COMMUNICATE_AARCH32
#endif
/* MM return error codes */
-#define ARM_SMC_MM_RET_SUCCESS 0
-#define ARM_SMC_MM_RET_NOT_SUPPORTED -1
-#define ARM_SMC_MM_RET_INVALID_PARAMS -2
-#define ARM_SMC_MM_RET_DENIED -3
-#define ARM_SMC_MM_RET_NO_MEMORY -4
+#define ARM_SMC_MM_RET_SUCCESS 0
+#define ARM_SMC_MM_RET_NOT_SUPPORTED -1
+#define ARM_SMC_MM_RET_INVALID_PARAMS -2
+#define ARM_SMC_MM_RET_DENIED -3
+#define ARM_SMC_MM_RET_NO_MEMORY -4
// ARM Architecture Calls
-#define SMCCC_VERSION 0x80000000
-#define SMCCC_ARCH_FEATURES 0x80000001
-#define SMCCC_ARCH_SOC_ID 0x80000002
-#define SMCCC_ARCH_WORKAROUND_1 0x80008000
-#define SMCCC_ARCH_WORKAROUND_2 0x80007FFF
+#define SMCCC_VERSION 0x80000000
+#define SMCCC_ARCH_FEATURES 0x80000001
+#define SMCCC_ARCH_SOC_ID 0x80000002
+#define SMCCC_ARCH_WORKAROUND_1 0x80008000
+#define SMCCC_ARCH_WORKAROUND_2 0x80007FFF
#define SMC_ARCH_CALL_SUCCESS 0
-#define SMC_ARCH_CALL_NOT_SUPPORTED -1
-#define SMC_ARCH_CALL_NOT_REQUIRED -2
-#define SMC_ARCH_CALL_INVALID_PARAMETER -3
+#define SMC_ARCH_CALL_NOT_SUPPORTED -1
+#define SMC_ARCH_CALL_NOT_REQUIRED -2
+#define SMC_ARCH_CALL_INVALID_PARAMETER -3
/*
* Power State Coordination Interface (PSCI) calls cover a subset of the
@@ -101,15 +101,15 @@ ((ARM_SMC_PSCI_VERSION_MAJOR << 16) | ARM_SMC_PSCI_VERSION_MINOR)
/* PSCI return error codes */
-#define ARM_SMC_PSCI_RET_SUCCESS 0
-#define ARM_SMC_PSCI_RET_NOT_SUPPORTED -1
-#define ARM_SMC_PSCI_RET_INVALID_PARAMS -2
-#define ARM_SMC_PSCI_RET_DENIED -3
-#define ARM_SMC_PSCI_RET_ALREADY_ON -4
-#define ARM_SMC_PSCI_RET_ON_PENDING -5
-#define ARM_SMC_PSCI_RET_INTERN_FAIL -6
-#define ARM_SMC_PSCI_RET_NOT_PRESENT -7
-#define ARM_SMC_PSCI_RET_DISABLED -8
+#define ARM_SMC_PSCI_RET_SUCCESS 0
+#define ARM_SMC_PSCI_RET_NOT_SUPPORTED -1
+#define ARM_SMC_PSCI_RET_INVALID_PARAMS -2
+#define ARM_SMC_PSCI_RET_DENIED -3
+#define ARM_SMC_PSCI_RET_ALREADY_ON -4
+#define ARM_SMC_PSCI_RET_ON_PENDING -5
+#define ARM_SMC_PSCI_RET_INTERN_FAIL -6
+#define ARM_SMC_PSCI_RET_NOT_PRESENT -7
+#define ARM_SMC_PSCI_RET_DISABLED -8
#define ARM_SMC_PSCI_TARGET_CPU32(Aff2, Aff1, Aff0) \
((((Aff2) & 0xFF) << 16) | (((Aff1) & 0xFF) << 8) | ((Aff0) & 0xFF))
@@ -120,10 +120,10 @@ #define ARM_SMC_PSCI_TARGET_GET_AFF0(TargetId) ((TargetId) & 0xFF)
#define ARM_SMC_PSCI_TARGET_GET_AFF1(TargetId) (((TargetId) >> 8) & 0xFF)
-#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_0 0
-#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_1 1
-#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_2 2
-#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_3 3
+#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_0 0
+#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_1 1
+#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_2 2
+#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_3 3
#define ARM_SMC_ID_PSCI_AFFINITY_INFO_ON 0
#define ARM_SMC_ID_PSCI_AFFINITY_INFO_OFF 1
@@ -132,9 +132,9 @@ /*
* SMC function IDs for Trusted OS Service queries
*/
-#define ARM_SMC_ID_TOS_CALL_COUNT 0xbf00ff00
-#define ARM_SMC_ID_TOS_UID 0xbf00ff01
+#define ARM_SMC_ID_TOS_CALL_COUNT 0xbf00ff00
+#define ARM_SMC_ID_TOS_UID 0xbf00ff01
/* 0xbf00ff02 is reserved */
-#define ARM_SMC_ID_TOS_REVISION 0xbf00ff03
+#define ARM_SMC_ID_TOS_REVISION 0xbf00ff03
#endif // ARM_STD_SMC_H_
diff --git a/ArmPkg/Include/Library/ArmDisassemblerLib.h b/ArmPkg/Include/Library/ArmDisassemblerLib.h index d8c7af029d..f065ded5f3 100644 --- a/ArmPkg/Include/Library/ArmDisassemblerLib.h +++ b/ArmPkg/Include/Library/ArmDisassemblerLib.h @@ -26,12 +26,12 @@ **/
VOID
DisassembleInstruction (
- IN UINT8 **OpCodePtr,
- IN BOOLEAN Thumb,
- IN BOOLEAN Extended,
- IN OUT UINT32 *ItBlock,
- OUT CHAR8 *Buf,
- OUT UINTN Size
+ IN UINT8 **OpCodePtr,
+ IN BOOLEAN Thumb,
+ IN BOOLEAN Extended,
+ IN OUT UINT32 *ItBlock,
+ OUT CHAR8 *Buf,
+ OUT UINTN Size
);
#endif // ARM_DISASSEMBLER_LIB_H_
diff --git a/ArmPkg/Include/Library/ArmGenericTimerCounterLib.h b/ArmPkg/Include/Library/ArmGenericTimerCounterLib.h index 96bdffbf1e..45a32c6c2c 100644 --- a/ArmPkg/Include/Library/ArmGenericTimerCounterLib.h +++ b/ArmPkg/Include/Library/ArmGenericTimerCounterLib.h @@ -43,7 +43,7 @@ ArmGenericTimerGetTimerFreq ( VOID
EFIAPI
ArmGenericTimerSetTimerVal (
- IN UINTN Value
+ IN UINTN Value
);
UINTN
@@ -67,7 +67,7 @@ ArmGenericTimerGetTimerCtrlReg ( VOID
EFIAPI
ArmGenericTimerSetTimerCtrlReg (
- UINTN Value
+ UINTN Value
);
UINT64
@@ -79,7 +79,7 @@ ArmGenericTimerGetCompareVal ( VOID
EFIAPI
ArmGenericTimerSetCompareVal (
- IN UINT64 Value
+ IN UINT64 Value
);
#endif // ARM_GENERIC_TIMER_COUNTER_LIB_H_
diff --git a/ArmPkg/Include/Library/ArmGicArchLib.h b/ArmPkg/Include/Library/ArmGicArchLib.h index b3635d2268..72ac17e13b 100644 --- a/ArmPkg/Include/Library/ArmGicArchLib.h +++ b/ArmPkg/Include/Library/ArmGicArchLib.h @@ -17,7 +17,6 @@ typedef enum { ARM_GIC_ARCH_REVISION_3
} ARM_GIC_ARCH_REVISION;
-
ARM_GIC_ARCH_REVISION
EFIAPI
ArmGicGetSupportedArchRevision (
diff --git a/ArmPkg/Include/Library/ArmGicLib.h b/ArmPkg/Include/Library/ArmGicLib.h index b4c320be11..4ab6709675 100644 --- a/ArmPkg/Include/Library/ArmGicLib.h +++ b/ArmPkg/Include/Library/ArmGicLib.h @@ -12,36 +12,36 @@ #include <Library/ArmGicArchLib.h>
// GIC Distributor
-#define ARM_GIC_ICDDCR 0x000 // Distributor Control Register
-#define ARM_GIC_ICDICTR 0x004 // Interrupt Controller Type Register
-#define ARM_GIC_ICDIIDR 0x008 // Implementer Identification Register
+#define ARM_GIC_ICDDCR 0x000 // Distributor Control Register
+#define ARM_GIC_ICDICTR 0x004 // Interrupt Controller Type Register
+#define ARM_GIC_ICDIIDR 0x008 // Implementer Identification Register
// Each reg base below repeats for Number of interrupts / 4 (see GIC spec)
-#define ARM_GIC_ICDISR 0x080 // Interrupt Security Registers
-#define ARM_GIC_ICDISER 0x100 // Interrupt Set-Enable Registers
-#define ARM_GIC_ICDICER 0x180 // Interrupt Clear-Enable Registers
-#define ARM_GIC_ICDSPR 0x200 // Interrupt Set-Pending Registers
-#define ARM_GIC_ICDICPR 0x280 // Interrupt Clear-Pending Registers
-#define ARM_GIC_ICDABR 0x300 // Active Bit Registers
+#define ARM_GIC_ICDISR 0x080 // Interrupt Security Registers
+#define ARM_GIC_ICDISER 0x100 // Interrupt Set-Enable Registers
+#define ARM_GIC_ICDICER 0x180 // Interrupt Clear-Enable Registers
+#define ARM_GIC_ICDSPR 0x200 // Interrupt Set-Pending Registers
+#define ARM_GIC_ICDICPR 0x280 // Interrupt Clear-Pending Registers
+#define ARM_GIC_ICDABR 0x300 // Active Bit Registers
// Each reg base below repeats for Number of interrupts / 4
-#define ARM_GIC_ICDIPR 0x400 // Interrupt Priority Registers
+#define ARM_GIC_ICDIPR 0x400 // Interrupt Priority Registers
// Each reg base below repeats for Number of interrupts
-#define ARM_GIC_ICDIPTR 0x800 // Interrupt Processor Target Registers
-#define ARM_GIC_ICDICFR 0xC00 // Interrupt Configuration Registers
+#define ARM_GIC_ICDIPTR 0x800 // Interrupt Processor Target Registers
+#define ARM_GIC_ICDICFR 0xC00 // Interrupt Configuration Registers
-#define ARM_GIC_ICDPPISR 0xD00 // PPI Status register
+#define ARM_GIC_ICDPPISR 0xD00 // PPI Status register
// just one of these
-#define ARM_GIC_ICDSGIR 0xF00 // Software Generated Interrupt Register
+#define ARM_GIC_ICDSGIR 0xF00 // Software Generated Interrupt Register
// GICv3 specific registers
-#define ARM_GICD_IROUTER 0x6100 // Interrupt Routing Registers
+#define ARM_GICD_IROUTER 0x6100 // Interrupt Routing Registers
// GICD_CTLR bits
-#define ARM_GIC_ICDDCR_ARE (1 << 4) // Affinity Routing Enable (ARE)
-#define ARM_GIC_ICDDCR_DS (1 << 6) // Disable Security (DS)
+#define ARM_GIC_ICDDCR_ARE (1 << 4) // Affinity Routing Enable (ARE)
+#define ARM_GIC_ICDDCR_DS (1 << 6) // Disable Security (DS)
// GICD_ICDICFR bits
#define ARM_GIC_ICDICFR_WIDTH 32 // ICDICFR is a 32 bit register
@@ -52,125 +52,124 @@ #define ARM_GIC_ICDICFR_LEVEL_TRIGGERED 0x0 // Level triggered interrupt
#define ARM_GIC_ICDICFR_EDGE_TRIGGERED 0x1 // Edge triggered interrupt
-
// GIC Redistributor
-#define ARM_GICR_CTLR_FRAME_SIZE SIZE_64KB
-#define ARM_GICR_SGI_PPI_FRAME_SIZE SIZE_64KB
-#define ARM_GICR_SGI_VLPI_FRAME_SIZE SIZE_64KB
-#define ARM_GICR_SGI_RESERVED_FRAME_SIZE SIZE_64KB
+#define ARM_GICR_CTLR_FRAME_SIZE SIZE_64KB
+#define ARM_GICR_SGI_PPI_FRAME_SIZE SIZE_64KB
+#define ARM_GICR_SGI_VLPI_FRAME_SIZE SIZE_64KB
+#define ARM_GICR_SGI_RESERVED_FRAME_SIZE SIZE_64KB
// GIC Redistributor Control frame
-#define ARM_GICR_TYPER 0x0008 // Redistributor Type Register
+#define ARM_GICR_TYPER 0x0008 // Redistributor Type Register
// GIC Redistributor TYPER bit assignments
-#define ARM_GICR_TYPER_PLPIS (1 << 0) // Physical LPIs
-#define ARM_GICR_TYPER_VLPIS (1 << 1) // Virtual LPIs
-#define ARM_GICR_TYPER_DIRECTLPI (1 << 3) // Direct LPIs
-#define ARM_GICR_TYPER_LAST (1 << 4) // Last Redistributor in series
-#define ARM_GICR_TYPER_DPGS (1 << 5) // Disable Processor Group
+#define ARM_GICR_TYPER_PLPIS (1 << 0) // Physical LPIs
+#define ARM_GICR_TYPER_VLPIS (1 << 1) // Virtual LPIs
+#define ARM_GICR_TYPER_DIRECTLPI (1 << 3) // Direct LPIs
+#define ARM_GICR_TYPER_LAST (1 << 4) // Last Redistributor in series
+#define ARM_GICR_TYPER_DPGS (1 << 5) // Disable Processor Group
// Selection Support
-#define ARM_GICR_TYPER_PROCNO (0xFFFF << 8) // Processor Number
-#define ARM_GICR_TYPER_COMMONLPIAFF (0x3 << 24) // Common LPI Affinity
-#define ARM_GICR_TYPER_AFFINITY (0xFFFFFFFFULL << 32) // Redistributor Affinity
+#define ARM_GICR_TYPER_PROCNO (0xFFFF << 8) // Processor Number
+#define ARM_GICR_TYPER_COMMONLPIAFF (0x3 << 24) // Common LPI Affinity
+#define ARM_GICR_TYPER_AFFINITY (0xFFFFFFFFULL << 32) // Redistributor Affinity
#define ARM_GICR_TYPER_GET_AFFINITY(TypeReg) (((TypeReg) & \
ARM_GICR_TYPER_AFFINITY) >> 32)
// GIC SGI & PPI Redistributor frame
-#define ARM_GICR_ISENABLER 0x0100 // Interrupt Set-Enable Registers
-#define ARM_GICR_ICENABLER 0x0180 // Interrupt Clear-Enable Registers
+#define ARM_GICR_ISENABLER 0x0100 // Interrupt Set-Enable Registers
+#define ARM_GICR_ICENABLER 0x0180 // Interrupt Clear-Enable Registers
// GIC Cpu interface
-#define ARM_GIC_ICCICR 0x00 // CPU Interface Control Register
-#define ARM_GIC_ICCPMR 0x04 // Interrupt Priority Mask Register
-#define ARM_GIC_ICCBPR 0x08 // Binary Point Register
-#define ARM_GIC_ICCIAR 0x0C // Interrupt Acknowledge Register
-#define ARM_GIC_ICCEIOR 0x10 // End Of Interrupt Register
-#define ARM_GIC_ICCRPR 0x14 // Running Priority Register
-#define ARM_GIC_ICCPIR 0x18 // Highest Pending Interrupt Register
-#define ARM_GIC_ICCABPR 0x1C // Aliased Binary Point Register
-#define ARM_GIC_ICCIIDR 0xFC // Identification Register
-
-#define ARM_GIC_ICDSGIR_FILTER_TARGETLIST 0x0
-#define ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE 0x1
-#define ARM_GIC_ICDSGIR_FILTER_ITSELF 0x2
+#define ARM_GIC_ICCICR 0x00 // CPU Interface Control Register
+#define ARM_GIC_ICCPMR 0x04 // Interrupt Priority Mask Register
+#define ARM_GIC_ICCBPR 0x08 // Binary Point Register
+#define ARM_GIC_ICCIAR 0x0C // Interrupt Acknowledge Register
+#define ARM_GIC_ICCEIOR 0x10 // End Of Interrupt Register
+#define ARM_GIC_ICCRPR 0x14 // Running Priority Register
+#define ARM_GIC_ICCPIR 0x18 // Highest Pending Interrupt Register
+#define ARM_GIC_ICCABPR 0x1C // Aliased Binary Point Register
+#define ARM_GIC_ICCIIDR 0xFC // Identification Register
+
+#define ARM_GIC_ICDSGIR_FILTER_TARGETLIST 0x0
+#define ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE 0x1
+#define ARM_GIC_ICDSGIR_FILTER_ITSELF 0x2
// Bit-masks to configure the CPU Interface Control register
-#define ARM_GIC_ICCICR_ENABLE_SECURE 0x01
-#define ARM_GIC_ICCICR_ENABLE_NS 0x02
-#define ARM_GIC_ICCICR_ACK_CTL 0x04
-#define ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ 0x08
-#define ARM_GIC_ICCICR_USE_SBPR 0x10
+#define ARM_GIC_ICCICR_ENABLE_SECURE 0x01
+#define ARM_GIC_ICCICR_ENABLE_NS 0x02
+#define ARM_GIC_ICCICR_ACK_CTL 0x04
+#define ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ 0x08
+#define ARM_GIC_ICCICR_USE_SBPR 0x10
// Bit Mask for GICC_IIDR
-#define ARM_GIC_ICCIIDR_GET_PRODUCT_ID(IccIidr) (((IccIidr) >> 20) & 0xFFF)
-#define ARM_GIC_ICCIIDR_GET_ARCH_VERSION(IccIidr) (((IccIidr) >> 16) & 0xF)
-#define ARM_GIC_ICCIIDR_GET_REVISION(IccIidr) (((IccIidr) >> 12) & 0xF)
-#define ARM_GIC_ICCIIDR_GET_IMPLEMENTER(IccIidr) ((IccIidr) & 0xFFF)
+#define ARM_GIC_ICCIIDR_GET_PRODUCT_ID(IccIidr) (((IccIidr) >> 20) & 0xFFF)
+#define ARM_GIC_ICCIIDR_GET_ARCH_VERSION(IccIidr) (((IccIidr) >> 16) & 0xF)
+#define ARM_GIC_ICCIIDR_GET_REVISION(IccIidr) (((IccIidr) >> 12) & 0xF)
+#define ARM_GIC_ICCIIDR_GET_IMPLEMENTER(IccIidr) ((IccIidr) & 0xFFF)
// Bit Mask for
-#define ARM_GIC_ICCIAR_ACKINTID 0x3FF
+#define ARM_GIC_ICCIAR_ACKINTID 0x3FF
UINTN
EFIAPI
ArmGicGetInterfaceIdentification (
- IN INTN GicInterruptInterfaceBase
+ IN INTN GicInterruptInterfaceBase
);
// GIC Secure interfaces
VOID
EFIAPI
ArmGicSetupNonSecure (
- IN UINTN MpId,
- IN INTN GicDistributorBase,
- IN INTN GicInterruptInterfaceBase
+ IN UINTN MpId,
+ IN INTN GicDistributorBase,
+ IN INTN GicInterruptInterfaceBase
);
VOID
EFIAPI
ArmGicSetSecureInterrupts (
- IN UINTN GicDistributorBase,
- IN UINTN* GicSecureInterruptMask,
- IN UINTN GicSecureInterruptMaskSize
+ IN UINTN GicDistributorBase,
+ IN UINTN *GicSecureInterruptMask,
+ IN UINTN GicSecureInterruptMaskSize
);
VOID
EFIAPI
ArmGicEnableInterruptInterface (
- IN INTN GicInterruptInterfaceBase
+ IN INTN GicInterruptInterfaceBase
);
VOID
EFIAPI
ArmGicDisableInterruptInterface (
- IN INTN GicInterruptInterfaceBase
+ IN INTN GicInterruptInterfaceBase
);
VOID
EFIAPI
ArmGicEnableDistributor (
- IN INTN GicDistributorBase
+ IN INTN GicDistributorBase
);
VOID
EFIAPI
ArmGicDisableDistributor (
- IN INTN GicDistributorBase
+ IN INTN GicDistributorBase
);
UINTN
EFIAPI
ArmGicGetMaxNumInterrupts (
- IN INTN GicDistributorBase
+ IN INTN GicDistributorBase
);
VOID
EFIAPI
ArmGicSendSgiTo (
- IN INTN GicDistributorBase,
- IN INTN TargetListFilter,
- IN INTN CPUTargetList,
- IN INTN SgiId
+ IN INTN GicDistributorBase,
+ IN INTN TargetListFilter,
+ IN INTN CPUTargetList,
+ IN INTN SgiId
);
/*
@@ -190,55 +189,55 @@ ArmGicSendSgiTo ( UINTN
EFIAPI
ArmGicAcknowledgeInterrupt (
- IN UINTN GicInterruptInterfaceBase,
- OUT UINTN *InterruptId
+ IN UINTN GicInterruptInterfaceBase,
+ OUT UINTN *InterruptId
);
VOID
EFIAPI
ArmGicEndOfInterrupt (
- IN UINTN GicInterruptInterfaceBase,
- IN UINTN Source
+ IN UINTN GicInterruptInterfaceBase,
+ IN UINTN Source
);
UINTN
EFIAPI
ArmGicSetPriorityMask (
- IN INTN GicInterruptInterfaceBase,
- IN INTN PriorityMask
+ IN INTN GicInterruptInterfaceBase,
+ IN INTN PriorityMask
);
VOID
EFIAPI
ArmGicSetInterruptPriority (
- IN UINTN GicDistributorBase,
- IN UINTN GicRedistributorBase,
- IN UINTN Source,
- IN UINTN Priority
+ IN UINTN GicDistributorBase,
+ IN UINTN GicRedistributorBase,
+ IN UINTN Source,
+ IN UINTN Priority
);
VOID
EFIAPI
ArmGicEnableInterrupt (
- IN UINTN GicDistributorBase,
- IN UINTN GicRedistributorBase,
- IN UINTN Source
+ IN UINTN GicDistributorBase,
+ IN UINTN GicRedistributorBase,
+ IN UINTN Source
);
VOID
EFIAPI
ArmGicDisableInterrupt (
- IN UINTN GicDistributorBase,
- IN UINTN GicRedistributorBase,
- IN UINTN Source
+ IN UINTN GicDistributorBase,
+ IN UINTN GicRedistributorBase,
+ IN UINTN Source
);
BOOLEAN
EFIAPI
ArmGicIsInterruptEnabled (
- IN UINTN GicDistributorBase,
- IN UINTN GicRedistributorBase,
- IN UINTN Source
+ IN UINTN GicDistributorBase,
+ IN UINTN GicRedistributorBase,
+ IN UINTN Source
);
// GIC revision 2 specific declarations
@@ -251,41 +250,41 @@ ArmGicIsInterruptEnabled ( VOID
EFIAPI
ArmGicV2SetupNonSecure (
- IN UINTN MpId,
- IN INTN GicDistributorBase,
- IN INTN GicInterruptInterfaceBase
+ IN UINTN MpId,
+ IN INTN GicDistributorBase,
+ IN INTN GicInterruptInterfaceBase
);
VOID
EFIAPI
ArmGicV2EnableInterruptInterface (
- IN INTN GicInterruptInterfaceBase
+ IN INTN GicInterruptInterfaceBase
);
VOID
EFIAPI
ArmGicV2DisableInterruptInterface (
- IN INTN GicInterruptInterfaceBase
+ IN INTN GicInterruptInterfaceBase
);
UINTN
EFIAPI
ArmGicV2AcknowledgeInterrupt (
- IN UINTN GicInterruptInterfaceBase
+ IN UINTN GicInterruptInterfaceBase
);
VOID
EFIAPI
ArmGicV2EndOfInterrupt (
- IN UINTN GicInterruptInterfaceBase,
- IN UINTN Source
+ IN UINTN GicInterruptInterfaceBase,
+ IN UINTN Source
);
// GIC revision 3 specific declarations
-#define ICC_SRE_EL2_SRE (1 << 0)
+#define ICC_SRE_EL2_SRE (1 << 0)
-#define ARM_GICD_IROUTER_IRM BIT31
+#define ARM_GICD_IROUTER_IRM BIT31
UINT32
EFIAPI
@@ -296,7 +295,7 @@ ArmGicV3GetControlSystemRegisterEnable ( VOID
EFIAPI
ArmGicV3SetControlSystemRegisterEnable (
- IN UINT32 ControlSystemRegisterEnable
+ IN UINT32 ControlSystemRegisterEnable
);
VOID
@@ -320,17 +319,17 @@ ArmGicV3AcknowledgeInterrupt ( VOID
EFIAPI
ArmGicV3EndOfInterrupt (
- IN UINTN Source
+ IN UINTN Source
);
VOID
ArmGicV3SetBinaryPointer (
- IN UINTN BinaryPoint
+ IN UINTN BinaryPoint
);
VOID
ArmGicV3SetPriorityMask (
- IN UINTN Priority
+ IN UINTN Priority
);
#endif // ARMGIC_H_
diff --git a/ArmPkg/Include/Library/ArmHvcLib.h b/ArmPkg/Include/Library/ArmHvcLib.h index d202c2af6e..663ceb8e13 100644 --- a/ArmPkg/Include/Library/ArmHvcLib.h +++ b/ArmPkg/Include/Library/ArmHvcLib.h @@ -14,14 +14,14 @@ * The native size is used for the arguments.
*/
typedef struct {
- UINTN Arg0;
- UINTN Arg1;
- UINTN Arg2;
- UINTN Arg3;
- UINTN Arg4;
- UINTN Arg5;
- UINTN Arg6;
- UINTN Arg7;
+ UINTN Arg0;
+ UINTN Arg1;
+ UINTN Arg2;
+ UINTN Arg3;
+ UINTN Arg4;
+ UINTN Arg5;
+ UINTN Arg6;
+ UINTN Arg7;
} ARM_HVC_ARGS;
/**
@@ -34,7 +34,7 @@ typedef struct { **/
VOID
ArmCallHvc (
- IN OUT ARM_HVC_ARGS *Args
+ IN OUT ARM_HVC_ARGS *Args
);
#endif // ARM_HVC_LIB_H_
diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLib.h index 79ea755777..e4d0476090 100644 --- a/ArmPkg/Include/Library/ArmLib.h +++ b/ArmPkg/Include/Library/ArmLib.h @@ -15,13 +15,13 @@ #ifdef MDE_CPU_ARM
#include <Chipset/ArmV7.h>
-#elif defined(MDE_CPU_AARCH64)
+#elif defined (MDE_CPU_AARCH64)
#include <Chipset/AArch64.h>
#else
- #error "Unknown chipset."
+ #error "Unknown chipset."
#endif
-#define EFI_MEMORY_CACHETYPE_MASK (EFI_MEMORY_UC | EFI_MEMORY_WC | \
+#define EFI_MEMORY_CACHETYPE_MASK (EFI_MEMORY_UC | EFI_MEMORY_WC | \
EFI_MEMORY_WT | EFI_MEMORY_WB | \
EFI_MEMORY_UCE)
@@ -50,17 +50,21 @@ typedef enum { ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE
} ARM_MEMORY_REGION_ATTRIBUTES;
-#define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)
+#define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)
typedef struct {
- EFI_PHYSICAL_ADDRESS PhysicalBase;
- EFI_VIRTUAL_ADDRESS VirtualBase;
- UINT64 Length;
- ARM_MEMORY_REGION_ATTRIBUTES Attributes;
+ EFI_PHYSICAL_ADDRESS PhysicalBase;
+ EFI_VIRTUAL_ADDRESS VirtualBase;
+ UINT64 Length;
+ ARM_MEMORY_REGION_ATTRIBUTES Attributes;
} ARM_MEMORY_REGION_DESCRIPTOR;
-typedef VOID (*CACHE_OPERATION)(VOID);
-typedef VOID (*LINE_OPERATION)(UINTN);
+typedef VOID (*CACHE_OPERATION)(
+ VOID
+ );
+typedef VOID (*LINE_OPERATION)(
+ UINTN
+ );
//
// ARM Processor Mode
@@ -80,34 +84,34 @@ typedef enum { //
// ARM Cpu IDs
//
-#define ARM_CPU_IMPLEMENTER_MASK (0xFFU << 24)
-#define ARM_CPU_IMPLEMENTER_ARMLTD (0x41U << 24)
-#define ARM_CPU_IMPLEMENTER_DEC (0x44U << 24)
-#define ARM_CPU_IMPLEMENTER_MOT (0x4DU << 24)
-#define ARM_CPU_IMPLEMENTER_QUALCOMM (0x51U << 24)
-#define ARM_CPU_IMPLEMENTER_MARVELL (0x56U << 24)
-
-#define ARM_CPU_PRIMARY_PART_MASK (0xFFF << 4)
-#define ARM_CPU_PRIMARY_PART_CORTEXA5 (0xC05 << 4)
-#define ARM_CPU_PRIMARY_PART_CORTEXA7 (0xC07 << 4)
-#define ARM_CPU_PRIMARY_PART_CORTEXA8 (0xC08 << 4)
-#define ARM_CPU_PRIMARY_PART_CORTEXA9 (0xC09 << 4)
-#define ARM_CPU_PRIMARY_PART_CORTEXA15 (0xC0F << 4)
+#define ARM_CPU_IMPLEMENTER_MASK (0xFFU << 24)
+#define ARM_CPU_IMPLEMENTER_ARMLTD (0x41U << 24)
+#define ARM_CPU_IMPLEMENTER_DEC (0x44U << 24)
+#define ARM_CPU_IMPLEMENTER_MOT (0x4DU << 24)
+#define ARM_CPU_IMPLEMENTER_QUALCOMM (0x51U << 24)
+#define ARM_CPU_IMPLEMENTER_MARVELL (0x56U << 24)
+
+#define ARM_CPU_PRIMARY_PART_MASK (0xFFF << 4)
+#define ARM_CPU_PRIMARY_PART_CORTEXA5 (0xC05 << 4)
+#define ARM_CPU_PRIMARY_PART_CORTEXA7 (0xC07 << 4)
+#define ARM_CPU_PRIMARY_PART_CORTEXA8 (0xC08 << 4)
+#define ARM_CPU_PRIMARY_PART_CORTEXA9 (0xC09 << 4)
+#define ARM_CPU_PRIMARY_PART_CORTEXA15 (0xC0F << 4)
//
// ARM MP Core IDs
//
-#define ARM_CORE_AFF0 0xFF
-#define ARM_CORE_AFF1 (0xFF << 8)
-#define ARM_CORE_AFF2 (0xFF << 16)
-#define ARM_CORE_AFF3 (0xFFULL << 32)
-
-#define ARM_CORE_MASK ARM_CORE_AFF0
-#define ARM_CLUSTER_MASK ARM_CORE_AFF1
-#define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK)
-#define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8)
-#define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId))
-#define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)
+#define ARM_CORE_AFF0 0xFF
+#define ARM_CORE_AFF1 (0xFF << 8)
+#define ARM_CORE_AFF2 (0xFF << 16)
+#define ARM_CORE_AFF3 (0xFFULL << 32)
+
+#define ARM_CORE_MASK ARM_CORE_AFF0
+#define ARM_CLUSTER_MASK ARM_CORE_AFF1
+#define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK)
+#define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8)
+#define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId))
+#define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)
/** Reads the CCSIDR register for the specified cache.
@@ -118,7 +122,7 @@ typedef enum { **/
UINTN
ReadCCSIDR (
- IN UINT32 CSSELR
+ IN UINT32 CSSELR
);
/** Reads the CCSIDR2 for the specified cache.
@@ -129,7 +133,7 @@ ReadCCSIDR ( **/
UINT32
ReadCCSIDR2 (
- IN UINT32 CSSELR
+ IN UINT32 CSSELR
);
/** Reads the Cache Level ID (CLIDR) register.
@@ -183,7 +187,6 @@ ArmInvalidateDataCache ( VOID
);
-
VOID
EFIAPI
ArmCleanInvalidateDataCache (
@@ -205,31 +208,31 @@ ArmInvalidateInstructionCache ( VOID
EFIAPI
ArmInvalidateDataCacheEntryByMVA (
- IN UINTN Address
+ IN UINTN Address
);
VOID
EFIAPI
ArmCleanDataCacheEntryToPoUByMVA (
- IN UINTN Address
+ IN UINTN Address
);
VOID
EFIAPI
ArmInvalidateInstructionCacheEntryToPoUByMVA (
- IN UINTN Address
+ IN UINTN Address
);
VOID
EFIAPI
ArmCleanDataCacheEntryByMVA (
-IN UINTN Address
-);
+ IN UINTN Address
+ );
VOID
EFIAPI
ArmCleanInvalidateDataCacheEntryByMVA (
- IN UINTN Address
+ IN UINTN Address
);
VOID
@@ -352,8 +355,8 @@ ArmInvalidateTlb ( VOID
EFIAPI
ArmUpdateTranslationTableEntry (
- IN VOID *TranslationTableEntry,
- IN VOID *Mva
+ IN VOID *TranslationTableEntry,
+ IN VOID *Mva
);
VOID
@@ -371,7 +374,7 @@ ArmSetTTBR0 ( VOID
EFIAPI
ArmSetTTBCR (
- IN UINT32 Bits
+ IN UINT32 Bits
);
VOID *
@@ -431,7 +434,7 @@ ArmInstructionSynchronizationBarrier ( VOID
EFIAPI
ArmWriteVBar (
- IN UINTN VectorBase
+ IN UINTN VectorBase
);
UINTN
@@ -443,7 +446,7 @@ ArmReadVBar ( VOID
EFIAPI
ArmWriteAuxCr (
- IN UINT32 Bit
+ IN UINT32 Bit
);
UINT32
@@ -455,13 +458,13 @@ ArmReadAuxCr ( VOID
EFIAPI
ArmSetAuxCrBit (
- IN UINT32 Bits
+ IN UINT32 Bits
);
VOID
EFIAPI
ArmUnsetAuxCrBit (
- IN UINT32 Bits
+ IN UINT32 Bits
);
VOID
@@ -504,7 +507,7 @@ ArmReadCpacr ( VOID
EFIAPI
ArmWriteCpacr (
- IN UINT32 Access
+ IN UINT32 Access
);
VOID
@@ -534,7 +537,7 @@ ArmReadScr ( VOID
EFIAPI
ArmWriteScr (
- IN UINT32 Value
+ IN UINT32 Value
);
UINT32
@@ -546,7 +549,7 @@ ArmReadMVBar ( VOID
EFIAPI
ArmWriteMVBar (
- IN UINT32 VectorMonitorBase
+ IN UINT32 VectorMonitorBase
);
UINT32
@@ -558,7 +561,7 @@ ArmReadSctlr ( VOID
EFIAPI
ArmWriteSctlr (
- IN UINT32 Value
+ IN UINT32 Value
);
UINTN
@@ -570,10 +573,9 @@ ArmReadHVBar ( VOID
EFIAPI
ArmWriteHVBar (
- IN UINTN HypModeVectorBase
+ IN UINTN HypModeVectorBase
);
-
//
// Helper functions for accessing CPU ACTLR
//
@@ -587,28 +589,28 @@ ArmReadCpuActlr ( VOID
EFIAPI
ArmWriteCpuActlr (
- IN UINTN Val
+ IN UINTN Val
);
VOID
EFIAPI
ArmSetCpuActlrBit (
- IN UINTN Bits
+ IN UINTN Bits
);
VOID
EFIAPI
ArmUnsetCpuActlrBit (
- IN UINTN Bits
+ IN UINTN Bits
);
//
// Accessors for the architected generic timer registers
//
-#define ARM_ARCH_TIMER_ENABLE (1 << 0)
-#define ARM_ARCH_TIMER_IMASK (1 << 1)
-#define ARM_ARCH_TIMER_ISTATUS (1 << 2)
+#define ARM_ARCH_TIMER_ENABLE (1 << 0)
+#define ARM_ARCH_TIMER_IMASK (1 << 1)
+#define ARM_ARCH_TIMER_ISTATUS (1 << 2)
UINTN
EFIAPI
@@ -619,7 +621,7 @@ ArmReadCntFrq ( VOID
EFIAPI
ArmWriteCntFrq (
- UINTN FreqInHz
+ UINTN FreqInHz
);
UINT64
@@ -637,7 +639,7 @@ ArmReadCntkCtl ( VOID
EFIAPI
ArmWriteCntkCtl (
- UINTN Val
+ UINTN Val
);
UINTN
@@ -649,7 +651,7 @@ ArmReadCntpTval ( VOID
EFIAPI
ArmWriteCntpTval (
- UINTN Val
+ UINTN Val
);
UINTN
@@ -661,7 +663,7 @@ ArmReadCntpCtl ( VOID
EFIAPI
ArmWriteCntpCtl (
- UINTN Val
+ UINTN Val
);
UINTN
@@ -673,7 +675,7 @@ ArmReadCntvTval ( VOID
EFIAPI
ArmWriteCntvTval (
- UINTN Val
+ UINTN Val
);
UINTN
@@ -685,7 +687,7 @@ ArmReadCntvCtl ( VOID
EFIAPI
ArmWriteCntvCtl (
- UINTN Val
+ UINTN Val
);
UINT64
@@ -703,7 +705,7 @@ ArmReadCntpCval ( VOID
EFIAPI
ArmWriteCntpCval (
- UINT64 Val
+ UINT64 Val
);
UINT64
@@ -715,7 +717,7 @@ ArmReadCntvCval ( VOID
EFIAPI
ArmWriteCntvCval (
- UINT64 Val
+ UINT64 Val
);
UINT64
@@ -727,7 +729,7 @@ ArmReadCntvOff ( VOID
EFIAPI
ArmWriteCntvOff (
- UINT64 Val
+ UINT64 Val
);
UINTN
@@ -736,7 +738,6 @@ ArmGetPhysicalAddressBits ( VOID
);
-
///
/// ID Register Helper functions
///
@@ -768,6 +769,7 @@ ArmHasCcidx ( ///
/// AArch32-only ID Register Helper functions
///
+
/**
Check whether the CPU supports the Security extensions
@@ -779,6 +781,7 @@ EFIAPI ArmHasSecurityExtensions (
VOID
);
+
#endif // MDE_CPU_ARM
#endif // ARM_LIB_H_
diff --git a/ArmPkg/Include/Library/ArmMmuLib.h b/ArmPkg/Include/Library/ArmMmuLib.h index 410f06ce37..7538a8274a 100644 --- a/ArmPkg/Include/Library/ArmMmuLib.h +++ b/ArmPkg/Include/Library/ArmMmuLib.h @@ -24,29 +24,29 @@ ArmConfigureMmu ( EFI_STATUS
EFIAPI
ArmSetMemoryRegionNoExec (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
);
EFI_STATUS
EFIAPI
ArmClearMemoryRegionNoExec (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
);
EFI_STATUS
EFIAPI
ArmSetMemoryRegionReadOnly (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
);
EFI_STATUS
EFIAPI
ArmClearMemoryRegionReadOnly (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
);
VOID
@@ -59,9 +59,9 @@ ArmReplaceLiveTranslationEntry ( EFI_STATUS
ArmSetMemoryAttributes (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length,
- IN UINT64 Attributes
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN UINT64 Attributes
);
#endif // ARM_MMU_LIB_H_
diff --git a/ArmPkg/Include/Library/ArmMtlLib.h b/ArmPkg/Include/Library/ArmMtlLib.h index 35059bf789..3050f06167 100644 --- a/ArmPkg/Include/Library/ArmMtlLib.h +++ b/ArmPkg/Include/Library/ArmMtlLib.h @@ -18,37 +18,37 @@ #pragma pack(1)
typedef struct {
- UINT32 Reserved1;
- UINT32 ChannelStatus;
- UINT64 Reserved2;
- UINT32 Flags;
- UINT32 Length;
- UINT32 MessageHeader;
+ UINT32 Reserved1;
+ UINT32 ChannelStatus;
+ UINT64 Reserved2;
+ UINT32 Flags;
+ UINT32 Length;
+ UINT32 MessageHeader;
// NOTE: Since EDK2 does not allow flexible array member [] we declare
// here array of 1 element length. However below is used as a variable
// length array.
- UINT32 Payload[1]; // size less object gives offset to payload.
+ UINT32 Payload[1]; // size less object gives offset to payload.
} MTL_MAILBOX;
#pragma pack()
// Channel Type, Low-priority, and High-priority
typedef enum {
- MTL_CHANNEL_TYPE_LOW = 0,
+ MTL_CHANNEL_TYPE_LOW = 0,
MTL_CHANNEL_TYPE_HIGH = 1
} MTL_CHANNEL_TYPE;
typedef struct {
- UINT64 PhysicalAddress;
- UINT32 ModifyMask;
- UINT32 PreserveMask;
+ UINT64 PhysicalAddress;
+ UINT32 ModifyMask;
+ UINT32 PreserveMask;
} MTL_DOORBELL;
typedef struct {
- MTL_CHANNEL_TYPE ChannelType;
- MTL_MAILBOX * CONST MailBox;
- MTL_DOORBELL DoorBell;
+ MTL_CHANNEL_TYPE ChannelType;
+ MTL_MAILBOX *CONST MailBox;
+ MTL_DOORBELL DoorBell;
} MTL_CHANNEL;
/** Wait until channel is free.
@@ -71,7 +71,7 @@ MtlWaitUntilChannelFree ( @retval UINT32* Pointer to the payload.
**/
-UINT32*
+UINT32 *
MtlGetChannelPayload (
IN MTL_CHANNEL *Channel
);
@@ -127,5 +127,4 @@ MtlReceiveMessage ( OUT UINT32 *PayloadLength
);
-#endif /* ARM_MTL_LIB_H_ */
-
+#endif /* ARM_MTL_LIB_H_ */
diff --git a/ArmPkg/Include/Library/ArmSmcLib.h b/ArmPkg/Include/Library/ArmSmcLib.h index ced60b3c11..f5b45f0a8c 100644 --- a/ArmPkg/Include/Library/ArmSmcLib.h +++ b/ArmPkg/Include/Library/ArmSmcLib.h @@ -14,14 +14,14 @@ * The native size is used for the arguments.
*/
typedef struct {
- UINTN Arg0;
- UINTN Arg1;
- UINTN Arg2;
- UINTN Arg3;
- UINTN Arg4;
- UINTN Arg5;
- UINTN Arg6;
- UINTN Arg7;
+ UINTN Arg0;
+ UINTN Arg1;
+ UINTN Arg2;
+ UINTN Arg3;
+ UINTN Arg4;
+ UINTN Arg5;
+ UINTN Arg6;
+ UINTN Arg7;
} ARM_SMC_ARGS;
/**
@@ -34,7 +34,7 @@ typedef struct { **/
VOID
ArmCallSmc (
- IN OUT ARM_SMC_ARGS *Args
+ IN OUT ARM_SMC_ARGS *Args
);
#endif // ARM_SMC_LIB_H_
diff --git a/ArmPkg/Include/Library/ArmSvcLib.h b/ArmPkg/Include/Library/ArmSvcLib.h index d4a1a8f118..71a640b9c9 100644 --- a/ArmPkg/Include/Library/ArmSvcLib.h +++ b/ArmPkg/Include/Library/ArmSvcLib.h @@ -14,14 +14,14 @@ * The native size is used for the arguments.
*/
typedef struct {
- UINTN Arg0;
- UINTN Arg1;
- UINTN Arg2;
- UINTN Arg3;
- UINTN Arg4;
- UINTN Arg5;
- UINTN Arg6;
- UINTN Arg7;
+ UINTN Arg0;
+ UINTN Arg1;
+ UINTN Arg2;
+ UINTN Arg3;
+ UINTN Arg4;
+ UINTN Arg5;
+ UINTN Arg6;
+ UINTN Arg7;
} ARM_SVC_ARGS;
/**
@@ -40,7 +40,7 @@ typedef struct { **/
VOID
ArmCallSvc (
- IN OUT ARM_SVC_ARGS *Args
+ IN OUT ARM_SVC_ARGS *Args
);
#endif // ARM_SVC_LIB_H_
diff --git a/ArmPkg/Include/Library/DefaultExceptionHandlerLib.h b/ArmPkg/Include/Library/DefaultExceptionHandlerLib.h index 57dc555e13..63d5dc78de 100644 --- a/ArmPkg/Include/Library/DefaultExceptionHandlerLib.h +++ b/ArmPkg/Include/Library/DefaultExceptionHandlerLib.h @@ -18,8 +18,8 @@ **/
VOID
DefaultExceptionHandler (
- IN EFI_EXCEPTION_TYPE ExceptionType,
- IN OUT EFI_SYSTEM_CONTEXT SystemContext
+ IN EFI_EXCEPTION_TYPE ExceptionType,
+ IN OUT EFI_SYSTEM_CONTEXT SystemContext
);
#endif // DEFAULT_EXCEPTION_HANDLER_LIB_H_
diff --git a/ArmPkg/Include/Library/OemMiscLib.h b/ArmPkg/Include/Library/OemMiscLib.h index 0b03fe8d4d..569cd51352 100644 --- a/ArmPkg/Include/Library/OemMiscLib.h +++ b/ArmPkg/Include/Library/OemMiscLib.h @@ -8,15 +8,13 @@ *
**/
-
#ifndef OEM_MISC_LIB_H_
#define OEM_MISC_LIB_H_
#include <Uefi.h>
#include <IndustryStandard/SmBios.h>
-typedef enum
-{
+typedef enum {
CpuCacheL1 = 1,
CpuCacheL2,
CpuCacheL3,
@@ -27,37 +25,35 @@ typedef enum CpuCacheLevelMax
} OEM_MISC_CPU_CACHE_LEVEL;
-typedef struct
-{
- UINT8 Voltage; ///< Processor voltage
- UINT16 CurrentSpeed; ///< Current clock speed in MHz
- UINT16 MaxSpeed; ///< Maximum clock speed in MHz
- UINT16 ExternalClock; ///< External clock speed in MHz
- UINT16 CoreCount; ///< Number of cores available
- UINT16 CoresEnabled; ///< Number of cores enabled
- UINT16 ThreadCount; ///< Number of threads per processor
+typedef struct {
+ UINT8 Voltage; ///< Processor voltage
+ UINT16 CurrentSpeed; ///< Current clock speed in MHz
+ UINT16 MaxSpeed; ///< Maximum clock speed in MHz
+ UINT16 ExternalClock; ///< External clock speed in MHz
+ UINT16 CoreCount; ///< Number of cores available
+ UINT16 CoresEnabled; ///< Number of cores enabled
+ UINT16 ThreadCount; ///< Number of threads per processor
} OEM_MISC_PROCESSOR_DATA;
-typedef enum
-{
- ProductNameType01,
- SerialNumType01,
- UuidType01,
- SystemManufacturerType01,
- SkuNumberType01,
- FamilyType01,
- AssertTagType02,
- SerialNumberType02,
- BoardManufacturerType02,
- SkuNumberType02,
- ChassisLocationType02,
- AssetTagType03,
- SerialNumberType03,
- VersionType03,
- ChassisTypeType03,
- ManufacturerType03,
- SkuNumberType03,
- SmbiosHiiStringFieldMax
+typedef enum {
+ ProductNameType01,
+ SerialNumType01,
+ UuidType01,
+ SystemManufacturerType01,
+ SkuNumberType01,
+ FamilyType01,
+ AssertTagType02,
+ SerialNumberType02,
+ BoardManufacturerType02,
+ SkuNumberType02,
+ ChassisLocationType02,
+ AssetTagType03,
+ SerialNumberType03,
+ VersionType03,
+ ChassisTypeType03,
+ ManufacturerType03,
+ SkuNumberType03,
+ SmbiosHiiStringFieldMax
} OEM_MISC_SMBIOS_HII_STRING_FIELD;
/*
@@ -74,7 +70,7 @@ typedef enum UINTN
EFIAPI
OemGetCpuFreq (
- IN UINT8 ProcessorIndex
+ IN UINT8 ProcessorIndex
);
/** Gets information about the specified processor and stores it in
@@ -90,10 +86,10 @@ OemGetCpuFreq ( BOOLEAN
EFIAPI
OemGetProcessorInformation (
- IN UINTN ProcessorIndex,
- IN OUT PROCESSOR_STATUS_DATA *ProcessorStatus,
- IN OUT PROCESSOR_CHARACTERISTIC_FLAGS *ProcessorCharacteristics,
- IN OUT OEM_MISC_PROCESSOR_DATA *MiscProcessorData
+ IN UINTN ProcessorIndex,
+ IN OUT PROCESSOR_STATUS_DATA *ProcessorStatus,
+ IN OUT PROCESSOR_CHARACTERISTIC_FLAGS *ProcessorCharacteristics,
+ IN OUT OEM_MISC_PROCESSOR_DATA *MiscProcessorData
);
/** Gets information about the cache at the specified cache level.
@@ -109,11 +105,11 @@ OemGetProcessorInformation ( BOOLEAN
EFIAPI
OemGetCacheInformation (
- IN UINT8 ProcessorIndex,
- IN UINT8 CacheLevel,
- IN BOOLEAN DataCache,
- IN BOOLEAN UnifiedCache,
- IN OUT SMBIOS_TABLE_TYPE7 *SmbiosCacheTable
+ IN UINT8 ProcessorIndex,
+ IN UINT8 CacheLevel,
+ IN BOOLEAN DataCache,
+ IN BOOLEAN UnifiedCache,
+ IN OUT SMBIOS_TABLE_TYPE7 *SmbiosCacheTable
);
/** Gets the maximum number of processors supported by the platform.
@@ -145,7 +141,7 @@ OemGetChassisType ( BOOLEAN
EFIAPI
OemIsProcessorPresent (
- IN UINTN ProcessorIndex
+ IN UINTN ProcessorIndex
);
/** Updates the HII string for the specified field.
@@ -157,9 +153,9 @@ OemIsProcessorPresent ( VOID
EFIAPI
OemUpdateSmbiosInfo (
- IN EFI_HII_HANDLE HiiHandle,
- IN EFI_STRING_ID TokenToUpdate,
- IN OEM_MISC_SMBIOS_HII_STRING_FIELD Field
+ IN EFI_HII_HANDLE HiiHandle,
+ IN EFI_STRING_ID TokenToUpdate,
+ IN OEM_MISC_SMBIOS_HII_STRING_FIELD Field
);
/** Fetches the Type 32 boot information status.
diff --git a/ArmPkg/Include/Library/OpteeLib.h b/ArmPkg/Include/Library/OpteeLib.h index b9399d2e18..593c32b135 100644 --- a/ArmPkg/Include/Library/OpteeLib.h +++ b/ArmPkg/Include/Library/OpteeLib.h @@ -15,24 +15,24 @@ * The 'Trusted OS Call UID' is supposed to return the following UUID for
* OP-TEE OS. This is a 128-bit value.
*/
-#define OPTEE_OS_UID0 0x384fb3e0
-#define OPTEE_OS_UID1 0xe7f811e3
-#define OPTEE_OS_UID2 0xaf630002
-#define OPTEE_OS_UID3 0xa5d5c51b
+#define OPTEE_OS_UID0 0x384fb3e0
+#define OPTEE_OS_UID1 0xe7f811e3
+#define OPTEE_OS_UID2 0xaf630002
+#define OPTEE_OS_UID3 0xa5d5c51b
-#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_NONE 0x0
-#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_VALUE_INPUT 0x1
-#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_VALUE_OUTPUT 0x2
-#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_VALUE_INOUT 0x3
-#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_MEMORY_INPUT 0x9
-#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_MEMORY_OUTPUT 0xa
-#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_MEMORY_INOUT 0xb
+#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_NONE 0x0
+#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_VALUE_INPUT 0x1
+#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_VALUE_OUTPUT 0x2
+#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_VALUE_INOUT 0x3
+#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_MEMORY_INPUT 0x9
+#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_MEMORY_OUTPUT 0xa
+#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_MEMORY_INOUT 0xb
-#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_MASK 0xff
+#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_MASK 0xff
-#define OPTEE_SUCCESS 0x00000000
-#define OPTEE_ORIGIN_COMMUNICATION 0x00000002
-#define OPTEE_ERROR_COMMUNICATION 0xFFFF000E
+#define OPTEE_SUCCESS 0x00000000
+#define OPTEE_ORIGIN_COMMUNICATION 0x00000002
+#define OPTEE_ERROR_COMMUNICATION 0xFFFF000E
typedef struct {
UINT64 BufferAddress;
@@ -47,44 +47,44 @@ typedef struct { } OPTEE_MESSAGE_PARAM_VALUE;
typedef union {
- OPTEE_MESSAGE_PARAM_MEMORY Memory;
- OPTEE_MESSAGE_PARAM_VALUE Value;
+ OPTEE_MESSAGE_PARAM_MEMORY Memory;
+ OPTEE_MESSAGE_PARAM_VALUE Value;
} OPTEE_MESSAGE_PARAM_UNION;
typedef struct {
- UINT64 Attribute;
- OPTEE_MESSAGE_PARAM_UNION Union;
+ UINT64 Attribute;
+ OPTEE_MESSAGE_PARAM_UNION Union;
} OPTEE_MESSAGE_PARAM;
-#define OPTEE_MAX_CALL_PARAMS 4
+#define OPTEE_MAX_CALL_PARAMS 4
typedef struct {
- UINT32 Command;
- UINT32 Function;
- UINT32 Session;
- UINT32 CancelId;
- UINT32 Pad;
- UINT32 Return;
- UINT32 ReturnOrigin;
- UINT32 NumParams;
+ UINT32 Command;
+ UINT32 Function;
+ UINT32 Session;
+ UINT32 CancelId;
+ UINT32 Pad;
+ UINT32 Return;
+ UINT32 ReturnOrigin;
+ UINT32 NumParams;
// NumParams tells the actual number of element in Params
- OPTEE_MESSAGE_PARAM Params[OPTEE_MAX_CALL_PARAMS];
+ OPTEE_MESSAGE_PARAM Params[OPTEE_MAX_CALL_PARAMS];
} OPTEE_MESSAGE_ARG;
typedef struct {
- EFI_GUID Uuid; // [in] GUID/UUID of the Trusted Application
- UINT32 Session; // [out] Session id
- UINT32 Return; // [out] Return value
- UINT32 ReturnOrigin; // [out] Origin of the return value
+ EFI_GUID Uuid; // [in] GUID/UUID of the Trusted Application
+ UINT32 Session; // [out] Session id
+ UINT32 Return; // [out] Return value
+ UINT32 ReturnOrigin; // [out] Origin of the return value
} OPTEE_OPEN_SESSION_ARG;
typedef struct {
- UINT32 Function; // [in] Trusted Application function, specific to the TA
- UINT32 Session; // [in] Session id
- UINT32 Return; // [out] Return value
- UINT32 ReturnOrigin; // [out] Origin of the return value
- OPTEE_MESSAGE_PARAM Params[OPTEE_MAX_CALL_PARAMS]; // Params for function to be invoked
+ UINT32 Function; // [in] Trusted Application function, specific to the TA
+ UINT32 Session; // [in] Session id
+ UINT32 Return; // [out] Return value
+ UINT32 ReturnOrigin; // [out] Origin of the return value
+ OPTEE_MESSAGE_PARAM Params[OPTEE_MAX_CALL_PARAMS]; // Params for function to be invoked
} OPTEE_INVOKE_FUNCTION_ARG;
BOOLEAN
@@ -102,19 +102,19 @@ OpteeInit ( EFI_STATUS
EFIAPI
OpteeOpenSession (
- IN OUT OPTEE_OPEN_SESSION_ARG *OpenSessionArg
+ IN OUT OPTEE_OPEN_SESSION_ARG *OpenSessionArg
);
EFI_STATUS
EFIAPI
OpteeCloseSession (
- IN UINT32 Session
+ IN UINT32 Session
);
EFI_STATUS
EFIAPI
OpteeInvokeFunction (
- IN OUT OPTEE_INVOKE_FUNCTION_ARG *InvokeFunctionArg
+ IN OUT OPTEE_INVOKE_FUNCTION_ARG *InvokeFunctionArg
);
#endif // OPTEE_LIB_H_
diff --git a/ArmPkg/Include/Library/SemihostLib.h b/ArmPkg/Include/Library/SemihostLib.h index 590728c804..e0ff9251cb 100644 --- a/ArmPkg/Include/Library/SemihostLib.h +++ b/ArmPkg/Include/Library/SemihostLib.h @@ -17,12 +17,12 @@ *
*/
-#define SEMIHOST_FILE_MODE_READ (0 << 2)
-#define SEMIHOST_FILE_MODE_WRITE (1 << 2)
-#define SEMIHOST_FILE_MODE_APPEND (2 << 2)
-#define SEMIHOST_FILE_MODE_UPDATE (1 << 1)
-#define SEMIHOST_FILE_MODE_BINARY (1 << 0)
-#define SEMIHOST_FILE_MODE_ASCII (0 << 0)
+#define SEMIHOST_FILE_MODE_READ (0 << 2)
+#define SEMIHOST_FILE_MODE_WRITE (1 << 2)
+#define SEMIHOST_FILE_MODE_APPEND (2 << 2)
+#define SEMIHOST_FILE_MODE_UPDATE (1 << 1)
+#define SEMIHOST_FILE_MODE_BINARY (1 << 0)
+#define SEMIHOST_FILE_MODE_ASCII (0 << 0)
BOOLEAN
SemihostConnectionSupported (
@@ -31,9 +31,9 @@ SemihostConnectionSupported ( RETURN_STATUS
SemihostFileOpen (
- IN CHAR8 *FileName,
- IN UINT32 Mode,
- OUT UINTN *FileHandle
+ IN CHAR8 *FileName,
+ IN UINT32 Mode,
+ OUT UINTN *FileHandle
);
RETURN_STATUS
@@ -81,7 +81,7 @@ SemihostFileLength ( **/
RETURN_STATUS
-SemihostFileTmpName(
+SemihostFileTmpName (
OUT VOID *Buffer,
IN UINT8 Identifier,
IN UINTN Length
@@ -89,7 +89,7 @@ SemihostFileTmpName( RETURN_STATUS
SemihostFileRemove (
- IN CHAR8 *FileName
+ IN CHAR8 *FileName
);
/**
@@ -104,7 +104,7 @@ SemihostFileRemove ( **/
RETURN_STATUS
-SemihostFileRename(
+SemihostFileRename (
IN CHAR8 *FileName,
IN CHAR8 *NewFileName
);
@@ -116,17 +116,17 @@ SemihostReadCharacter ( VOID
SemihostWriteCharacter (
- IN CHAR8 Character
+ IN CHAR8 Character
);
VOID
SemihostWriteString (
- IN CHAR8 *String
+ IN CHAR8 *String
);
UINT32
SemihostSystem (
- IN CHAR8 *CommandLine
+ IN CHAR8 *CommandLine
);
#endif // SEMIHOSTING_LIB_H_
diff --git a/ArmPkg/Include/Library/StandaloneMmMmuLib.h b/ArmPkg/Include/Library/StandaloneMmMmuLib.h index ccc016d035..c27020def0 100644 --- a/ArmPkg/Include/Library/StandaloneMmMmuLib.h +++ b/ArmPkg/Include/Library/StandaloneMmMmuLib.h @@ -11,26 +11,26 @@ EFI_STATUS
ArmSetMemoryRegionNoExec (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
);
EFI_STATUS
ArmClearMemoryRegionNoExec (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
);
EFI_STATUS
ArmSetMemoryRegionReadOnly (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
);
EFI_STATUS
ArmClearMemoryRegionReadOnly (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
);
#endif /* STANDALONE_MM_MMU_LIB_ */
diff --git a/ArmPkg/Include/Ppi/ArmMpCoreInfo.h b/ArmPkg/Include/Ppi/ArmMpCoreInfo.h index b1e404ce13..c9f2ac6fc1 100644 --- a/ArmPkg/Include/Ppi/ArmMpCoreInfo.h +++ b/ArmPkg/Include/Ppi/ArmMpCoreInfo.h @@ -32,10 +32,10 @@ **/
typedef
EFI_STATUS
-(EFIAPI * ARM_MP_CORE_INFO_GET) (
+(EFIAPI *ARM_MP_CORE_INFO_GET)(
OUT UINTN *ArmCoreCount,
OUT ARM_CORE_INFO **ArmCoreTable
-);
+ );
///
/// This service abstracts the ability to migrate contents of the platform early memory store.
@@ -43,10 +43,10 @@ EFI_STATUS /// This PPI was optional.
///
typedef struct {
- ARM_MP_CORE_INFO_GET GetMpCoreInfo;
+ ARM_MP_CORE_INFO_GET GetMpCoreInfo;
} ARM_MP_CORE_INFO_PPI;
-extern EFI_GUID gArmMpCoreInfoPpiGuid;
-extern EFI_GUID gArmMpCoreInfoGuid;
+extern EFI_GUID gArmMpCoreInfoPpiGuid;
+extern EFI_GUID gArmMpCoreInfoGuid;
#endif // ARM_MP_CORE_INFO_PPI_H_
diff --git a/ArmPkg/Include/Protocol/ArmScmi.h b/ArmPkg/Include/Protocol/ArmScmi.h index aedea8f61f..93edec769c 100644 --- a/ArmPkg/Include/Protocol/ArmScmi.h +++ b/ArmPkg/Include/Protocol/ArmScmi.h @@ -15,7 +15,6 @@ /* As per SCMI specification, maximum allowed ASCII string length
for various return values/parameters of a SCMI message.
*/
-#define SCMI_MAX_STR_LEN 16
+#define SCMI_MAX_STR_LEN 16
#endif /* ARM_SCMI_H_ */
-
diff --git a/ArmPkg/Include/Protocol/ArmScmiBaseProtocol.h b/ArmPkg/Include/Protocol/ArmScmiBaseProtocol.h index c4b81c0f56..f6d97dd6da 100644 --- a/ArmPkg/Include/Protocol/ArmScmiBaseProtocol.h +++ b/ArmPkg/Include/Protocol/ArmScmiBaseProtocol.h @@ -17,24 +17,24 @@ #define BASE_PROTOCOL_VERSION_V1 0x10000
#define BASE_PROTOCOL_VERSION_V2 0x20000
-#define NUM_PROTOCOL_MASK 0xFFU
-#define NUM_AGENT_MASK 0xFFU
+#define NUM_PROTOCOL_MASK 0xFFU
+#define NUM_AGENT_MASK 0xFFU
-#define NUM_AGENT_SHIFT 0x8
+#define NUM_AGENT_SHIFT 0x8
/** Returns total number of protocols that are
implemented (excluding the Base protocol)
*/
-#define SCMI_TOTAL_PROTOCOLS(Attr) (Attr & NUM_PROTOCOL_MASK)
+#define SCMI_TOTAL_PROTOCOLS(Attr) (Attr & NUM_PROTOCOL_MASK)
// Returns total number of agents in the system.
-#define SCMI_TOTAL_AGENTS(Attr) ((Attr >> NUM_AGENT_SHIFT) & NUM_AGENT_MASK)
+#define SCMI_TOTAL_AGENTS(Attr) ((Attr >> NUM_AGENT_SHIFT) & NUM_AGENT_MASK)
#define ARM_SCMI_BASE_PROTOCOL_GUID { \
0xd7e5abe9, 0x33ab, 0x418e, {0x9f, 0x91, 0x72, 0xda, 0xe2, 0xba, 0x8e, 0x2f} \
}
-extern EFI_GUID gArmScmiBaseProtocolGuid;
+extern EFI_GUID gArmScmiBaseProtocolGuid;
typedef struct _SCMI_BASE_PROTOCOL SCMI_BASE_PROTOCOL;
@@ -50,7 +50,7 @@ typedef struct _SCMI_BASE_PROTOCOL SCMI_BASE_PROTOCOL; **/
typedef
EFI_STATUS
-(EFIAPI *SCMI_BASE_GET_VERSION) (
+(EFIAPI *SCMI_BASE_GET_VERSION)(
IN SCMI_BASE_PROTOCOL *This,
OUT UINT32 *Version
);
@@ -67,7 +67,7 @@ EFI_STATUS **/
typedef
EFI_STATUS
-(EFIAPI *SCMI_BASE_GET_TOTAL_PROTOCOLS) (
+(EFIAPI *SCMI_BASE_GET_TOTAL_PROTOCOLS)(
IN SCMI_BASE_PROTOCOL *This,
OUT UINT32 *TotalProtocols
);
@@ -85,7 +85,7 @@ EFI_STATUS **/
typedef
EFI_STATUS
-(EFIAPI *SCMI_BASE_DISCOVER_VENDOR) (
+(EFIAPI *SCMI_BASE_DISCOVER_VENDOR)(
IN SCMI_BASE_PROTOCOL *This,
OUT UINT8 VendorIdentifier[SCMI_MAX_STR_LEN]
);
@@ -103,7 +103,7 @@ EFI_STATUS **/
typedef
EFI_STATUS
-(EFIAPI *SCMI_BASE_DISCOVER_SUB_VENDOR) (
+(EFIAPI *SCMI_BASE_DISCOVER_SUB_VENDOR)(
IN SCMI_BASE_PROTOCOL *This,
OUT UINT8 VendorIdentifier[SCMI_MAX_STR_LEN]
);
@@ -120,7 +120,7 @@ EFI_STATUS **/
typedef
EFI_STATUS
-(EFIAPI *SCMI_BASE_DISCOVER_IMPLEMENTATION_VERSION) (
+(EFIAPI *SCMI_BASE_DISCOVER_IMPLEMENTATION_VERSION)(
IN SCMI_BASE_PROTOCOL *This,
OUT UINT32 *ImplementationVersion
);
@@ -141,7 +141,7 @@ EFI_STATUS **/
typedef
EFI_STATUS
-(EFIAPI *SCMI_BASE_DISCOVER_LIST_PROTOCOLS) (
+(EFIAPI *SCMI_BASE_DISCOVER_LIST_PROTOCOLS)(
IN SCMI_BASE_PROTOCOL *This,
IN OUT UINT32 *ProtocolListSize,
OUT UINT8 *ProtocolList
@@ -149,20 +149,20 @@ EFI_STATUS // Base protocol.
typedef struct _SCMI_BASE_PROTOCOL {
- SCMI_BASE_GET_VERSION GetVersion;
- SCMI_BASE_GET_TOTAL_PROTOCOLS GetTotalProtocols;
- SCMI_BASE_DISCOVER_VENDOR DiscoverVendor;
- SCMI_BASE_DISCOVER_SUB_VENDOR DiscoverSubVendor;
- SCMI_BASE_DISCOVER_IMPLEMENTATION_VERSION DiscoverImplementationVersion;
- SCMI_BASE_DISCOVER_LIST_PROTOCOLS DiscoverListProtocols;
+ SCMI_BASE_GET_VERSION GetVersion;
+ SCMI_BASE_GET_TOTAL_PROTOCOLS GetTotalProtocols;
+ SCMI_BASE_DISCOVER_VENDOR DiscoverVendor;
+ SCMI_BASE_DISCOVER_SUB_VENDOR DiscoverSubVendor;
+ SCMI_BASE_DISCOVER_IMPLEMENTATION_VERSION DiscoverImplementationVersion;
+ SCMI_BASE_DISCOVER_LIST_PROTOCOLS DiscoverListProtocols;
} SCMI_BASE_PROTOCOL;
// SCMI Message IDs for Base protocol.
typedef enum {
- ScmiMessageIdBaseDiscoverVendor = 0x3,
- ScmiMessageIdBaseDiscoverSubVendor = 0x4,
- ScmiMessageIdBaseDiscoverImplementationVersion = 0x5,
- ScmiMessageIdBaseDiscoverListProtocols = 0x6
+ ScmiMessageIdBaseDiscoverVendor = 0x3,
+ ScmiMessageIdBaseDiscoverSubVendor = 0x4,
+ ScmiMessageIdBaseDiscoverImplementationVersion = 0x5,
+ ScmiMessageIdBaseDiscoverListProtocols = 0x6
} SCMI_MESSAGE_ID_BASE;
#endif /* ARM_SCMI_BASE_PROTOCOL_H_ */
diff --git a/ArmPkg/Include/Protocol/ArmScmiClock2Protocol.h b/ArmPkg/Include/Protocol/ArmScmiClock2Protocol.h index 0e26491a62..d37d23f40c 100644 --- a/ArmPkg/Include/Protocol/ArmScmiClock2Protocol.h +++ b/ArmPkg/Include/Protocol/ArmScmiClock2Protocol.h @@ -15,13 +15,13 @@ #include <Protocol/ArmScmi.h>
#include <Protocol/ArmScmiClockProtocol.h>
-#define ARM_SCMI_CLOCK2_PROTOCOL_GUID { \
+#define ARM_SCMI_CLOCK2_PROTOCOL_GUID {\
0xb8d8caf2, 0x9e94, 0x462c, { 0xa8, 0x34, 0x6c, 0x99, 0xfc, 0x05, 0xef, 0xcf } \
}
-extern EFI_GUID gArmScmiClock2ProtocolGuid;
+extern EFI_GUID gArmScmiClock2ProtocolGuid;
-#define SCMI_CLOCK2_PROTOCOL_VERSION 1
+#define SCMI_CLOCK2_PROTOCOL_VERSION 1
typedef struct _SCMI_CLOCK2_PROTOCOL SCMI_CLOCK2_PROTOCOL;
@@ -39,7 +39,7 @@ typedef struct _SCMI_CLOCK2_PROTOCOL SCMI_CLOCK2_PROTOCOL; **/
typedef
EFI_STATUS
-(EFIAPI *SCMI_CLOCK2_GET_VERSION) (
+(EFIAPI *SCMI_CLOCK2_GET_VERSION)(
IN SCMI_CLOCK2_PROTOCOL *This,
OUT UINT32 *Version
);
@@ -57,7 +57,7 @@ EFI_STATUS **/
typedef
EFI_STATUS
-(EFIAPI *SCMI_CLOCK2_GET_TOTAL_CLOCKS) (
+(EFIAPI *SCMI_CLOCK2_GET_TOTAL_CLOCKS)(
IN SCMI_CLOCK2_PROTOCOL *This,
OUT UINT32 *TotalClocks
);
@@ -77,7 +77,7 @@ EFI_STATUS **/
typedef
EFI_STATUS
-(EFIAPI *SCMI_CLOCK2_GET_CLOCK_ATTRIBUTES) (
+(EFIAPI *SCMI_CLOCK2_GET_CLOCK_ATTRIBUTES)(
IN SCMI_CLOCK2_PROTOCOL *This,
IN UINT32 ClockId,
OUT BOOLEAN *Enabled,
@@ -109,7 +109,7 @@ EFI_STATUS **/
typedef
EFI_STATUS
-(EFIAPI *SCMI_CLOCK2_DESCRIBE_RATES) (
+(EFIAPI *SCMI_CLOCK2_DESCRIBE_RATES)(
IN SCMI_CLOCK2_PROTOCOL *This,
IN UINT32 ClockId,
OUT SCMI_CLOCK_RATE_FORMAT *Format,
@@ -131,7 +131,7 @@ EFI_STATUS **/
typedef
EFI_STATUS
-(EFIAPI *SCMI_CLOCK2_RATE_GET) (
+(EFIAPI *SCMI_CLOCK2_RATE_GET)(
IN SCMI_CLOCK2_PROTOCOL *This,
IN UINT32 ClockId,
OUT UINT64 *Rate
@@ -149,7 +149,7 @@ EFI_STATUS **/
typedef
EFI_STATUS
-(EFIAPI *SCMI_CLOCK2_RATE_SET) (
+(EFIAPI *SCMI_CLOCK2_RATE_SET)(
IN SCMI_CLOCK2_PROTOCOL *This,
IN UINT32 ClockId,
IN UINT64 Rate
@@ -168,24 +168,24 @@ EFI_STATUS **/
typedef
EFI_STATUS
-(EFIAPI *SCMI_CLOCK2_ENABLE) (
+(EFIAPI *SCMI_CLOCK2_ENABLE)(
IN SCMI_CLOCK2_PROTOCOL *This,
IN UINT32 ClockId,
IN BOOLEAN Enable
);
typedef struct _SCMI_CLOCK2_PROTOCOL {
- SCMI_CLOCK2_GET_VERSION GetVersion;
- SCMI_CLOCK2_GET_TOTAL_CLOCKS GetTotalClocks;
- SCMI_CLOCK2_GET_CLOCK_ATTRIBUTES GetClockAttributes;
- SCMI_CLOCK2_DESCRIBE_RATES DescribeRates;
- SCMI_CLOCK2_RATE_GET RateGet;
- SCMI_CLOCK2_RATE_SET RateSet;
+ SCMI_CLOCK2_GET_VERSION GetVersion;
+ SCMI_CLOCK2_GET_TOTAL_CLOCKS GetTotalClocks;
+ SCMI_CLOCK2_GET_CLOCK_ATTRIBUTES GetClockAttributes;
+ SCMI_CLOCK2_DESCRIBE_RATES DescribeRates;
+ SCMI_CLOCK2_RATE_GET RateGet;
+ SCMI_CLOCK2_RATE_SET RateSet;
// Extension to original ClockProtocol, added here so SCMI_CLOCK2_PROTOCOL
// can be cast to SCMI_CLOCK_PROTOCOL
- UINTN Version; // For future expandability
- SCMI_CLOCK2_ENABLE Enable;
+ UINTN Version; // For future expandability
+ SCMI_CLOCK2_ENABLE Enable;
} SCMI_CLOCK2_PROTOCOL;
#endif /* ARM_SCMI_CLOCK2_PROTOCOL_H_ */
diff --git a/ArmPkg/Include/Protocol/ArmScmiClockProtocol.h b/ArmPkg/Include/Protocol/ArmScmiClockProtocol.h index 4210a53cf9..7cdc61ff7c 100644 --- a/ArmPkg/Include/Protocol/ArmScmiClockProtocol.h +++ b/ArmPkg/Include/Protocol/ArmScmiClockProtocol.h @@ -14,11 +14,11 @@ #include <Protocol/ArmScmi.h>
-#define ARM_SCMI_CLOCK_PROTOCOL_GUID { \
+#define ARM_SCMI_CLOCK_PROTOCOL_GUID {\
0x91ce67a8, 0xe0aa, 0x4012, {0xb9, 0x9f, 0xb6, 0xfc, 0xf3, 0x4, 0x8e, 0xaa} \
}
-extern EFI_GUID gArmScmiClockProtocolGuid;
+extern EFI_GUID gArmScmiClockProtocolGuid;
// Message Type for clock management protocol.
typedef enum {
@@ -35,21 +35,21 @@ typedef enum { } SCMI_CLOCK_RATE_FORMAT;
// Clock management protocol version.
-#define SCMI_CLOCK_PROTOCOL_VERSION 0x10000
+#define SCMI_CLOCK_PROTOCOL_VERSION 0x10000
-#define SCMI_CLOCK_PROTOCOL_PENDING_ASYNC_RATES_MASK 0xFFU
-#define SCMI_CLOCK_PROTOCOL_PENDING_ASYNC_RATES_SHIFT 16
-#define SCMI_CLOCK_PROTOCOL_NUM_CLOCKS_MASK 0xFFFFU
+#define SCMI_CLOCK_PROTOCOL_PENDING_ASYNC_RATES_MASK 0xFFU
+#define SCMI_CLOCK_PROTOCOL_PENDING_ASYNC_RATES_SHIFT 16
+#define SCMI_CLOCK_PROTOCOL_NUM_CLOCKS_MASK 0xFFFFU
/** Total number of pending asynchronous clock rates changes
supported by the SCP, Attr Bits[23:16]
*/
-#define SCMI_CLOCK_PROTOCOL_MAX_ASYNC_CLK_RATES(Attr) ( \
+#define SCMI_CLOCK_PROTOCOL_MAX_ASYNC_CLK_RATES(Attr) ( \
(Attr >> SCMI_CLOCK_PROTOCOL_PENDING_ASYNC_RATES_SHIFT) && \
SCMI_CLOCK_PROTOCOL_PENDING_ASYNC_RATES_MASK)
// Total of clock devices supported by the SCP, Attr Bits[15:0]
-#define SCMI_CLOCK_PROTOCOL_TOTAL_CLKS(Attr) (Attr & SCMI_CLOCK_PROTOCOL_NUM_CLOCKS_MASK)
+#define SCMI_CLOCK_PROTOCOL_TOTAL_CLKS(Attr) (Attr & SCMI_CLOCK_PROTOCOL_NUM_CLOCKS_MASK)
#pragma pack(1)
@@ -57,18 +57,18 @@ typedef enum { either Rate or Min/Max/Step triplet is valid.
*/
typedef struct {
- UINT64 Min;
- UINT64 Max;
- UINT64 Step;
+ UINT64 Min;
+ UINT64 Max;
+ UINT64 Step;
} SCMI_CLOCK_RATE_CONTINUOUS;
typedef struct {
- UINT64 Rate;
+ UINT64 Rate;
} SCMI_CLOCK_RATE_DISCRETE;
typedef union {
- SCMI_CLOCK_RATE_CONTINUOUS ContinuousRate;
- SCMI_CLOCK_RATE_DISCRETE DiscreteRate;
+ SCMI_CLOCK_RATE_CONTINUOUS ContinuousRate;
+ SCMI_CLOCK_RATE_DISCRETE DiscreteRate;
} SCMI_CLOCK_RATE;
#pragma pack()
@@ -89,7 +89,7 @@ typedef struct _SCMI_CLOCK_PROTOCOL SCMI_CLOCK_PROTOCOL; **/
typedef
EFI_STATUS
-(EFIAPI *SCMI_CLOCK_GET_VERSION) (
+(EFIAPI *SCMI_CLOCK_GET_VERSION)(
IN SCMI_CLOCK_PROTOCOL *This,
OUT UINT32 *Version
);
@@ -107,7 +107,7 @@ EFI_STATUS **/
typedef
EFI_STATUS
-(EFIAPI *SCMI_CLOCK_GET_TOTAL_CLOCKS) (
+(EFIAPI *SCMI_CLOCK_GET_TOTAL_CLOCKS)(
IN SCMI_CLOCK_PROTOCOL *This,
OUT UINT32 *TotalClocks
);
@@ -127,7 +127,7 @@ EFI_STATUS **/
typedef
EFI_STATUS
-(EFIAPI *SCMI_CLOCK_GET_CLOCK_ATTRIBUTES) (
+(EFIAPI *SCMI_CLOCK_GET_CLOCK_ATTRIBUTES)(
IN SCMI_CLOCK_PROTOCOL *This,
IN UINT32 ClockId,
OUT BOOLEAN *Enabled,
@@ -159,7 +159,7 @@ EFI_STATUS **/
typedef
EFI_STATUS
-(EFIAPI *SCMI_CLOCK_DESCRIBE_RATES) (
+(EFIAPI *SCMI_CLOCK_DESCRIBE_RATES)(
IN SCMI_CLOCK_PROTOCOL *This,
IN UINT32 ClockId,
OUT SCMI_CLOCK_RATE_FORMAT *Format,
@@ -181,7 +181,7 @@ EFI_STATUS **/
typedef
EFI_STATUS
-(EFIAPI *SCMI_CLOCK_RATE_GET) (
+(EFIAPI *SCMI_CLOCK_RATE_GET)(
IN SCMI_CLOCK_PROTOCOL *This,
IN UINT32 ClockId,
OUT UINT64 *Rate
@@ -199,20 +199,19 @@ EFI_STATUS **/
typedef
EFI_STATUS
-(EFIAPI *SCMI_CLOCK_RATE_SET) (
+(EFIAPI *SCMI_CLOCK_RATE_SET)(
IN SCMI_CLOCK_PROTOCOL *This,
IN UINT32 ClockId,
IN UINT64 Rate
);
typedef struct _SCMI_CLOCK_PROTOCOL {
- SCMI_CLOCK_GET_VERSION GetVersion;
- SCMI_CLOCK_GET_TOTAL_CLOCKS GetTotalClocks;
- SCMI_CLOCK_GET_CLOCK_ATTRIBUTES GetClockAttributes;
- SCMI_CLOCK_DESCRIBE_RATES DescribeRates;
- SCMI_CLOCK_RATE_GET RateGet;
- SCMI_CLOCK_RATE_SET RateSet;
+ SCMI_CLOCK_GET_VERSION GetVersion;
+ SCMI_CLOCK_GET_TOTAL_CLOCKS GetTotalClocks;
+ SCMI_CLOCK_GET_CLOCK_ATTRIBUTES GetClockAttributes;
+ SCMI_CLOCK_DESCRIBE_RATES DescribeRates;
+ SCMI_CLOCK_RATE_GET RateGet;
+ SCMI_CLOCK_RATE_SET RateSet;
} SCMI_CLOCK_PROTOCOL;
#endif /* ARM_SCMI_CLOCK_PROTOCOL_H_ */
-
diff --git a/ArmPkg/Include/Protocol/ArmScmiPerformanceProtocol.h b/ArmPkg/Include/Protocol/ArmScmiPerformanceProtocol.h index 8c70aa7528..7e548e4765 100644 --- a/ArmPkg/Include/Protocol/ArmScmiPerformanceProtocol.h +++ b/ArmPkg/Include/Protocol/ArmScmiPerformanceProtocol.h @@ -20,15 +20,15 @@ 0x9b8ba84, 0x3dd3, 0x49a6, {0xa0, 0x5a, 0x31, 0x34, 0xa5, 0xf0, 0x7b, 0xad} \
}
-extern EFI_GUID gArmScmiPerformanceProtocolGuid;
+extern EFI_GUID gArmScmiPerformanceProtocolGuid;
typedef struct _SCMI_PERFORMANCE_PROTOCOL SCMI_PERFORMANCE_PROTOCOL;
#pragma pack(1)
-#define POWER_IN_MW_SHIFT 16
-#define POWER_IN_MW_MASK 0x1
-#define NUM_PERF_DOMAINS_MASK 0xFFFF
+#define POWER_IN_MW_SHIFT 16
+#define POWER_IN_MW_MASK 0x1
+#define NUM_PERF_DOMAINS_MASK 0xFFFF
// Total number of performance domains, Attr Bits [15:0]
#define SCMI_PERF_TOTAL_DOMAINS(Attr) (Attr & NUM_PERF_DOMAINS_MASK)
@@ -39,41 +39,41 @@ typedef struct _SCMI_PERFORMANCE_PROTOCOL SCMI_PERFORMANCE_PROTOCOL; // Performance protocol attributes return values.
typedef struct {
- UINT32 Attributes;
- UINT64 StatisticsAddress;
- UINT32 StatisticsLen;
+ UINT32 Attributes;
+ UINT64 StatisticsAddress;
+ UINT32 StatisticsLen;
} SCMI_PERFORMANCE_PROTOCOL_ATTRIBUTES;
-#define SCMI_PERF_SUPPORT_LVL_CHANGE_NOTIFY(Attr) ((Attr >> 28) & 0x1)
-#define SCMI_PERF_SUPPORT_LIM_CHANGE_NOTIFY(Attr) ((Attr >> 29) & 0x1)
-#define SCMI_PERF_SUPPORT_SET_LVL(Attr) ((Attr >> 30) & 0x1)
-#define SCMI_PERF_SUPPORT_SET_LIM(Attr) ((Attr >> 31) & 0x1)
-#define SCMI_PERF_RATE_LIMIT(RateLimit) (RateLimit & 0xFFF)
+#define SCMI_PERF_SUPPORT_LVL_CHANGE_NOTIFY(Attr) ((Attr >> 28) & 0x1)
+#define SCMI_PERF_SUPPORT_LIM_CHANGE_NOTIFY(Attr) ((Attr >> 29) & 0x1)
+#define SCMI_PERF_SUPPORT_SET_LVL(Attr) ((Attr >> 30) & 0x1)
+#define SCMI_PERF_SUPPORT_SET_LIM(Attr) ((Attr >> 31) & 0x1)
+#define SCMI_PERF_RATE_LIMIT(RateLimit) (RateLimit & 0xFFF)
// Performance protocol domain attributes.
typedef struct {
- UINT32 Attributes;
- UINT32 RateLimit;
- UINT32 SustainedFreq;
- UINT32 SustainedPerfLevel;
- UINT8 Name[SCMI_MAX_STR_LEN];
+ UINT32 Attributes;
+ UINT32 RateLimit;
+ UINT32 SustainedFreq;
+ UINT32 SustainedPerfLevel;
+ UINT8 Name[SCMI_MAX_STR_LEN];
} SCMI_PERFORMANCE_DOMAIN_ATTRIBUTES;
// Worst case latency in microseconds, Bits[15:0]
-#define PERF_LATENCY_MASK 0xFFFF
-#define SCMI_PERFORMANCE_PROTOCOL_LATENCY(Latency) (Latency & PERF_LATENCY_MASK)
+#define PERF_LATENCY_MASK 0xFFFF
+#define SCMI_PERFORMANCE_PROTOCOL_LATENCY(Latency) (Latency & PERF_LATENCY_MASK)
// Performance protocol performance level.
typedef struct {
- UINT32 Level;
- UINT32 PowerCost;
- UINT32 Latency;
+ UINT32 Level;
+ UINT32 PowerCost;
+ UINT32 Latency;
} SCMI_PERFORMANCE_LEVEL;
// Performance protocol performance limit.
typedef struct {
- UINT32 RangeMax;
- UINT32 RangeMin;
+ UINT32 RangeMax;
+ UINT32 RangeMin;
} SCMI_PERFORMANCE_LIMITS;
#pragma pack()
@@ -92,7 +92,7 @@ typedef struct { **/
typedef
EFI_STATUS
-(EFIAPI *SCMI_PERFORMANCE_GET_VERSION) (
+(EFIAPI *SCMI_PERFORMANCE_GET_VERSION)(
IN SCMI_PERFORMANCE_PROTOCOL *This,
OUT UINT32 *Version
);
@@ -109,7 +109,7 @@ EFI_STATUS **/
typedef
EFI_STATUS
-(EFIAPI *SCMI_PERFORMANCE_GET_ATTRIBUTES) (
+(EFIAPI *SCMI_PERFORMANCE_GET_ATTRIBUTES)(
IN SCMI_PERFORMANCE_PROTOCOL *This,
OUT SCMI_PERFORMANCE_PROTOCOL_ATTRIBUTES *Attributes
@@ -128,7 +128,7 @@ EFI_STATUS **/
typedef
EFI_STATUS
-(EFIAPI *SCMI_PERFORMANCE_GET_DOMAIN_ATTRIBUTES) (
+(EFIAPI *SCMI_PERFORMANCE_GET_DOMAIN_ATTRIBUTES)(
IN SCMI_PERFORMANCE_PROTOCOL *This,
IN UINT32 DomainId,
OUT SCMI_PERFORMANCE_DOMAIN_ATTRIBUTES *DomainAttributes
@@ -153,7 +153,7 @@ EFI_STATUS **/
typedef
EFI_STATUS
-(EFIAPI *SCMI_PERFORMANCE_DESCRIBE_LEVELS) (
+(EFIAPI *SCMI_PERFORMANCE_DESCRIBE_LEVELS)(
IN SCMI_PERFORMANCE_PROTOCOL *This,
IN UINT32 DomainId,
OUT UINT32 *NumLevels,
@@ -173,7 +173,7 @@ EFI_STATUS **/
typedef
EFI_STATUS
-(EFIAPI *SCMI_PERFORMANCE_LIMITS_SET) (
+(EFIAPI *SCMI_PERFORMANCE_LIMITS_SET)(
IN SCMI_PERFORMANCE_PROTOCOL *This,
IN UINT32 DomainId,
IN SCMI_PERFORMANCE_LIMITS *Limits
@@ -192,7 +192,7 @@ EFI_STATUS **/
typedef
EFI_STATUS
-(EFIAPI *SCMI_PERFORMANCE_LIMITS_GET) (
+(EFIAPI *SCMI_PERFORMANCE_LIMITS_GET)(
SCMI_PERFORMANCE_PROTOCOL *This,
UINT32 DomainId,
SCMI_PERFORMANCE_LIMITS *Limits
@@ -210,7 +210,7 @@ EFI_STATUS **/
typedef
EFI_STATUS
-(EFIAPI *SCMI_PERFORMANCE_LEVEL_SET) (
+(EFIAPI *SCMI_PERFORMANCE_LEVEL_SET)(
IN SCMI_PERFORMANCE_PROTOCOL *This,
IN UINT32 DomainId,
IN UINT32 Level
@@ -229,21 +229,21 @@ EFI_STATUS **/
typedef
EFI_STATUS
-(EFIAPI *SCMI_PERFORMANCE_LEVEL_GET) (
+(EFIAPI *SCMI_PERFORMANCE_LEVEL_GET)(
IN SCMI_PERFORMANCE_PROTOCOL *This,
IN UINT32 DomainId,
OUT UINT32 *Level
);
typedef struct _SCMI_PERFORMANCE_PROTOCOL {
- SCMI_PERFORMANCE_GET_VERSION GetVersion;
- SCMI_PERFORMANCE_GET_ATTRIBUTES GetProtocolAttributes;
- SCMI_PERFORMANCE_GET_DOMAIN_ATTRIBUTES GetDomainAttributes;
- SCMI_PERFORMANCE_DESCRIBE_LEVELS DescribeLevels;
- SCMI_PERFORMANCE_LIMITS_SET LimitsSet;
- SCMI_PERFORMANCE_LIMITS_GET LimitsGet;
- SCMI_PERFORMANCE_LEVEL_SET LevelSet;
- SCMI_PERFORMANCE_LEVEL_GET LevelGet;
+ SCMI_PERFORMANCE_GET_VERSION GetVersion;
+ SCMI_PERFORMANCE_GET_ATTRIBUTES GetProtocolAttributes;
+ SCMI_PERFORMANCE_GET_DOMAIN_ATTRIBUTES GetDomainAttributes;
+ SCMI_PERFORMANCE_DESCRIBE_LEVELS DescribeLevels;
+ SCMI_PERFORMANCE_LIMITS_SET LimitsSet;
+ SCMI_PERFORMANCE_LIMITS_GET LimitsGet;
+ SCMI_PERFORMANCE_LEVEL_SET LevelSet;
+ SCMI_PERFORMANCE_LEVEL_GET LevelGet;
} SCMI_PERFORMANCE_PROTOCOL;
typedef enum {
@@ -256,4 +256,3 @@ typedef enum { } SCMI_MESSAGE_ID_PERFORMANCE;
#endif /* ARM_SCMI_PERFORMANCE_PROTOCOL_H_ */
-
|