diff options
Diffstat (limited to 'ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.asm')
| -rw-r--r-- | ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.asm | 46 |
1 files changed, 16 insertions, 30 deletions
diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.asm b/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.asm index 8179232253..cbbe8dbe3d 100644 --- a/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.asm +++ b/ArmPkg/Library/ArmLib/ArmV7/ArmLibSupportV7.asm @@ -14,27 +14,13 @@ //------------------------------------------------------------------------------
- EXPORT ArmIsMpCore
- EXPORT ArmHasMpExtensions
- EXPORT ArmEnableAsynchronousAbort
- EXPORT ArmDisableAsynchronousAbort
- EXPORT ArmEnableIrq
- EXPORT ArmDisableIrq
- EXPORT ArmEnableFiq
- EXPORT ArmDisableFiq
- EXPORT ArmEnableInterrupts
- EXPORT ArmDisableInterrupts
- EXPORT ReadCCSIDR
- EXPORT ReadCLIDR
- EXPORT ArmReadNsacr
- EXPORT ArmWriteNsacr
-
- AREA ArmLibSupportV7, CODE, READONLY
+
+ INCLUDE AsmMacroExport.inc
//------------------------------------------------------------------------------
-ArmIsMpCore
+ RVCT_ASM_EXPORT ArmIsMpCore
mrc p15,0,R0,c0,c0,5
// Get Multiprocessing extension (bit31) & U bit (bit30)
and R0, R0, #0xC0000000
@@ -44,48 +30,48 @@ ArmIsMpCore movne R0, #0
bx LR
-ArmHasMpExtensions
+ RVCT_ASM_EXPORT ArmHasMpExtensions
mrc p15,0,R0,c0,c0,5
// Get Multiprocessing extension (bit31)
lsr R0, R0, #31
bx LR
-ArmEnableAsynchronousAbort
+ RVCT_ASM_EXPORT ArmEnableAsynchronousAbort
cpsie a
isb
bx LR
-ArmDisableAsynchronousAbort
+ RVCT_ASM_EXPORT ArmDisableAsynchronousAbort
cpsid a
isb
bx LR
-ArmEnableIrq
+ RVCT_ASM_EXPORT ArmEnableIrq
cpsie i
isb
bx LR
-ArmDisableIrq
+ RVCT_ASM_EXPORT ArmDisableIrq
cpsid i
isb
bx LR
-ArmEnableFiq
+ RVCT_ASM_EXPORT ArmEnableFiq
cpsie f
isb
bx LR
-ArmDisableFiq
+ RVCT_ASM_EXPORT ArmDisableFiq
cpsid f
isb
bx LR
-ArmEnableInterrupts
+ RVCT_ASM_EXPORT ArmEnableInterrupts
cpsie if
isb
bx LR
-ArmDisableInterrupts
+ RVCT_ASM_EXPORT ArmDisableInterrupts
cpsid if
isb
bx LR
@@ -94,7 +80,7 @@ ArmDisableInterrupts // ReadCCSIDR (
// IN UINT32 CSSELR
// )
-ReadCCSIDR
+ RVCT_ASM_EXPORT ReadCCSIDR
mcr p15,2,r0,c0,c0,0 ; Write Cache Size Selection Register (CSSELR)
isb
mrc p15,1,r0,c0,c0,0 ; Read current CP15 Cache Size ID Register (CCSIDR)
@@ -104,15 +90,15 @@ ReadCCSIDR // ReadCLIDR (
// IN UINT32 CSSELR
// )
-ReadCLIDR
+ RVCT_ASM_EXPORT ReadCLIDR
mrc p15,1,r0,c0,c0,1 ; Read CP15 Cache Level ID Register
bx lr
-ArmReadNsacr
+ RVCT_ASM_EXPORT ArmReadNsacr
mrc p15, 0, r0, c1, c1, 2
bx lr
-ArmWriteNsacr
+ RVCT_ASM_EXPORT ArmWriteNsacr
mcr p15, 0, r0, c1, c1, 2
bx lr
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