diff options
Diffstat (limited to 'ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S')
| -rw-r--r-- | ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S | 42 |
1 files changed, 21 insertions, 21 deletions
diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S index 954762717c..c31d49bcfb 100644 --- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S +++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S @@ -1,4 +1,4 @@ -#------------------------------------------------------------------------------
+#------------------------------------------------------------------------------
#
# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
# Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
@@ -63,13 +63,13 @@ GCC_ASM_EXPORT (ArmReadIdPfr1) ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
- mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line
+ mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line
dsb
isb
bx lr
ASM_PFX(ArmCleanDataCacheEntryByMVA):
- mcr p15, 0, r0, c7, c10, 1 @clean single data cache line
+ mcr p15, 0, r0, c7, c10, 1 @clean single data cache line
dsb
isb
bx lr
@@ -83,21 +83,21 @@ ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA): ASM_PFX(ArmInvalidateDataCacheEntryBySetWay):
- mcr p15, 0, r0, c7, c6, 2 @ Invalidate this line
+ mcr p15, 0, r0, c7, c6, 2 @ Invalidate this line
dsb
isb
bx lr
ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay):
- mcr p15, 0, r0, c7, c14, 2 @ Clean and Invalidate this line
+ mcr p15, 0, r0, c7, c14, 2 @ Clean and Invalidate this line
dsb
isb
bx lr
ASM_PFX(ArmCleanDataCacheEntryBySetWay):
- mcr p15, 0, r0, c7, c10, 2 @ Clean this line
+ mcr p15, 0, r0, c7, c10, 2 @ Clean this line
dsb
isb
bx lr
@@ -141,7 +141,7 @@ ASM_PFX(ArmDisableCachesAndMmu): ASM_PFX(ArmMmuEnabled):
mrc p15,0,R0,c1,c0,0
and R0,R0,#1
- bx LR
+ bx LR
ASM_PFX(ArmEnableDataCache):
ldr R1,=DC_ON
@@ -151,7 +151,7 @@ ASM_PFX(ArmEnableDataCache): dsb
isb
bx LR
-
+
ASM_PFX(ArmDisableDataCache):
ldr R1,=DC_ON
mrc p15,0,R0,c1,c0,0 @Read control register configuration data
@@ -169,7 +169,7 @@ ASM_PFX(ArmEnableInstructionCache): dsb
isb
bx LR
-
+
ASM_PFX(ArmDisableInstructionCache):
ldr R1,=IC_ON
mrc p15,0,R0,c1,c0,0 @Read control register configuration data
@@ -225,14 +225,14 @@ ASM_PFX(ArmV7AllDataCachesOperation): beq L_Finished
mov R10, #0
-Loop1:
+Loop1:
add R2, R10, R10, LSR #1 @ Work out 3xcachelevel
mov R12, R6, LSR R2 @ bottom 3 bits are the Cache type for this level
and R12, R12, #7 @ get those 3 bits alone
cmp R12, #2
blt L_Skip @ no cache or only instruction cache at this level
mcr p15, 2, R10, c0, c0, 0 @ write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
- isb @ isb to sync the change to the CacheSizeID reg
+ isb @ isb to sync the change to the CacheSizeID reg
mrc p15, 1, R12, c0, c0, 0 @ reads current Cache Size ID register (CCSIDR)
and R2, R12, #0x7 @ extract the line length field
add R2, R2, #4 @ add 4 for the line length offset (log2 16 bytes)
@@ -246,10 +246,10 @@ Loop1: sub R7, R7, #1
ands R7, R7, R12, LSR #13 @ R7 is the max number of the index size (right aligned)
-Loop2:
+Loop2:
mov R9, R4 @ R9 working copy of the max way size (right aligned)
-Loop3:
+Loop3:
orr R0, R10, R9, LSL R5 @ factor in the way number and cache number into R11
orr R0, R0, R7, LSL R2 @ factor in the index number
@@ -259,11 +259,11 @@ Loop3: bge Loop3
subs R7, R7, #1 @ decrement the index
bge Loop2
-L_Skip:
+L_Skip:
add R10, R10, #2 @ increment the cache number
cmp R3, R10
bgt Loop1
-
+
L_Finished:
dsb
ldmfd SP!, {r4-r12, lr}
@@ -285,7 +285,7 @@ Loop4: cmp R12, #2
blt Skip2 @ no cache or only instruction cache at this level
mcr p15, 2, R10, c0, c0, 0 @ write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
- isb @ isb to sync the change to the CacheSizeID reg
+ isb @ isb to sync the change to the CacheSizeID reg
mrc p15, 1, R12, c0, c0, 0 @ reads current Cache Size ID register (CCSIDR)
and R2, R12, #0x7 @ extract the line length field
add R2, R2, #4 @ add 4 for the line length offset (log2 16 bytes)
@@ -312,7 +312,7 @@ Skip2: add R10, R10, #2 @ increment the cache number
cmp R3, R10
bgt Loop4
-
+
Finished2:
dsb
ldmfd SP!, {r4-r12, lr}
@@ -321,12 +321,12 @@ Finished2: ASM_PFX(ArmDataMemoryBarrier):
dmb
bx LR
-
+
ASM_PFX(ArmDataSyncronizationBarrier):
ASM_PFX(ArmDrainWriteBuffer):
dsb
bx LR
-
+
ASM_PFX(ArmInstructionSynchronizationBarrier):
isb
bx LR
@@ -338,7 +338,7 @@ ASM_PFX(ArmReadVBar): ASM_PFX(ArmWriteVBar):
# Set the Address of the Vector Table in the VBAR register
- mcr p15, 0, r0, c12, c0, 0
+ mcr p15, 0, r0, c12, c0, 0
# Ensure the SCTLR.V bit is clear
mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
bic r0, r0, #0x00002000 @ clear V bit
@@ -376,7 +376,7 @@ ASM_PFX(ArmInvalidateInstructionAndDataTlb): ASM_PFX(ArmReadMpidr):
mrc p15, 0, r0, c0, c0, 5 @ read MPIDR
bx lr
-
+
ASM_PFX(ArmReadTpidrurw):
mrc p15, 0, r0, c13, c0, 2 @ read TPIDRURW
bx lr
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