diff options
Diffstat (limited to 'ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArm.c')
| -rw-r--r-- | ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArm.c | 41 |
1 files changed, 20 insertions, 21 deletions
diff --git a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArm.c b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArm.c index 7616fca425..ddee0e4489 100644 --- a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArm.c +++ b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArm.c @@ -23,21 +23,21 @@ **/
UINT64
SmbiosProcessorGetCacheSize (
- IN UINT8 CacheLevel,
- IN BOOLEAN DataCache,
- IN BOOLEAN UnifiedCache
+ IN UINT8 CacheLevel,
+ IN BOOLEAN DataCache,
+ IN BOOLEAN UnifiedCache
)
{
- CCSIDR_DATA Ccsidr;
- CCSIDR2_DATA Ccsidr2;
- CSSELR_DATA Csselr;
- BOOLEAN CcidxSupported;
- UINT64 CacheSize;
+ CCSIDR_DATA Ccsidr;
+ CCSIDR2_DATA Ccsidr2;
+ CSSELR_DATA Csselr;
+ BOOLEAN CcidxSupported;
+ UINT64 CacheSize;
// Read the CCSIDR register to get the cache architecture
- Csselr.Data = 0;
+ Csselr.Data = 0;
Csselr.Bits.Level = CacheLevel - 1;
- Csselr.Bits.InD = (!DataCache && !UnifiedCache);
+ Csselr.Bits.InD = (!DataCache && !UnifiedCache);
Ccsidr.Data = ReadCCSIDR (Csselr.Data);
@@ -45,13 +45,13 @@ SmbiosProcessorGetCacheSize ( if (CcidxSupported) {
Ccsidr2.Data = ReadCCSIDR2 (Csselr.Data);
- CacheSize = (1 << (Ccsidr.BitsCcidxAA32.LineSize + 4)) *
- (Ccsidr.BitsCcidxAA32.Associativity + 1) *
- (Ccsidr2.Bits.NumSets + 1);
+ CacheSize = (1 << (Ccsidr.BitsCcidxAA32.LineSize + 4)) *
+ (Ccsidr.BitsCcidxAA32.Associativity + 1) *
+ (Ccsidr2.Bits.NumSets + 1);
} else {
CacheSize = (1 << (Ccsidr.BitsNonCcidx.LineSize + 4)) *
- (Ccsidr.BitsNonCcidx.Associativity + 1) *
- (Ccsidr.BitsNonCcidx.NumSets + 1);
+ (Ccsidr.BitsNonCcidx.Associativity + 1) *
+ (Ccsidr.BitsNonCcidx.NumSets + 1);
}
return CacheSize;
@@ -67,9 +67,9 @@ SmbiosProcessorGetCacheSize ( **/
UINT32
SmbiosProcessorGetCacheAssociativity (
- IN UINT8 CacheLevel,
- IN BOOLEAN DataCache,
- IN BOOLEAN UnifiedCache
+ IN UINT8 CacheLevel,
+ IN BOOLEAN DataCache,
+ IN BOOLEAN UnifiedCache
)
{
CCSIDR_DATA Ccsidr;
@@ -78,9 +78,9 @@ SmbiosProcessorGetCacheAssociativity ( UINT32 Associativity;
// Read the CCSIDR register to get the cache architecture
- Csselr.Data = 0;
+ Csselr.Data = 0;
Csselr.Bits.Level = CacheLevel - 1;
- Csselr.Bits.InD = (!DataCache && !UnifiedCache);
+ Csselr.Bits.InD = (!DataCache && !UnifiedCache);
Ccsidr.Data = ReadCCSIDR (Csselr.Data);
@@ -94,4 +94,3 @@ SmbiosProcessorGetCacheAssociativity ( return Associativity;
}
-
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