diff options
Diffstat (limited to 'ArmPlatformPkg/PrePeiCore/MainMPCore.c')
| -rw-r--r-- | ArmPlatformPkg/PrePeiCore/MainMPCore.c | 47 |
1 files changed, 25 insertions, 22 deletions
diff --git a/ArmPlatformPkg/PrePeiCore/MainMPCore.c b/ArmPlatformPkg/PrePeiCore/MainMPCore.c index 859f1adf20..0b8e5dfb3f 100644 --- a/ArmPlatformPkg/PrePeiCore/MainMPCore.c +++ b/ArmPlatformPkg/PrePeiCore/MainMPCore.c @@ -24,7 +24,7 @@ VOID
EFIAPI
SecondaryMain (
- IN UINTN MpId
+ IN UINTN MpId
)
{
EFI_STATUS Status;
@@ -37,18 +37,21 @@ SecondaryMain ( ARM_CORE_INFO *ArmCoreInfoTable;
UINT32 ClusterId;
UINT32 CoreId;
- VOID (*SecondaryStart)(VOID);
- UINTN SecondaryEntryAddr;
- UINTN AcknowledgeInterrupt;
- UINTN InterruptId;
- ClusterId = GET_CLUSTER_ID(MpId);
- CoreId = GET_CORE_ID(MpId);
+ VOID (*SecondaryStart)(
+ VOID
+ );
+ UINTN SecondaryEntryAddr;
+ UINTN AcknowledgeInterrupt;
+ UINTN InterruptId;
+
+ ClusterId = GET_CLUSTER_ID (MpId);
+ CoreId = GET_CORE_ID (MpId);
// Get the gArmMpCoreInfoPpiGuid
PpiListSize = 0;
ArmPlatformGetPlatformPpiList (&PpiListSize, &PpiList);
- PpiListCount = PpiListSize / sizeof(EFI_PEI_PPI_DESCRIPTOR);
+ PpiListCount = PpiListSize / sizeof (EFI_PEI_PPI_DESCRIPTOR);
for (Index = 0; Index < PpiListCount; Index++, PpiList++) {
if (CompareGuid (PpiList->Guid, &gArmMpCoreInfoPpiGuid) == TRUE) {
break;
@@ -59,8 +62,8 @@ SecondaryMain ( ASSERT (Index != PpiListCount);
ArmMpCoreInfoPpi = PpiList->Ppi;
- ArmCoreCount = 0;
- Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable);
+ ArmCoreCount = 0;
+ Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable);
ASSERT_EFI_ERROR (Status);
// Find the core in the ArmCoreTable
@@ -92,11 +95,11 @@ SecondaryMain ( } while (SecondaryEntryAddr == 0);
// Jump to secondary core entry point.
- SecondaryStart = (VOID (*)())SecondaryEntryAddr;
- SecondaryStart();
+ SecondaryStart = (VOID (*)()) SecondaryEntryAddr;
+ SecondaryStart ();
// The secondaries shouldn't reach here
- ASSERT(FALSE);
+ ASSERT (FALSE);
}
VOID
@@ -105,26 +108,26 @@ PrimaryMain ( IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint
)
{
- EFI_SEC_PEI_HAND_OFF SecCoreData;
- UINTN PpiListSize;
- EFI_PEI_PPI_DESCRIPTOR *PpiList;
- UINTN TemporaryRamBase;
- UINTN TemporaryRamSize;
+ EFI_SEC_PEI_HAND_OFF SecCoreData;
+ UINTN PpiListSize;
+ EFI_PEI_PPI_DESCRIPTOR *PpiList;
+ UINTN TemporaryRamBase;
+ UINTN TemporaryRamSize;
CreatePpiList (&PpiListSize, &PpiList);
// Enable the GIC Distributor
- ArmGicEnableDistributor (PcdGet64(PcdGicDistributorBase));
+ ArmGicEnableDistributor (PcdGet64 (PcdGicDistributorBase));
// If ArmVe has not been built as Standalone then we need to wake up the secondary cores
if (FeaturePcdGet (PcdSendSgiToBringUpSecondaryCores)) {
// Sending SGI to all the Secondary CPU interfaces
- ArmGicSendSgiTo (PcdGet64(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId));
+ ArmGicSendSgiTo (PcdGet64 (PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId));
}
// Adjust the Temporary Ram as the new Ppi List (Common + Platform Ppi Lists) is created at
// the base of the primary core stack
- PpiListSize = ALIGN_VALUE(PpiListSize, CPU_STACK_ALIGNMENT);
+ PpiListSize = ALIGN_VALUE (PpiListSize, CPU_STACK_ALIGNMENT);
TemporaryRamBase = (UINTN)PcdGet64 (PcdCPUCoresStackBase) + PpiListSize;
TemporaryRamSize = (UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize) - PpiListSize;
@@ -133,7 +136,7 @@ PrimaryMain ( // Note: this must be in sync with the stuff in the asm file
// Note also: HOBs (pei temp ram) MUST be above stack
//
- SecCoreData.DataSize = sizeof(EFI_SEC_PEI_HAND_OFF);
+ SecCoreData.DataSize = sizeof (EFI_SEC_PEI_HAND_OFF);
SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet64 (PcdFvBaseAddress);
SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdFvSize);
SecCoreData.TemporaryRamBase = (VOID *)TemporaryRamBase; // We run on the primary core (and so we use the first stack)
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