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-rw-r--r--ArmPlatformPkg/PrePeiCore/PrePeiCore.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c
index ececd4c763..e165fd9456 100644
--- a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c
+++ b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c
@@ -87,7 +87,8 @@ CEntryPoint (
//
// Write VBAR - The Exception Vector table must be aligned to its requirement
- ASSERT (((UINTN)PeiVectorTable & ARM_VECTOR_TABLE_ALIGNMENT) == 0);
+ //TODO: Fix baseTools to ensure the Exception Vector Table is correctly aligned in AArch64
+ //ASSERT(((UINTN)PeiVectorTable & ARM_VECTOR_TABLE_ALIGNMENT) == 0);
ArmWriteVBar ((UINTN)PeiVectorTable);
//Note: The MMU will be enabled by MemoryPeim. Only the primary core will have the MMU on.