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-rw-r--r--ArmPlatformPkg/PrePeiCore/PrePeiCore.c24
1 files changed, 13 insertions, 11 deletions
diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c
index 9c4b25df95..8b86c6e69a 100644
--- a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c
+++ b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c
@@ -58,17 +58,19 @@ CEntryPoint (
IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint
)
{
- // Data Cache enabled on Primary core when MMU is enabled.
- ArmDisableDataCache ();
- // Invalidate instruction cache
- ArmInvalidateInstructionCache ();
- // Enable Instruction Caches on all cores.
- ArmEnableInstructionCache ();
-
- InvalidateDataCacheRange (
- (VOID *)(UINTN)PcdGet64 (PcdCPUCoresStackBase),
- PcdGet32 (PcdCPUCorePrimaryStackSize)
- );
+ if (!ArmMmuEnabled ()) {
+ // Data Cache enabled on Primary core when MMU is enabled.
+ ArmDisableDataCache ();
+ // Invalidate instruction cache
+ ArmInvalidateInstructionCache ();
+ // Enable Instruction Caches on all cores.
+ ArmEnableInstructionCache ();
+
+ InvalidateDataCacheRange (
+ (VOID *)(UINTN)PcdGet64 (PcdCPUCoresStackBase),
+ PcdGet32 (PcdCPUCorePrimaryStackSize)
+ );
+ }
//
// Note: Doesn't have to Enable CPU interface in non-secure world,