summaryrefslogtreecommitdiffstats
path: root/ArmPlatformPkg
diff options
context:
space:
mode:
Diffstat (limited to 'ArmPlatformPkg')
-rw-r--r--ArmPlatformPkg/PrePeiCore/PrePeiCore.c6
-rw-r--r--ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf1
-rw-r--r--ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf1
3 files changed, 6 insertions, 2 deletions
diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c
index 4f691d62cf..5202aa641e 100644
--- a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c
+++ b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c
@@ -8,6 +8,7 @@
**/
#include <Library/BaseLib.h>
+#include <Library/CacheMaintenanceLib.h>
#include <Library/DebugAgentLib.h>
#include <Library/ArmLib.h>
@@ -59,13 +60,14 @@ CEntryPoint (
{
// Data Cache enabled on Primary core when MMU is enabled.
ArmDisableDataCache ();
- // Invalidate Data cache
- ArmInvalidateDataCache ();
// Invalidate instruction cache
ArmInvalidateInstructionCache ();
// Enable Instruction Caches on all cores.
ArmEnableInstructionCache ();
+ InvalidateDataCacheRange ((VOID *)(UINTN)PcdGet64 (PcdCPUCoresStackBase),
+ PcdGet32 (PcdCPUCorePrimaryStackSize));
+
//
// Note: Doesn't have to Enable CPU interface in non-secure world,
// as Non-secure interface is already enabled in Secure world.
diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf b/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
index 104c7da533..fb01dd1a11 100644
--- a/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
+++ b/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
@@ -44,6 +44,7 @@
[LibraryClasses]
ArmLib
ArmPlatformLib
+ CacheMaintenanceLib
BaseLib
DebugLib
DebugAgentLib
diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf b/ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
index ceb173d34f..e9eb092d3a 100644
--- a/ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
+++ b/ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
@@ -44,6 +44,7 @@
[LibraryClasses]
ArmLib
ArmPlatformLib
+ CacheMaintenanceLib
BaseLib
DebugLib
DebugAgentLib