summaryrefslogtreecommitdiffstats
path: root/IntelFsp2Pkg/FspSecCore/Fsp22SecCoreS.inf
diff options
context:
space:
mode:
Diffstat (limited to 'IntelFsp2Pkg/FspSecCore/Fsp22SecCoreS.inf')
-rw-r--r--IntelFsp2Pkg/FspSecCore/Fsp22SecCoreS.inf10
1 files changed, 8 insertions, 2 deletions
diff --git a/IntelFsp2Pkg/FspSecCore/Fsp22SecCoreS.inf b/IntelFsp2Pkg/FspSecCore/Fsp22SecCoreS.inf
index 0a24eb2a8b..4a67388ddf 100644
--- a/IntelFsp2Pkg/FspSecCore/Fsp22SecCoreS.inf
+++ b/IntelFsp2Pkg/FspSecCore/Fsp22SecCoreS.inf
@@ -1,7 +1,7 @@
## @file
# Sec Core for FSP to support MultiPhase (SeparatePhase) SiInitialization.
#
-# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2020 - 2022, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -17,7 +17,7 @@
#
# The following information is for reference only and not required by the build tools.
#
-# VALID_ARCHITECTURES = IA32
+# VALID_ARCHITECTURES = IA32 X64
#
[Sources]
@@ -30,6 +30,12 @@
Ia32/FspApiEntryCommon.nasm
Ia32/FspHelper.nasm
+[Sources.X64]
+ X64/Stack.nasm
+ X64/Fsp22ApiEntryS.nasm
+ X64/FspApiEntryCommon.nasm
+ X64/FspHelper.nasm
+
[Binaries.Ia32]
RAW|Vtf0/Bin/ResetVec.ia32.raw |GCC