diff options
Diffstat (limited to 'MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c')
| -rw-r--r-- | MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c | 1039 |
1 files changed, 561 insertions, 478 deletions
diff --git a/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c b/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c index aec7d0cfbe..a240be940d 100644 --- a/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c +++ b/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c @@ -25,7 +25,7 @@ AhciReadReg ( IN UINT32 Offset
)
{
- UINT32 Data;
+ UINT32 Data;
ASSERT (PciIo != NULL);
@@ -35,7 +35,7 @@ AhciReadReg ( PciIo,
EfiPciIoWidthUint32,
EFI_AHCI_BAR_INDEX,
- (UINT64) Offset,
+ (UINT64)Offset,
1,
&Data
);
@@ -65,12 +65,12 @@ AhciWriteReg ( PciIo,
EfiPciIoWidthUint32,
EFI_AHCI_BAR_INDEX,
- (UINT64) Offset,
+ (UINT64)Offset,
1,
&Data
);
- return ;
+ return;
}
/**
@@ -89,11 +89,11 @@ AhciAndReg ( IN UINT32 AndData
)
{
- UINT32 Data;
+ UINT32 Data;
ASSERT (PciIo != NULL);
- Data = AhciReadReg (PciIo, Offset);
+ Data = AhciReadReg (PciIo, Offset);
Data &= AndData;
@@ -116,11 +116,11 @@ AhciOrReg ( IN UINT32 OrData
)
{
- UINT32 Data;
+ UINT32 Data;
ASSERT (PciIo != NULL);
- Data = AhciReadReg (PciIo, Offset);
+ Data = AhciReadReg (PciIo, Offset);
Data |= OrData;
@@ -143,16 +143,16 @@ AhciOrReg ( EFI_STATUS
EFIAPI
AhciWaitMmioSet (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN UINTN Offset,
- IN UINT32 MaskValue,
- IN UINT32 TestValue,
- IN UINT64 Timeout
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN UINTN Offset,
+ IN UINT32 MaskValue,
+ IN UINT32 TestValue,
+ IN UINT64 Timeout
)
{
- UINT32 Value;
- UINT64 Delay;
- BOOLEAN InfiniteWait;
+ UINT32 Value;
+ UINT64 Delay;
+ BOOLEAN InfiniteWait;
if (Timeout == 0) {
InfiniteWait = TRUE;
@@ -166,7 +166,7 @@ AhciWaitMmioSet ( //
// Access PCI MMIO space to see if the value is the tested one.
//
- Value = AhciReadReg (PciIo, (UINT32) Offset) & MaskValue;
+ Value = AhciReadReg (PciIo, (UINT32)Offset) & MaskValue;
if (Value == TestValue) {
return EFI_SUCCESS;
@@ -178,7 +178,6 @@ AhciWaitMmioSet ( MicroSecondDelay (100);
Delay--;
-
} while (InfiniteWait || (Delay > 0));
return EFI_TIMEOUT;
@@ -199,15 +198,15 @@ AhciWaitMmioSet ( EFI_STATUS
EFIAPI
AhciWaitMemSet (
- IN EFI_PHYSICAL_ADDRESS Address,
- IN UINT32 MaskValue,
- IN UINT32 TestValue,
- IN UINT64 Timeout
+ IN EFI_PHYSICAL_ADDRESS Address,
+ IN UINT32 MaskValue,
+ IN UINT32 TestValue,
+ IN UINT64 Timeout
)
{
- UINT32 Value;
- UINT64 Delay;
- BOOLEAN InfiniteWait;
+ UINT32 Value;
+ UINT64 Delay;
+ BOOLEAN InfiniteWait;
if (Timeout == 0) {
InfiniteWait = TRUE;
@@ -226,7 +225,7 @@ AhciWaitMemSet ( // compiler from optimizing the access to the memory address
// to only read once.
//
- Value = *(volatile UINT32 *) (UINTN) Address;
+ Value = *(volatile UINT32 *)(UINTN)Address;
Value &= MaskValue;
if (Value == TestValue) {
@@ -239,7 +238,6 @@ AhciWaitMemSet ( MicroSecondDelay (100);
Delay--;
-
} while (InfiniteWait || (Delay > 0));
return EFI_TIMEOUT;
@@ -258,14 +256,14 @@ AhciWaitMemSet ( EFI_STATUS
EFIAPI
AhciCheckMemSet (
- IN UINTN Address,
- IN UINT32 MaskValue,
- IN UINT32 TestValue
+ IN UINTN Address,
+ IN UINT32 MaskValue,
+ IN UINT32 TestValue
)
{
- UINT32 Value;
+ UINT32 Value;
- Value = *(volatile UINT32 *) Address;
+ Value = *(volatile UINT32 *)Address;
Value &= MaskValue;
if (Value == TestValue) {
@@ -275,7 +273,6 @@ AhciCheckMemSet ( return EFI_NOT_READY;
}
-
/**
Clear the port interrupt and error status. It will also clear
@@ -288,11 +285,11 @@ AhciCheckMemSet ( VOID
EFIAPI
AhciClearPortStatus (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN UINT8 Port
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN UINT8 Port
)
{
- UINT32 Offset;
+ UINT32 Offset;
//
// Clear any error status
@@ -325,16 +322,16 @@ AhciClearPortStatus ( VOID
EFIAPI
AhciDumpPortStatus (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN EFI_AHCI_REGISTERS *AhciRegisters,
- IN UINT8 Port,
- IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN EFI_AHCI_REGISTERS *AhciRegisters,
+ IN UINT8 Port,
+ IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock
)
{
- UINTN Offset;
- UINT32 Data;
- UINTN FisBaseAddr;
- EFI_STATUS Status;
+ UINTN Offset;
+ UINT32 Data;
+ UINTN FisBaseAddr;
+ EFI_STATUS Status;
ASSERT (PciIo != NULL);
@@ -358,7 +355,7 @@ AhciDumpPortStatus ( Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_TFD;
Data = AhciReadReg (PciIo, (UINT32)Offset);
- AtaStatusBlock->AtaStatus = (UINT8)Data;
+ AtaStatusBlock->AtaStatus = (UINT8)Data;
if ((AtaStatusBlock->AtaStatus & BIT0) != 0) {
AtaStatusBlock->AtaError = (UINT8)(Data >> 8);
}
@@ -366,7 +363,6 @@ AhciDumpPortStatus ( }
}
-
/**
Enable the FIS running for giving port.
@@ -382,12 +378,12 @@ AhciDumpPortStatus ( EFI_STATUS
EFIAPI
AhciEnableFisReceive (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN UINT8 Port,
- IN UINT64 Timeout
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN UINT8 Port,
+ IN UINT64 Timeout
)
{
- UINT32 Offset;
+ UINT32 Offset;
Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_CMD_FRE);
@@ -411,13 +407,13 @@ AhciEnableFisReceive ( EFI_STATUS
EFIAPI
AhciDisableFisReceive (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN UINT8 Port,
- IN UINT64 Timeout
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN UINT8 Port,
+ IN UINT64 Timeout
)
{
- UINT32 Offset;
- UINT32 Data;
+ UINT32 Offset;
+ UINT32 Data;
Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
Data = AhciReadReg (PciIo, Offset);
@@ -436,7 +432,7 @@ AhciDisableFisReceive ( return EFI_SUCCESS;
}
- AhciAndReg (PciIo, Offset, (UINT32)~(EFI_AHCI_PORT_CMD_FRE));
+ AhciAndReg (PciIo, Offset, (UINT32) ~(EFI_AHCI_PORT_CMD_FRE));
return AhciWaitMmioSet (
PciIo,
@@ -447,8 +443,6 @@ AhciDisableFisReceive ( );
}
-
-
/**
Build the command list, command table and prepare the fis receiver.
@@ -468,26 +462,26 @@ AhciDisableFisReceive ( VOID
EFIAPI
AhciBuildCommand (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN EFI_AHCI_REGISTERS *AhciRegisters,
- IN UINT8 Port,
- IN UINT8 PortMultiplier,
- IN EFI_AHCI_COMMAND_FIS *CommandFis,
- IN EFI_AHCI_COMMAND_LIST *CommandList,
- IN EFI_AHCI_ATAPI_COMMAND *AtapiCommand OPTIONAL,
- IN UINT8 AtapiCommandLength,
- IN UINT8 CommandSlotNumber,
- IN OUT VOID *DataPhysicalAddr,
- IN UINT32 DataLength
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN EFI_AHCI_REGISTERS *AhciRegisters,
+ IN UINT8 Port,
+ IN UINT8 PortMultiplier,
+ IN EFI_AHCI_COMMAND_FIS *CommandFis,
+ IN EFI_AHCI_COMMAND_LIST *CommandList,
+ IN EFI_AHCI_ATAPI_COMMAND *AtapiCommand OPTIONAL,
+ IN UINT8 AtapiCommandLength,
+ IN UINT8 CommandSlotNumber,
+ IN OUT VOID *DataPhysicalAddr,
+ IN UINT32 DataLength
)
{
- UINT64 BaseAddr;
- UINT32 PrdtNumber;
- UINT32 PrdtIndex;
- UINTN RemainedData;
- UINTN MemAddr;
- DATA_64 Data64;
- UINT32 Offset;
+ UINT64 BaseAddr;
+ UINT32 PrdtNumber;
+ UINT32 PrdtIndex;
+ UINTN RemainedData;
+ UINTN MemAddr;
+ DATA_64 Data64;
+ UINT32 Offset;
//
// Filling the PRDT
@@ -501,11 +495,11 @@ AhciBuildCommand ( //
ASSERT (PrdtNumber <= 65535);
- Data64.Uint64 = (UINTN) (AhciRegisters->AhciRFis) + sizeof (EFI_AHCI_RECEIVED_FIS) * Port;
+ Data64.Uint64 = (UINTN)(AhciRegisters->AhciRFis) + sizeof (EFI_AHCI_RECEIVED_FIS) * Port;
BaseAddr = Data64.Uint64;
- ZeroMem ((VOID *)((UINTN) BaseAddr), sizeof (EFI_AHCI_RECEIVED_FIS));
+ ZeroMem ((VOID *)((UINTN)BaseAddr), sizeof (EFI_AHCI_RECEIVED_FIS));
ZeroMem (AhciRegisters->AhciCommandTable, sizeof (EFI_AHCI_COMMAND_TABLE));
@@ -526,11 +520,11 @@ AhciBuildCommand ( AhciOrReg (PciIo, Offset, (EFI_AHCI_PORT_CMD_DLAE | EFI_AHCI_PORT_CMD_ATAPI));
} else {
- AhciAndReg (PciIo, Offset, (UINT32)~(EFI_AHCI_PORT_CMD_DLAE | EFI_AHCI_PORT_CMD_ATAPI));
+ AhciAndReg (PciIo, Offset, (UINT32) ~(EFI_AHCI_PORT_CMD_DLAE | EFI_AHCI_PORT_CMD_ATAPI));
}
- RemainedData = (UINTN) DataLength;
- MemAddr = (UINTN) DataPhysicalAddr;
+ RemainedData = (UINTN)DataLength;
+ MemAddr = (UINTN)DataPhysicalAddr;
CommandList->AhciCmdPrdtl = PrdtNumber;
for (PrdtIndex = 0; PrdtIndex < PrdtNumber; PrdtIndex++) {
@@ -540,11 +534,11 @@ AhciBuildCommand ( AhciRegisters->AhciCommandTable->PrdtTable[PrdtIndex].AhciPrdtDbc = EFI_AHCI_MAX_DATA_PER_PRDT - 1;
}
- Data64.Uint64 = (UINT64)MemAddr;
+ Data64.Uint64 = (UINT64)MemAddr;
AhciRegisters->AhciCommandTable->PrdtTable[PrdtIndex].AhciPrdtDba = Data64.Uint32.Lower32;
AhciRegisters->AhciCommandTable->PrdtTable[PrdtIndex].AhciPrdtDbau = Data64.Uint32.Upper32;
- RemainedData -= EFI_AHCI_MAX_DATA_PER_PRDT;
- MemAddr += EFI_AHCI_MAX_DATA_PER_PRDT;
+ RemainedData -= EFI_AHCI_MAX_DATA_PER_PRDT;
+ MemAddr += EFI_AHCI_MAX_DATA_PER_PRDT;
}
//
@@ -555,16 +549,15 @@ AhciBuildCommand ( }
CopyMem (
- (VOID *) ((UINTN) AhciRegisters->AhciCmdList + (UINTN) CommandSlotNumber * sizeof (EFI_AHCI_COMMAND_LIST)),
+ (VOID *)((UINTN)AhciRegisters->AhciCmdList + (UINTN)CommandSlotNumber * sizeof (EFI_AHCI_COMMAND_LIST)),
CommandList,
sizeof (EFI_AHCI_COMMAND_LIST)
);
- Data64.Uint64 = (UINT64)(UINTN) AhciRegisters->AhciCommandTablePciAddr;
+ Data64.Uint64 = (UINT64)(UINTN)AhciRegisters->AhciCommandTablePciAddr;
AhciRegisters->AhciCmdList[CommandSlotNumber].AhciCmdCtba = Data64.Uint32.Lower32;
AhciRegisters->AhciCmdList[CommandSlotNumber].AhciCmdCtbau = Data64.Uint32.Upper32;
AhciRegisters->AhciCmdList[CommandSlotNumber].AhciCmdPmp = PortMultiplier;
-
}
/**
@@ -577,8 +570,8 @@ AhciBuildCommand ( VOID
EFIAPI
AhciBuildCommandFis (
- IN OUT EFI_AHCI_COMMAND_FIS *CmdFis,
- IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock
+ IN OUT EFI_AHCI_COMMAND_FIS *CmdFis,
+ IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock
)
{
ZeroMem (CmdFis, sizeof (EFI_AHCI_COMMAND_FIS));
@@ -587,25 +580,25 @@ AhciBuildCommandFis ( //
// Indicator it's a command
//
- CmdFis->AhciCFisCmdInd = 0x1;
- CmdFis->AhciCFisCmd = AtaCommandBlock->AtaCommand;
+ CmdFis->AhciCFisCmdInd = 0x1;
+ CmdFis->AhciCFisCmd = AtaCommandBlock->AtaCommand;
- CmdFis->AhciCFisFeature = AtaCommandBlock->AtaFeatures;
- CmdFis->AhciCFisFeatureExp = AtaCommandBlock->AtaFeaturesExp;
+ CmdFis->AhciCFisFeature = AtaCommandBlock->AtaFeatures;
+ CmdFis->AhciCFisFeatureExp = AtaCommandBlock->AtaFeaturesExp;
- CmdFis->AhciCFisSecNum = AtaCommandBlock->AtaSectorNumber;
- CmdFis->AhciCFisSecNumExp = AtaCommandBlock->AtaSectorNumberExp;
+ CmdFis->AhciCFisSecNum = AtaCommandBlock->AtaSectorNumber;
+ CmdFis->AhciCFisSecNumExp = AtaCommandBlock->AtaSectorNumberExp;
- CmdFis->AhciCFisClyLow = AtaCommandBlock->AtaCylinderLow;
- CmdFis->AhciCFisClyLowExp = AtaCommandBlock->AtaCylinderLowExp;
+ CmdFis->AhciCFisClyLow = AtaCommandBlock->AtaCylinderLow;
+ CmdFis->AhciCFisClyLowExp = AtaCommandBlock->AtaCylinderLowExp;
- CmdFis->AhciCFisClyHigh = AtaCommandBlock->AtaCylinderHigh;
- CmdFis->AhciCFisClyHighExp = AtaCommandBlock->AtaCylinderHighExp;
+ CmdFis->AhciCFisClyHigh = AtaCommandBlock->AtaCylinderHigh;
+ CmdFis->AhciCFisClyHighExp = AtaCommandBlock->AtaCylinderHighExp;
CmdFis->AhciCFisSecCount = AtaCommandBlock->AtaSectorCount;
CmdFis->AhciCFisSecCountExp = AtaCommandBlock->AtaSectorCountExp;
- CmdFis->AhciCFisDevHead = (UINT8) (AtaCommandBlock->AtaDeviceHead | 0xE0);
+ CmdFis->AhciCFisDevHead = (UINT8)(AtaCommandBlock->AtaDeviceHead | 0xE0);
}
/**
@@ -621,11 +614,11 @@ EFI_STATUS AhciWaitDeviceReady (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT8 Port
- )
+ )
{
- UINT32 PhyDetectDelay;
- UINT32 Data;
- UINT32 Offset;
+ UINT32 PhyDetectDelay;
+ UINT32 Data;
+ UINT32 Offset;
//
// According to SATA1.0a spec section 5.2, we need to wait for PxTFD.BSY and PxTFD.DRQ
@@ -634,9 +627,10 @@ AhciWaitDeviceReady ( PhyDetectDelay = 16 * 1000;
do {
Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SERR;
- if (AhciReadReg(PciIo, Offset) != 0) {
- AhciWriteReg (PciIo, Offset, AhciReadReg(PciIo, Offset));
+ if (AhciReadReg (PciIo, Offset) != 0) {
+ AhciWriteReg (PciIo, Offset, AhciReadReg (PciIo, Offset));
}
+
Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_TFD;
Data = AhciReadReg (PciIo, Offset) & EFI_AHCI_PORT_TFD_MASK;
@@ -656,7 +650,6 @@ AhciWaitDeviceReady ( }
}
-
/**
Reset the SATA port. Algorithm follows AHCI spec 1.3.1 section 10.4.2
@@ -681,7 +674,7 @@ AhciResetPort ( // SW is required to keep DET set to 0x1 at least for 1 milisecond to ensure that
// at least one COMRESET signal is sent.
//
- MicroSecondDelay(1000);
+ MicroSecondDelay (1000);
AhciAndReg (PciIo, Offset, ~(UINT32)EFI_AHCI_PORT_SSTS_DET_MASK);
Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SSTS;
@@ -715,7 +708,7 @@ AhciRecoverPortError ( UINT32 PortTfd;
EFI_STATUS Status;
- Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_IS;
+ Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_IS;
PortInterrupt = AhciReadReg (PciIo, Offset);
if ((PortInterrupt & EFI_AHCI_PORT_IS_FATAL_ERROR_MASK) == 0) {
//
@@ -738,7 +731,7 @@ AhciRecoverPortError ( // If TFD.BSY or TFD.DRQ is still set it means that drive is hung and software has
// to reset it before sending any additional commands.
//
- Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_TFD;
+ Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_TFD;
PortTfd = AhciReadReg (PciIo, Offset);
if ((PortTfd & (EFI_AHCI_PORT_TFD_BSY | EFI_AHCI_PORT_TFD_DRQ)) != 0) {
Status = AhciResetPort (PciIo, Port);
@@ -768,16 +761,17 @@ AhciCheckFisReceived ( IN SATA_FIS_TYPE FisType
)
{
- UINT32 Offset;
- UINT32 PortInterrupt;
- UINT32 PortTfd;
+ UINT32 Offset;
+ UINT32 PortInterrupt;
+ UINT32 PortTfd;
- Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_IS;
+ Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_IS;
PortInterrupt = AhciReadReg (PciIo, Offset);
if ((PortInterrupt & EFI_AHCI_PORT_IS_ERROR_MASK) != 0) {
DEBUG ((DEBUG_ERROR, "AHCI: Error interrupt reported PxIS: %X\n", PortInterrupt));
return EFI_DEVICE_ERROR;
}
+
//
// For PIO setup FIS - According to SATA 2.6 spec section 11.7, D2h FIS means an error encountered.
// But Qemu and Marvel 9230 sata controller may just receive a D2h FIS from device
@@ -786,10 +780,11 @@ AhciCheckFisReceived ( // By this way, we can know if there is a real error happened.
//
if (((FisType == SataFisD2H) && ((PortInterrupt & EFI_AHCI_PORT_IS_DHRS) != 0)) ||
- ((FisType == SataFisPioSetup) && (PortInterrupt & (EFI_AHCI_PORT_IS_PSS | EFI_AHCI_PORT_IS_DHRS)) != 0) ||
- ((FisType == SataFisDmaSetup) && (PortInterrupt & (EFI_AHCI_PORT_IS_DSS | EFI_AHCI_PORT_IS_DHRS)) != 0)) {
- Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_TFD;
- PortTfd = AhciReadReg (PciIo, (UINT32) Offset);
+ ((FisType == SataFisPioSetup) && ((PortInterrupt & (EFI_AHCI_PORT_IS_PSS | EFI_AHCI_PORT_IS_DHRS)) != 0)) ||
+ ((FisType == SataFisDmaSetup) && ((PortInterrupt & (EFI_AHCI_PORT_IS_DSS | EFI_AHCI_PORT_IS_DHRS)) != 0)))
+ {
+ Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_TFD;
+ PortTfd = AhciReadReg (PciIo, (UINT32)Offset);
if ((PortTfd & EFI_AHCI_PORT_TFD_ERR) != 0) {
return EFI_DEVICE_ERROR;
} else {
@@ -836,6 +831,7 @@ AhciWaitUntilFisReceived ( if (Status != EFI_NOT_READY) {
return Status;
}
+
//
// Stall for 100 microseconds.
//
@@ -929,30 +925,30 @@ AhciPrintStatusBlock ( EFI_STATUS
EFIAPI
AhciPioTransfer (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN EFI_AHCI_REGISTERS *AhciRegisters,
- IN UINT8 Port,
- IN UINT8 PortMultiplier,
- IN EFI_AHCI_ATAPI_COMMAND *AtapiCommand OPTIONAL,
- IN UINT8 AtapiCommandLength,
- IN BOOLEAN Read,
- IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock,
- IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock,
- IN OUT VOID *MemoryAddr,
- IN UINT32 DataCount,
- IN UINT64 Timeout,
- IN ATA_NONBLOCK_TASK *Task
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN EFI_AHCI_REGISTERS *AhciRegisters,
+ IN UINT8 Port,
+ IN UINT8 PortMultiplier,
+ IN EFI_AHCI_ATAPI_COMMAND *AtapiCommand OPTIONAL,
+ IN UINT8 AtapiCommandLength,
+ IN BOOLEAN Read,
+ IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock,
+ IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock,
+ IN OUT VOID *MemoryAddr,
+ IN UINT32 DataCount,
+ IN UINT64 Timeout,
+ IN ATA_NONBLOCK_TASK *Task
)
{
- EFI_STATUS Status;
- EFI_PHYSICAL_ADDRESS PhyAddr;
- VOID *Map;
- UINTN MapLength;
- EFI_PCI_IO_PROTOCOL_OPERATION Flag;
- EFI_AHCI_COMMAND_FIS CFis;
- EFI_AHCI_COMMAND_LIST CmdList;
- UINT32 PrdCount;
- UINT32 Retry;
+ EFI_STATUS Status;
+ EFI_PHYSICAL_ADDRESS PhyAddr;
+ VOID *Map;
+ UINTN MapLength;
+ EFI_PCI_IO_PROTOCOL_OPERATION Flag;
+ EFI_AHCI_COMMAND_FIS CFis;
+ EFI_AHCI_COMMAND_LIST CmdList;
+ UINT32 PrdCount;
+ UINT32 Retry;
if (Read) {
Flag = EfiPciIoOperationBusMasterWrite;
@@ -964,14 +960,14 @@ AhciPioTransfer ( // construct command list and command table with pci bus address
//
MapLength = DataCount;
- Status = PciIo->Map (
- PciIo,
- Flag,
- MemoryAddr,
- &MapLength,
- &PhyAddr,
- &Map
- );
+ Status = PciIo->Map (
+ PciIo,
+ Flag,
+ MemoryAddr,
+ &MapLength,
+ &PhyAddr,
+ &Map
+ );
if (EFI_ERROR (Status) || (DataCount != MapLength)) {
return EFI_BAD_BUFFER_SIZE;
@@ -1005,11 +1001,11 @@ AhciPioTransfer ( DEBUG ((DEBUG_VERBOSE, "Starting command for PIO transfer:\n"));
AhciPrintCommandBlock (AtaCommandBlock, DEBUG_VERBOSE);
Status = AhciStartCommand (
- PciIo,
- Port,
- 0,
- Timeout
- );
+ PciIo,
+ Port,
+ 0,
+ Timeout
+ );
if (EFI_ERROR (Status)) {
break;
}
@@ -1017,7 +1013,7 @@ AhciPioTransfer ( if (Read && (AtapiCommand == 0)) {
Status = AhciWaitUntilFisReceived (PciIo, Port, Timeout, SataFisPioSetup);
if (Status == EFI_SUCCESS) {
- PrdCount = *(volatile UINT32 *) (&(AhciRegisters->AhciCmdList[0].AhciCmdPrdbc));
+ PrdCount = *(volatile UINT32 *)(&(AhciRegisters->AhciCmdList[0].AhciCmdPrdbc));
if (PrdCount == DataCount) {
Status = EFI_SUCCESS;
} else {
@@ -1052,9 +1048,9 @@ AhciPioTransfer ( );
PciIo->Unmap (
- PciIo,
- Map
- );
+ PciIo,
+ Map
+ );
AhciDumpPortStatus (PciIo, AhciRegisters, Port, AtaStatusBlock);
@@ -1101,31 +1097,31 @@ AhciPioTransfer ( EFI_STATUS
EFIAPI
AhciDmaTransfer (
- IN ATA_ATAPI_PASS_THRU_INSTANCE *Instance,
- IN EFI_AHCI_REGISTERS *AhciRegisters,
- IN UINT8 Port,
- IN UINT8 PortMultiplier,
- IN EFI_AHCI_ATAPI_COMMAND *AtapiCommand OPTIONAL,
- IN UINT8 AtapiCommandLength,
- IN BOOLEAN Read,
- IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock,
- IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock,
- IN OUT VOID *MemoryAddr,
- IN UINT32 DataCount,
- IN UINT64 Timeout,
- IN ATA_NONBLOCK_TASK *Task
+ IN ATA_ATAPI_PASS_THRU_INSTANCE *Instance,
+ IN EFI_AHCI_REGISTERS *AhciRegisters,
+ IN UINT8 Port,
+ IN UINT8 PortMultiplier,
+ IN EFI_AHCI_ATAPI_COMMAND *AtapiCommand OPTIONAL,
+ IN UINT8 AtapiCommandLength,
+ IN BOOLEAN Read,
+ IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock,
+ IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock,
+ IN OUT VOID *MemoryAddr,
+ IN UINT32 DataCount,
+ IN UINT64 Timeout,
+ IN ATA_NONBLOCK_TASK *Task
)
{
- EFI_STATUS Status;
- EFI_PHYSICAL_ADDRESS PhyAddr;
- VOID *Map;
- UINTN MapLength;
- EFI_PCI_IO_PROTOCOL_OPERATION Flag;
- EFI_AHCI_COMMAND_FIS CFis;
- EFI_AHCI_COMMAND_LIST CmdList;
- EFI_PCI_IO_PROTOCOL *PciIo;
- EFI_TPL OldTpl;
- UINT32 Retry;
+ EFI_STATUS Status;
+ EFI_PHYSICAL_ADDRESS PhyAddr;
+ VOID *Map;
+ UINTN MapLength;
+ EFI_PCI_IO_PROTOCOL_OPERATION Flag;
+ EFI_AHCI_COMMAND_FIS CFis;
+ EFI_AHCI_COMMAND_LIST CmdList;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ EFI_TPL OldTpl;
+ UINT32 Retry;
Map = NULL;
PciIo = Instance->PciIo;
@@ -1151,24 +1147,25 @@ AhciDmaTransfer ( }
MapLength = DataCount;
- Status = PciIo->Map (
- PciIo,
- Flag,
- MemoryAddr,
- &MapLength,
- &PhyAddr,
- &Map
- );
+ Status = PciIo->Map (
+ PciIo,
+ Flag,
+ MemoryAddr,
+ &MapLength,
+ &PhyAddr,
+ &Map
+ );
if (EFI_ERROR (Status) || (DataCount != MapLength)) {
return EFI_BAD_BUFFER_SIZE;
}
+
if (Task != NULL) {
Task->Map = Map;
}
}
- if (Task == NULL || (Task != NULL && !Task->IsStart)) {
+ if ((Task == NULL) || ((Task != NULL) && !Task->IsStart)) {
AhciBuildCommandFis (&CFis, AtaCommandBlock);
ZeroMem (&CmdList, sizeof (EFI_AHCI_COMMAND_LIST));
@@ -1191,6 +1188,7 @@ AhciDmaTransfer ( //
MicroSecondDelay (100);
}
+
gBS->RestoreTPL (OldTpl);
for (Retry = 0; Retry < AHCI_COMMAND_RETRIES; Retry++) {
AhciBuildCommand (
@@ -1210,14 +1208,15 @@ AhciDmaTransfer ( DEBUG ((DEBUG_VERBOSE, "Starting command for sync DMA transfer:\n"));
AhciPrintCommandBlock (AtaCommandBlock, DEBUG_VERBOSE);
Status = AhciStartCommand (
- PciIo,
- Port,
- 0,
- Timeout
- );
+ PciIo,
+ Port,
+ 0,
+ Timeout
+ );
if (EFI_ERROR (Status)) {
break;
}
+
Status = AhciWaitUntilFisReceived (PciIo, Port, Timeout, SataFisD2H);
if (Status == EFI_DEVICE_ERROR) {
DEBUG ((DEBUG_ERROR, "DMA command failed at retry: %d\n", Retry));
@@ -1248,15 +1247,16 @@ AhciDmaTransfer ( DEBUG ((DEBUG_VERBOSE, "Starting command for async DMA transfer:\n"));
AhciPrintCommandBlock (AtaCommandBlock, DEBUG_VERBOSE);
Status = AhciStartCommand (
- PciIo,
- Port,
- 0,
- Timeout
- );
+ PciIo,
+ Port,
+ 0,
+ Timeout
+ );
if (!EFI_ERROR (Status)) {
Task->IsStart = TRUE;
}
}
+
if (Task->IsStart) {
Status = AhciCheckFisReceived (PciIo, Port, SataFisD2H);
if (Status == EFI_DEVICE_ERROR) {
@@ -1270,12 +1270,12 @@ AhciDmaTransfer ( //
if (Status == EFI_SUCCESS) {
Task->IsStart = FALSE;
- Status = EFI_NOT_READY;
+ Status = EFI_NOT_READY;
}
}
if (Status == EFI_NOT_READY) {
- if (!Task->InfiniteWait && Task->RetryTimes == 0) {
+ if (!Task->InfiniteWait && (Task->RetryTimes == 0)) {
Status = EFI_TIMEOUT;
} else {
Task->RetryTimes--;
@@ -1291,9 +1291,10 @@ AhciDmaTransfer ( // EFI_NOT_READY that means the command doesn't finished, try again.), first do the
// context cleanup, then set the packet's Asb status.
//
- if (Task == NULL ||
+ if ((Task == NULL) ||
((Task != NULL) && (Status != EFI_NOT_READY))
- ) {
+ )
+ {
AhciStopCommand (
PciIo,
Port,
@@ -1358,22 +1359,22 @@ AhciDmaTransfer ( EFI_STATUS
EFIAPI
AhciNonDataTransfer (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN EFI_AHCI_REGISTERS *AhciRegisters,
- IN UINT8 Port,
- IN UINT8 PortMultiplier,
- IN EFI_AHCI_ATAPI_COMMAND *AtapiCommand OPTIONAL,
- IN UINT8 AtapiCommandLength,
- IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock,
- IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock,
- IN UINT64 Timeout,
- IN ATA_NONBLOCK_TASK *Task
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN EFI_AHCI_REGISTERS *AhciRegisters,
+ IN UINT8 Port,
+ IN UINT8 PortMultiplier,
+ IN EFI_AHCI_ATAPI_COMMAND *AtapiCommand OPTIONAL,
+ IN UINT8 AtapiCommandLength,
+ IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock,
+ IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock,
+ IN UINT64 Timeout,
+ IN ATA_NONBLOCK_TASK *Task
)
{
- EFI_STATUS Status;
- EFI_AHCI_COMMAND_FIS CFis;
- EFI_AHCI_COMMAND_LIST CmdList;
- UINT32 Retry;
+ EFI_STATUS Status;
+ EFI_AHCI_COMMAND_FIS CFis;
+ EFI_AHCI_COMMAND_LIST CmdList;
+ UINT32 Retry;
//
// Package read needed
@@ -1402,11 +1403,11 @@ AhciNonDataTransfer ( DEBUG ((DEBUG_VERBOSE, "Starting command for non data transfer:\n"));
AhciPrintCommandBlock (AtaCommandBlock, DEBUG_VERBOSE);
Status = AhciStartCommand (
- PciIo,
- Port,
- 0,
- Timeout
- );
+ PciIo,
+ Port,
+ 0,
+ Timeout
+ );
if (EFI_ERROR (Status)) {
break;
}
@@ -1467,13 +1468,13 @@ AhciNonDataTransfer ( EFI_STATUS
EFIAPI
AhciStopCommand (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN UINT8 Port,
- IN UINT64 Timeout
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN UINT8 Port,
+ IN UINT64 Timeout
)
{
- UINT32 Offset;
- UINT32 Data;
+ UINT32 Offset;
+ UINT32 Data;
Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
Data = AhciReadReg (PciIo, Offset);
@@ -1483,7 +1484,7 @@ AhciStopCommand ( }
if ((Data & EFI_AHCI_PORT_CMD_ST) != 0) {
- AhciAndReg (PciIo, Offset, (UINT32)~(EFI_AHCI_PORT_CMD_ST));
+ AhciAndReg (PciIo, Offset, (UINT32) ~(EFI_AHCI_PORT_CMD_ST));
}
return AhciWaitMmioSet (
@@ -1511,26 +1512,26 @@ AhciStopCommand ( EFI_STATUS
EFIAPI
AhciStartCommand (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN UINT8 Port,
- IN UINT8 CommandSlot,
- IN UINT64 Timeout
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN UINT8 Port,
+ IN UINT8 CommandSlot,
+ IN UINT64 Timeout
)
{
- UINT32 CmdSlotBit;
- EFI_STATUS Status;
- UINT32 PortStatus;
- UINT32 StartCmd;
- UINT32 PortTfd;
- UINT32 Offset;
- UINT32 Capability;
+ UINT32 CmdSlotBit;
+ EFI_STATUS Status;
+ UINT32 PortStatus;
+ UINT32 StartCmd;
+ UINT32 PortTfd;
+ UINT32 Offset;
+ UINT32 Capability;
//
// Collect AHCI controller information
//
- Capability = AhciReadReg(PciIo, EFI_AHCI_CAPABILITY_OFFSET);
+ Capability = AhciReadReg (PciIo, EFI_AHCI_CAPABILITY_OFFSET);
- CmdSlotBit = (UINT32) (1 << CommandSlot);
+ CmdSlotBit = (UINT32)(1 << CommandSlot);
AhciClearPortStatus (
PciIo,
@@ -1547,17 +1548,17 @@ AhciStartCommand ( return Status;
}
- Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
+ Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
PortStatus = AhciReadReg (PciIo, Offset);
StartCmd = 0;
if ((PortStatus & EFI_AHCI_PORT_CMD_ALPE) != 0) {
- StartCmd = AhciReadReg (PciIo, Offset);
+ StartCmd = AhciReadReg (PciIo, Offset);
StartCmd &= ~EFI_AHCI_PORT_CMD_ICC_MASK;
StartCmd |= EFI_AHCI_PORT_CMD_ACTIVE;
}
- Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_TFD;
+ Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_TFD;
PortTfd = AhciReadReg (PciIo, Offset);
if ((PortTfd & (EFI_AHCI_PORT_TFD_BSY | EFI_AHCI_PORT_TFD_DRQ)) != 0) {
@@ -1588,7 +1589,6 @@ AhciStartCommand ( return EFI_SUCCESS;
}
-
/**
Do AHCI HBA reset.
@@ -1603,17 +1603,17 @@ AhciStartCommand ( EFI_STATUS
EFIAPI
AhciReset (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN UINT64 Timeout
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN UINT64 Timeout
)
{
- UINT64 Delay;
- UINT32 Value;
+ UINT64 Delay;
+ UINT32 Value;
//
// Make sure that GHC.AE bit is set before accessing any AHCI registers.
//
- Value = AhciReadReg(PciIo, EFI_AHCI_GHC_OFFSET);
+ Value = AhciReadReg (PciIo, EFI_AHCI_GHC_OFFSET);
if ((Value & EFI_AHCI_GHC_ENABLE) == 0) {
AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_ENABLE);
@@ -1621,10 +1621,10 @@ AhciReset ( AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_RESET);
- Delay = DivU64x32(Timeout, 1000) + 1;
+ Delay = DivU64x32 (Timeout, 1000) + 1;
do {
- Value = AhciReadReg(PciIo, EFI_AHCI_GHC_OFFSET);
+ Value = AhciReadReg (PciIo, EFI_AHCI_GHC_OFFSET);
if ((Value & EFI_AHCI_GHC_RESET) == 0) {
break;
@@ -1633,7 +1633,7 @@ AhciReset ( //
// Stall for 100 microseconds.
//
- MicroSecondDelay(100);
+ MicroSecondDelay (100);
Delay--;
} while (Delay > 0);
@@ -1661,19 +1661,19 @@ AhciReset ( EFI_STATUS
EFIAPI
AhciAtaSmartReturnStatusCheck (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN EFI_AHCI_REGISTERS *AhciRegisters,
- IN UINT8 Port,
- IN UINT8 PortMultiplier,
- IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN EFI_AHCI_REGISTERS *AhciRegisters,
+ IN UINT8 Port,
+ IN UINT8 PortMultiplier,
+ IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock
)
{
- EFI_STATUS Status;
- EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
- UINT8 LBAMid;
- UINT8 LBAHigh;
- UINTN FisBaseAddr;
- UINT32 Value;
+ EFI_STATUS Status;
+ EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
+ UINT8 LBAMid;
+ UINT8 LBAHigh;
+ UINTN FisBaseAddr;
+ UINT32 Value;
ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
@@ -1713,7 +1713,7 @@ AhciAtaSmartReturnStatusCheck ( FisBaseAddr = (UINTN)AhciRegisters->AhciRFis + Port * sizeof (EFI_AHCI_RECEIVED_FIS);
- Value = *(UINT32 *) (FisBaseAddr + EFI_AHCI_D2H_FIS_OFFSET);
+ Value = *(UINT32 *)(FisBaseAddr + EFI_AHCI_D2H_FIS_OFFSET);
if ((Value & EFI_AHCI_FIS_TYPE_MASK) == EFI_AHCI_FIS_REGISTER_D2H) {
LBAMid = ((UINT8 *)(UINTN)(FisBaseAddr + EFI_AHCI_D2H_FIS_OFFSET))[5];
@@ -1725,18 +1725,18 @@ AhciAtaSmartReturnStatusCheck ( //
DEBUG ((DEBUG_INFO, "The S.M.A.R.T threshold exceeded condition is not detected\n"));
REPORT_STATUS_CODE (
- EFI_PROGRESS_CODE,
- (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_UNDERTHRESHOLD)
- );
+ EFI_PROGRESS_CODE,
+ (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_UNDERTHRESHOLD)
+ );
} else if ((LBAMid == 0xf4) && (LBAHigh == 0x2c)) {
//
// The threshold exceeded condition is detected by the device
//
DEBUG ((DEBUG_INFO, "The S.M.A.R.T threshold exceeded condition is detected\n"));
REPORT_STATUS_CODE (
- EFI_PROGRESS_CODE,
- (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_OVERTHRESHOLD)
- );
+ EFI_PROGRESS_CODE,
+ (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_OVERTHRESHOLD)
+ );
}
}
@@ -1757,16 +1757,16 @@ AhciAtaSmartReturnStatusCheck ( VOID
EFIAPI
AhciAtaSmartSupport (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN EFI_AHCI_REGISTERS *AhciRegisters,
- IN UINT8 Port,
- IN UINT8 PortMultiplier,
- IN EFI_IDENTIFY_DATA *IdentifyData,
- IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN EFI_AHCI_REGISTERS *AhciRegisters,
+ IN UINT8 Port,
+ IN UINT8 PortMultiplier,
+ IN EFI_IDENTIFY_DATA *IdentifyData,
+ IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock
)
{
- EFI_STATUS Status;
- EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
+ EFI_STATUS Status;
+ EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
//
// Detect if the device supports S.M.A.R.T.
@@ -1775,8 +1775,12 @@ AhciAtaSmartSupport ( //
// S.M.A.R.T is not supported by the device
//
- DEBUG ((DEBUG_INFO, "S.M.A.R.T feature is not supported at port [%d] PortMultiplier [%d]!\n",
- Port, PortMultiplier));
+ DEBUG ((
+ DEBUG_INFO,
+ "S.M.A.R.T feature is not supported at port [%d] PortMultiplier [%d]!\n",
+ Port,
+ PortMultiplier
+ ));
REPORT_STATUS_CODE (
EFI_ERROR_CODE | EFI_ERROR_MINOR,
(EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_NOTSUPPORTED)
@@ -1786,7 +1790,6 @@ AhciAtaSmartSupport ( // Check if the feature is enabled. If not, then enable S.M.A.R.T.
//
if ((IdentifyData->AtaData.command_set_feature_enb_85 & 0x0001) != 0x0001) {
-
REPORT_STATUS_CODE (
EFI_PROGRESS_CODE,
(EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_DISABLE)
@@ -1815,7 +1818,6 @@ AhciAtaSmartSupport ( NULL
);
-
if (!EFI_ERROR (Status)) {
//
// Send S.M.A.R.T AutoSave command to device
@@ -1851,11 +1853,15 @@ AhciAtaSmartSupport ( AtaStatusBlock
);
- DEBUG ((DEBUG_INFO, "Enabled S.M.A.R.T feature at port [%d] PortMultiplier [%d]!\n",
- Port, PortMultiplier));
+ DEBUG ((
+ DEBUG_INFO,
+ "Enabled S.M.A.R.T feature at port [%d] PortMultiplier [%d]!\n",
+ Port,
+ PortMultiplier
+ ));
}
- return ;
+ return;
}
/**
@@ -1876,18 +1882,18 @@ AhciAtaSmartSupport ( EFI_STATUS
EFIAPI
AhciIdentify (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN EFI_AHCI_REGISTERS *AhciRegisters,
- IN UINT8 Port,
- IN UINT8 PortMultiplier,
- IN OUT EFI_IDENTIFY_DATA *Buffer
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN EFI_AHCI_REGISTERS *AhciRegisters,
+ IN UINT8 Port,
+ IN UINT8 PortMultiplier,
+ IN OUT EFI_IDENTIFY_DATA *Buffer
)
{
- EFI_STATUS Status;
- EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
- EFI_ATA_STATUS_BLOCK AtaStatusBlock;
+ EFI_STATUS Status;
+ EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
+ EFI_ATA_STATUS_BLOCK AtaStatusBlock;
- if (PciIo == NULL || AhciRegisters == NULL || Buffer == NULL) {
+ if ((PciIo == NULL) || (AhciRegisters == NULL) || (Buffer == NULL)) {
return EFI_INVALID_PARAMETER;
}
@@ -1934,18 +1940,18 @@ AhciIdentify ( EFI_STATUS
EFIAPI
AhciIdentifyPacket (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN EFI_AHCI_REGISTERS *AhciRegisters,
- IN UINT8 Port,
- IN UINT8 PortMultiplier,
- IN OUT EFI_IDENTIFY_DATA *Buffer
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN EFI_AHCI_REGISTERS *AhciRegisters,
+ IN UINT8 Port,
+ IN UINT8 PortMultiplier,
+ IN OUT EFI_IDENTIFY_DATA *Buffer
)
{
- EFI_STATUS Status;
- EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
- EFI_ATA_STATUS_BLOCK AtaStatusBlock;
+ EFI_STATUS Status;
+ EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
+ EFI_ATA_STATUS_BLOCK AtaStatusBlock;
- if (PciIo == NULL || AhciRegisters == NULL) {
+ if ((PciIo == NULL) || (AhciRegisters == NULL)) {
return EFI_INVALID_PARAMETER;
}
@@ -1994,29 +2000,29 @@ AhciIdentifyPacket ( EFI_STATUS
EFIAPI
AhciDeviceSetFeature (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN EFI_AHCI_REGISTERS *AhciRegisters,
- IN UINT8 Port,
- IN UINT8 PortMultiplier,
- IN UINT16 Feature,
- IN UINT32 FeatureSpecificData,
- IN UINT64 Timeout
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN EFI_AHCI_REGISTERS *AhciRegisters,
+ IN UINT8 Port,
+ IN UINT8 PortMultiplier,
+ IN UINT16 Feature,
+ IN UINT32 FeatureSpecificData,
+ IN UINT64 Timeout
)
{
- EFI_STATUS Status;
- EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
- EFI_ATA_STATUS_BLOCK AtaStatusBlock;
+ EFI_STATUS Status;
+ EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
+ EFI_ATA_STATUS_BLOCK AtaStatusBlock;
ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
ZeroMem (&AtaStatusBlock, sizeof (EFI_ATA_STATUS_BLOCK));
AtaCommandBlock.AtaCommand = ATA_CMD_SET_FEATURES;
- AtaCommandBlock.AtaFeatures = (UINT8) Feature;
- AtaCommandBlock.AtaFeaturesExp = (UINT8) (Feature >> 8);
- AtaCommandBlock.AtaSectorCount = (UINT8) FeatureSpecificData;
- AtaCommandBlock.AtaSectorNumber = (UINT8) (FeatureSpecificData >> 8);
- AtaCommandBlock.AtaCylinderLow = (UINT8) (FeatureSpecificData >> 16);
- AtaCommandBlock.AtaCylinderHigh = (UINT8) (FeatureSpecificData >> 24);
+ AtaCommandBlock.AtaFeatures = (UINT8)Feature;
+ AtaCommandBlock.AtaFeaturesExp = (UINT8)(Feature >> 8);
+ AtaCommandBlock.AtaSectorCount = (UINT8)FeatureSpecificData;
+ AtaCommandBlock.AtaSectorNumber = (UINT8)(FeatureSpecificData >> 8);
+ AtaCommandBlock.AtaCylinderLow = (UINT8)(FeatureSpecificData >> 16);
+ AtaCommandBlock.AtaCylinderHigh = (UINT8)(FeatureSpecificData >> 24);
Status = AhciNonDataTransfer (
PciIo,
@@ -2052,46 +2058,46 @@ AhciDeviceSetFeature ( EFI_STATUS
EFIAPI
AhciPacketCommandExecute (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN EFI_AHCI_REGISTERS *AhciRegisters,
- IN UINT8 Port,
- IN UINT8 PortMultiplier,
- IN EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET *Packet
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN EFI_AHCI_REGISTERS *AhciRegisters,
+ IN UINT8 Port,
+ IN UINT8 PortMultiplier,
+ IN EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET *Packet
)
{
- EFI_STATUS Status;
- VOID *Buffer;
- UINT32 Length;
- EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
- EFI_ATA_STATUS_BLOCK AtaStatusBlock;
- BOOLEAN Read;
-
- if (Packet == NULL || Packet->Cdb == NULL) {
+ EFI_STATUS Status;
+ VOID *Buffer;
+ UINT32 Length;
+ EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
+ EFI_ATA_STATUS_BLOCK AtaStatusBlock;
+ BOOLEAN Read;
+
+ if ((Packet == NULL) || (Packet->Cdb == NULL)) {
return EFI_INVALID_PARAMETER;
}
ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
ZeroMem (&AtaStatusBlock, sizeof (EFI_ATA_STATUS_BLOCK));
- AtaCommandBlock.AtaCommand = ATA_CMD_PACKET;
+ AtaCommandBlock.AtaCommand = ATA_CMD_PACKET;
//
// No OVL; No DMA
//
- AtaCommandBlock.AtaFeatures = 0x00;
+ AtaCommandBlock.AtaFeatures = 0x00;
//
// set the transfersize to ATAPI_MAX_BYTE_COUNT to let the device
// determine how many data should be transferred.
//
- AtaCommandBlock.AtaCylinderLow = (UINT8) (ATAPI_MAX_BYTE_COUNT & 0x00ff);
- AtaCommandBlock.AtaCylinderHigh = (UINT8) (ATAPI_MAX_BYTE_COUNT >> 8);
+ AtaCommandBlock.AtaCylinderLow = (UINT8)(ATAPI_MAX_BYTE_COUNT & 0x00ff);
+ AtaCommandBlock.AtaCylinderHigh = (UINT8)(ATAPI_MAX_BYTE_COUNT >> 8);
if (Packet->DataDirection == EFI_EXT_SCSI_DATA_DIRECTION_READ) {
Buffer = Packet->InDataBuffer;
Length = Packet->InTransferLength;
- Read = TRUE;
+ Read = TRUE;
} else {
Buffer = Packet->OutDataBuffer;
Length = Packet->OutTransferLength;
- Read = FALSE;
+ Read = FALSE;
}
if (Length == 0) {
@@ -2124,6 +2130,7 @@ AhciPacketCommandExecute ( NULL
);
}
+
return Status;
}
@@ -2137,13 +2144,13 @@ AhciPacketCommandExecute ( EFI_STATUS
EFIAPI
AhciCreateTransferDescriptor (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN OUT EFI_AHCI_REGISTERS *AhciRegisters
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN OUT EFI_AHCI_REGISTERS *AhciRegisters
)
{
- EFI_STATUS Status;
- UINTN Bytes;
- VOID *Buffer;
+ EFI_STATUS Status;
+ UINTN Bytes;
+ VOID *Buffer;
UINT32 Capability;
UINT32 PortImplementBitMap;
@@ -2161,31 +2168,31 @@ AhciCreateTransferDescriptor ( //
// Collect AHCI controller information
//
- Capability = AhciReadReg(PciIo, EFI_AHCI_CAPABILITY_OFFSET);
+ Capability = AhciReadReg (PciIo, EFI_AHCI_CAPABILITY_OFFSET);
//
// Get the number of command slots per port supported by this HBA.
//
- MaxCommandSlotNumber = (UINT8) (((Capability & 0x1F00) >> 8) + 1);
- Support64Bit = (BOOLEAN) (((Capability & BIT31) != 0) ? TRUE : FALSE);
+ MaxCommandSlotNumber = (UINT8)(((Capability & 0x1F00) >> 8) + 1);
+ Support64Bit = (BOOLEAN)(((Capability & BIT31) != 0) ? TRUE : FALSE);
- PortImplementBitMap = AhciReadReg(PciIo, EFI_AHCI_PI_OFFSET);
+ PortImplementBitMap = AhciReadReg (PciIo, EFI_AHCI_PI_OFFSET);
//
// Get the highest bit of implemented ports which decides how many bytes are allocated for received FIS.
//
- MaxPortNumber = (UINT8)(UINTN)(HighBitSet32(PortImplementBitMap) + 1);
+ MaxPortNumber = (UINT8)(UINTN)(HighBitSet32 (PortImplementBitMap) + 1);
if (MaxPortNumber == 0) {
return EFI_DEVICE_ERROR;
}
- MaxReceiveFisSize = MaxPortNumber * sizeof (EFI_AHCI_RECEIVED_FIS);
- Status = PciIo->AllocateBuffer (
- PciIo,
- AllocateAnyPages,
- EfiBootServicesData,
- EFI_SIZE_TO_PAGES ((UINTN) MaxReceiveFisSize),
- &Buffer,
- 0
- );
+ MaxReceiveFisSize = MaxPortNumber * sizeof (EFI_AHCI_RECEIVED_FIS);
+ Status = PciIo->AllocateBuffer (
+ PciIo,
+ AllocateAnyPages,
+ EfiBootServicesData,
+ EFI_SIZE_TO_PAGES ((UINTN)MaxReceiveFisSize),
+ &Buffer,
+ 0
+ );
if (EFI_ERROR (Status)) {
return EFI_OUT_OF_RESOURCES;
@@ -2195,7 +2202,7 @@ AhciCreateTransferDescriptor ( AhciRegisters->AhciRFis = Buffer;
AhciRegisters->MaxReceiveFisSize = MaxReceiveFisSize;
- Bytes = (UINTN)MaxReceiveFisSize;
+ Bytes = (UINTN)MaxReceiveFisSize;
Status = PciIo->Map (
PciIo,
@@ -2221,22 +2228,23 @@ AhciCreateTransferDescriptor ( Status = EFI_DEVICE_ERROR;
goto Error5;
}
+
AhciRegisters->AhciRFisPciAddr = (EFI_AHCI_RECEIVED_FIS *)(UINTN)AhciRFisPciAddr;
//
// Allocate memory for command list
// Note that the implementation is a single task model which only use a command list for all ports.
//
- Buffer = NULL;
+ Buffer = NULL;
MaxCommandListSize = MaxCommandSlotNumber * sizeof (EFI_AHCI_COMMAND_LIST);
- Status = PciIo->AllocateBuffer (
- PciIo,
- AllocateAnyPages,
- EfiBootServicesData,
- EFI_SIZE_TO_PAGES ((UINTN) MaxCommandListSize),
- &Buffer,
- 0
- );
+ Status = PciIo->AllocateBuffer (
+ PciIo,
+ AllocateAnyPages,
+ EfiBootServicesData,
+ EFI_SIZE_TO_PAGES ((UINTN)MaxCommandListSize),
+ &Buffer,
+ 0
+ );
if (EFI_ERROR (Status)) {
//
@@ -2250,7 +2258,7 @@ AhciCreateTransferDescriptor ( AhciRegisters->AhciCmdList = Buffer;
AhciRegisters->MaxCommandListSize = MaxCommandListSize;
- Bytes = (UINTN)MaxCommandListSize;
+ Bytes = (UINTN)MaxCommandListSize;
Status = PciIo->Map (
PciIo,
@@ -2276,20 +2284,21 @@ AhciCreateTransferDescriptor ( Status = EFI_DEVICE_ERROR;
goto Error3;
}
+
AhciRegisters->AhciCmdListPciAddr = (EFI_AHCI_COMMAND_LIST *)(UINTN)AhciCmdListPciAddr;
//
// Allocate memory for command table
// According to AHCI 1.3 spec, a PRD table can contain maximum 65535 entries.
//
- Buffer = NULL;
+ Buffer = NULL;
MaxCommandTableSize = sizeof (EFI_AHCI_COMMAND_TABLE);
Status = PciIo->AllocateBuffer (
PciIo,
AllocateAnyPages,
EfiBootServicesData,
- EFI_SIZE_TO_PAGES ((UINTN) MaxCommandTableSize),
+ EFI_SIZE_TO_PAGES ((UINTN)MaxCommandTableSize),
&Buffer,
0
);
@@ -2306,7 +2315,7 @@ AhciCreateTransferDescriptor ( AhciRegisters->AhciCommandTable = Buffer;
AhciRegisters->MaxCommandTableSize = MaxCommandTableSize;
- Bytes = (UINTN)MaxCommandTableSize;
+ Bytes = (UINTN)MaxCommandTableSize;
Status = PciIo->Map (
PciIo,
@@ -2332,6 +2341,7 @@ AhciCreateTransferDescriptor ( Status = EFI_DEVICE_ERROR;
goto Error1;
}
+
AhciRegisters->AhciCommandTablePciAddr = (EFI_AHCI_COMMAND_TABLE *)(UINTN)AhciCommandTablePciAddr;
return EFI_SUCCESS;
@@ -2346,7 +2356,7 @@ Error1: Error2:
PciIo->FreeBuffer (
PciIo,
- EFI_SIZE_TO_PAGES ((UINTN) MaxCommandTableSize),
+ EFI_SIZE_TO_PAGES ((UINTN)MaxCommandTableSize),
AhciRegisters->AhciCommandTable
);
Error3:
@@ -2357,7 +2367,7 @@ Error3: Error4:
PciIo->FreeBuffer (
PciIo,
- EFI_SIZE_TO_PAGES ((UINTN) MaxCommandListSize),
+ EFI_SIZE_TO_PAGES ((UINTN)MaxCommandListSize),
AhciRegisters->AhciCmdList
);
Error5:
@@ -2368,7 +2378,7 @@ Error5: Error6:
PciIo->FreeBuffer (
PciIo,
- EFI_SIZE_TO_PAGES ((UINTN) MaxReceiveFisSize),
+ EFI_SIZE_TO_PAGES ((UINTN)MaxReceiveFisSize),
AhciRegisters->AhciRFis
);
@@ -2391,19 +2401,19 @@ Error6: **/
EFI_STATUS
AhciReadLogExt (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN EFI_AHCI_REGISTERS *AhciRegisters,
- IN UINT8 Port,
- IN UINT8 PortMultiplier,
- IN OUT UINT8 *Buffer,
- IN UINT8 LogNumber,
- IN UINT8 PageNumber
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN EFI_AHCI_REGISTERS *AhciRegisters,
+ IN UINT8 Port,
+ IN UINT8 PortMultiplier,
+ IN OUT UINT8 *Buffer,
+ IN UINT8 LogNumber,
+ IN UINT8 PageNumber
)
{
- EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
- EFI_ATA_STATUS_BLOCK AtaStatusBlock;
+ EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
+ EFI_ATA_STATUS_BLOCK AtaStatusBlock;
- if (PciIo == NULL || AhciRegisters == NULL || Buffer == NULL) {
+ if ((PciIo == NULL) || (AhciRegisters == NULL) || (Buffer == NULL)) {
return EFI_INVALID_PARAMETER;
}
@@ -2450,11 +2460,11 @@ AhciReadLogExt ( **/
EFI_STATUS
AhciEnableDevSlp (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN EFI_AHCI_REGISTERS *AhciRegisters,
- IN UINT8 Port,
- IN UINT8 PortMultiplier,
- IN EFI_IDENTIFY_DATA *IdentifyData
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN EFI_AHCI_REGISTERS *AhciRegisters,
+ IN UINT8 Port,
+ IN UINT8 PortMultiplier,
+ IN EFI_IDENTIFY_DATA *IdentifyData
)
{
EFI_STATUS Status;
@@ -2488,19 +2498,28 @@ AhciEnableDevSlp ( DEBUG ((DEBUG_INFO, "Port CMD/DEVSLP = %08x / %08x\n", PortCmd, PortDevSlp));
if (((PortDevSlp & AHCI_PORT_DEVSLP_DSP) == 0) ||
((PortCmd & (EFI_AHCI_PORT_CMD_HPCP | EFI_AHCI_PORT_CMD_MPSP)) != 0)
- ) {
+ )
+ {
return EFI_UNSUPPORTED;
}
//
// Do not enable DevSlp if the device doesn't support DevSlp
//
- DEBUG ((DEBUG_INFO, "IDENTIFY DEVICE: [77] = %04x, [78] = %04x, [79] = %04x\n",
- IdentifyData->AtaData.reserved_77,
- IdentifyData->AtaData.serial_ata_features_supported, IdentifyData->AtaData.serial_ata_features_enabled));
+ DEBUG ((
+ DEBUG_INFO,
+ "IDENTIFY DEVICE: [77] = %04x, [78] = %04x, [79] = %04x\n",
+ IdentifyData->AtaData.reserved_77,
+ IdentifyData->AtaData.serial_ata_features_supported,
+ IdentifyData->AtaData.serial_ata_features_enabled
+ ));
if ((IdentifyData->AtaData.serial_ata_features_supported & BIT8) == 0) {
- DEBUG ((DEBUG_INFO, "DevSlp feature is not supported for device at port [%d] PortMultiplier [%d]!\n",
- Port, PortMultiplier));
+ DEBUG ((
+ DEBUG_INFO,
+ "DevSlp feature is not supported for device at port [%d] PortMultiplier [%d]!\n",
+ Port,
+ PortMultiplier
+ ));
return EFI_UNSUPPORTED;
}
@@ -2509,16 +2528,27 @@ AhciEnableDevSlp ( //
if ((IdentifyData->AtaData.serial_ata_features_enabled & BIT8) != 0) {
Status = AhciDeviceSetFeature (
- PciIo, AhciRegisters, Port, 0, ATA_SUB_CMD_ENABLE_SATA_FEATURE, 0x09, ATA_ATAPI_TIMEOUT
- );
- DEBUG ((DEBUG_INFO, "DevSlp set feature for device at port [%d] PortMultiplier [%d] - %r\n",
- Port, PortMultiplier, Status));
+ PciIo,
+ AhciRegisters,
+ Port,
+ 0,
+ ATA_SUB_CMD_ENABLE_SATA_FEATURE,
+ 0x09,
+ ATA_ATAPI_TIMEOUT
+ );
+ DEBUG ((
+ DEBUG_INFO,
+ "DevSlp set feature for device at port [%d] PortMultiplier [%d] - %r\n",
+ Port,
+ PortMultiplier,
+ Status
+ ));
if (EFI_ERROR (Status)) {
return Status;
}
}
- Status = AhciReadLogExt(PciIo, AhciRegisters, Port, PortMultiplier, LogData, 0x30, 0x08);
+ Status = AhciReadLogExt (PciIo, AhciRegisters, Port, PortMultiplier, LogData, 0x30, 0x08);
//
// Clear PxCMD.ST and PxDEVSLP.ADSE before updating PxDEVSLP.DITO and PxDEVSLP.MDAT.
@@ -2541,8 +2571,13 @@ AhciEnableDevSlp ( ZeroMem (&DevSlpTiming, sizeof (DevSlpTiming));
} else {
CopyMem (&DevSlpTiming, &LogData[48], sizeof (DevSlpTiming));
- DEBUG ((DEBUG_INFO, "DevSlpTiming: Supported(%d), Deto(%d), Madt(%d)\n",
- DevSlpTiming.Supported, DevSlpTiming.Deto, DevSlpTiming.Madt));
+ DEBUG ((
+ DEBUG_INFO,
+ "DevSlpTiming: Supported(%d), Deto(%d), Madt(%d)\n",
+ DevSlpTiming.Supported,
+ DevSlpTiming.Deto,
+ DevSlpTiming.Madt
+ ));
}
//
@@ -2574,11 +2609,16 @@ AhciEnableDevSlp ( }
}
-
AhciWriteReg (PciIo, Offset + EFI_AHCI_PORT_CMD, PortCmd);
- DEBUG ((DEBUG_INFO, "Enabled DevSlp feature at port [%d] PortMultiplier [%d], Port CMD/DEVSLP = %08x / %08x\n",
- Port, PortMultiplier, PortCmd, PortDevSlp));
+ DEBUG ((
+ DEBUG_INFO,
+ "Enabled DevSlp feature at port [%d] PortMultiplier [%d], Port CMD/DEVSLP = %08x / %08x\n",
+ Port,
+ PortMultiplier,
+ PortCmd,
+ PortDevSlp
+ ));
return EFI_SUCCESS;
}
@@ -2595,28 +2635,38 @@ AhciEnableDevSlp ( **/
EFI_STATUS
AhciSpinUpDisk (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN EFI_AHCI_REGISTERS *AhciRegisters,
- IN UINT8 Port,
- IN UINT8 PortMultiplier,
- IN OUT EFI_IDENTIFY_DATA *IdentifyData
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN EFI_AHCI_REGISTERS *AhciRegisters,
+ IN UINT8 Port,
+ IN UINT8 PortMultiplier,
+ IN OUT EFI_IDENTIFY_DATA *IdentifyData
)
{
- EFI_STATUS Status;
- EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
- EFI_ATA_STATUS_BLOCK AtaStatusBlock;
- UINT8 Buffer[512];
+ EFI_STATUS Status;
+ EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
+ EFI_ATA_STATUS_BLOCK AtaStatusBlock;
+ UINT8 Buffer[512];
if (IdentifyData->AtaData.specific_config == ATA_SPINUP_CFG_REQUIRED_IDD_INCOMPLETE) {
//
// Use SET_FEATURE subcommand to spin up the device.
//
Status = AhciDeviceSetFeature (
- PciIo, AhciRegisters, Port, PortMultiplier,
- ATA_SUB_CMD_PUIS_SET_DEVICE_SPINUP, 0x00, ATA_SPINUP_TIMEOUT
+ PciIo,
+ AhciRegisters,
+ Port,
+ PortMultiplier,
+ ATA_SUB_CMD_PUIS_SET_DEVICE_SPINUP,
+ 0x00,
+ ATA_SPINUP_TIMEOUT
);
- DEBUG ((DEBUG_INFO, "CMD_PUIS_SET_DEVICE_SPINUP for device at port [%d] PortMultiplier [%d] - %r!\n",
- Port, PortMultiplier, Status));
+ DEBUG ((
+ DEBUG_INFO,
+ "CMD_PUIS_SET_DEVICE_SPINUP for device at port [%d] PortMultiplier [%d] - %r!\n",
+ Port,
+ PortMultiplier,
+ Status
+ ));
if (EFI_ERROR (Status)) {
return Status;
}
@@ -2631,8 +2681,8 @@ AhciSpinUpDisk ( //
// Perform READ SECTORS PIO Data-In command to Read LBA 0
//
- AtaCommandBlock.AtaCommand = ATA_CMD_READ_SECTORS;
- AtaCommandBlock.AtaSectorCount = 0x1;
+ AtaCommandBlock.AtaCommand = ATA_CMD_READ_SECTORS;
+ AtaCommandBlock.AtaSectorCount = 0x1;
Status = AhciPioTransfer (
PciIo,
@@ -2649,8 +2699,13 @@ AhciSpinUpDisk ( ATA_SPINUP_TIMEOUT,
NULL
);
- DEBUG ((DEBUG_INFO, "Read LBA 0 for device at port [%d] PortMultiplier [%d] - %r!\n",
- Port, PortMultiplier, Status));
+ DEBUG ((
+ DEBUG_INFO,
+ "Read LBA 0 for device at port [%d] PortMultiplier [%d] - %r!\n",
+ Port,
+ PortMultiplier,
+ Status
+ ));
if (EFI_ERROR (Status)) {
return Status;
}
@@ -2662,14 +2717,24 @@ AhciSpinUpDisk ( ZeroMem (IdentifyData, sizeof (*IdentifyData));
Status = AhciIdentify (PciIo, AhciRegisters, Port, PortMultiplier, IdentifyData);
if (EFI_ERROR (Status)) {
- DEBUG ((DEBUG_ERROR, "Read IDD failed for device at port [%d] PortMultiplier [%d] - %r!\n",
- Port, PortMultiplier, Status));
+ DEBUG ((
+ DEBUG_ERROR,
+ "Read IDD failed for device at port [%d] PortMultiplier [%d] - %r!\n",
+ Port,
+ PortMultiplier,
+ Status
+ ));
return Status;
}
- DEBUG ((DEBUG_INFO, "IDENTIFY DEVICE: [0] = %016x, [2] = %016x, [83] = %016x, [86] = %016x\n",
- IdentifyData->AtaData.config, IdentifyData->AtaData.specific_config,
- IdentifyData->AtaData.command_set_supported_83, IdentifyData->AtaData.command_set_feature_enb_86));
+ DEBUG ((
+ DEBUG_INFO,
+ "IDENTIFY DEVICE: [0] = %016x, [2] = %016x, [83] = %016x, [86] = %016x\n",
+ IdentifyData->AtaData.config,
+ IdentifyData->AtaData.specific_config,
+ IdentifyData->AtaData.command_set_supported_83,
+ IdentifyData->AtaData.command_set_feature_enb_86
+ ));
//
// Check if IDD is incomplete
//
@@ -2691,13 +2756,13 @@ AhciSpinUpDisk ( **/
EFI_STATUS
AhciPuisEnable (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN EFI_AHCI_REGISTERS *AhciRegisters,
- IN UINT8 Port,
- IN UINT8 PortMultiplier
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN EFI_AHCI_REGISTERS *AhciRegisters,
+ IN UINT8 Port,
+ IN UINT8 PortMultiplier
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
Status = EFI_SUCCESS;
if (mAtaAtapiPolicy->PuisEnable == 0) {
@@ -2705,10 +2770,17 @@ AhciPuisEnable ( } else if (mAtaAtapiPolicy->PuisEnable == 1) {
Status = AhciDeviceSetFeature (PciIo, AhciRegisters, Port, PortMultiplier, ATA_SUB_CMD_ENABLE_PUIS, 0x00, ATA_ATAPI_TIMEOUT);
}
- DEBUG ((DEBUG_INFO, "%a PUIS feature at port [%d] PortMultiplier [%d] - %r!\n",
+
+ DEBUG ((
+ DEBUG_INFO,
+ "%a PUIS feature at port [%d] PortMultiplier [%d] - %r!\n",
(mAtaAtapiPolicy->PuisEnable == 0) ? "Disable" : (
- (mAtaAtapiPolicy->PuisEnable == 1) ? "Enable" : "Skip"
- ), Port, PortMultiplier, Status));
+ (mAtaAtapiPolicy->PuisEnable == 1) ? "Enable" : "Skip"
+ ),
+ Port,
+ PortMultiplier,
+ Status
+ ));
return Status;
}
@@ -2723,28 +2795,28 @@ AhciPuisEnable ( EFI_STATUS
EFIAPI
AhciModeInitialization (
- IN ATA_ATAPI_PASS_THRU_INSTANCE *Instance
+ IN ATA_ATAPI_PASS_THRU_INSTANCE *Instance
)
{
- EFI_STATUS Status;
- EFI_PCI_IO_PROTOCOL *PciIo;
- EFI_IDE_CONTROLLER_INIT_PROTOCOL *IdeInit;
- UINT32 Capability;
- UINT8 MaxPortNumber;
- UINT32 PortImplementBitMap;
-
- EFI_AHCI_REGISTERS *AhciRegisters;
-
- UINT8 Port;
- DATA_64 Data64;
- UINT32 Offset;
- UINT32 Data;
- EFI_IDENTIFY_DATA Buffer;
- EFI_ATA_DEVICE_TYPE DeviceType;
- EFI_ATA_COLLECTIVE_MODE *SupportedModes;
- EFI_ATA_TRANSFER_MODE TransferMode;
- UINT32 PhyDetectDelay;
- UINT32 Value;
+ EFI_STATUS Status;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ EFI_IDE_CONTROLLER_INIT_PROTOCOL *IdeInit;
+ UINT32 Capability;
+ UINT8 MaxPortNumber;
+ UINT32 PortImplementBitMap;
+
+ EFI_AHCI_REGISTERS *AhciRegisters;
+
+ UINT8 Port;
+ DATA_64 Data64;
+ UINT32 Offset;
+ UINT32 Data;
+ EFI_IDENTIFY_DATA Buffer;
+ EFI_ATA_DEVICE_TYPE DeviceType;
+ EFI_ATA_COLLECTIVE_MODE *SupportedModes;
+ EFI_ATA_TRANSFER_MODE TransferMode;
+ UINT32 PhyDetectDelay;
+ UINT32 Value;
if (Instance == NULL) {
return EFI_INVALID_PARAMETER;
@@ -2767,7 +2839,7 @@ AhciModeInitialization ( //
// Make sure that GHC.AE bit is set before accessing any AHCI registers.
//
- Value = AhciReadReg(PciIo, EFI_AHCI_GHC_OFFSET);
+ Value = AhciReadReg (PciIo, EFI_AHCI_GHC_OFFSET);
if ((Value & EFI_AHCI_GHC_ENABLE) == 0) {
AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_ENABLE);
@@ -2785,31 +2857,33 @@ AhciModeInitialization ( NULL
);
if (EFI_ERROR (Status)) {
- DEBUG ((DEBUG_WARN,
+ DEBUG ((
+ DEBUG_WARN,
"AhciModeInitialization: failed to enable 64-bit DMA on 64-bit capable controller (%r)\n",
- Status));
+ Status
+ ));
}
}
//
// Get the number of command slots per port supported by this HBA.
//
- MaxPortNumber = (UINT8) ((Capability & 0x1F) + 1);
+ MaxPortNumber = (UINT8)((Capability & 0x1F) + 1);
//
// Get the bit map of those ports exposed by this HBA.
// It indicates which ports that the HBA supports are available for software to use.
//
- PortImplementBitMap = AhciReadReg(PciIo, EFI_AHCI_PI_OFFSET);
+ PortImplementBitMap = AhciReadReg (PciIo, EFI_AHCI_PI_OFFSET);
AhciRegisters = &Instance->AhciRegisters;
- Status = AhciCreateTransferDescriptor (PciIo, AhciRegisters);
+ Status = AhciCreateTransferDescriptor (PciIo, AhciRegisters);
if (EFI_ERROR (Status)) {
return EFI_OUT_OF_RESOURCES;
}
- for (Port = 0; Port < EFI_AHCI_MAX_PORTS; Port ++) {
+ for (Port = 0; Port < EFI_AHCI_MAX_PORTS; Port++) {
if ((PortImplementBitMap & (((UINT32)BIT0) << Port)) != 0) {
//
// According to AHCI spec, MaxPortNumber should be equal or greater than the number of implemented ports.
@@ -2827,20 +2901,20 @@ AhciModeInitialization ( //
// Initialize FIS Base Address Register and Command List Base Address Register for use.
//
- Data64.Uint64 = (UINTN) (AhciRegisters->AhciRFisPciAddr) + sizeof (EFI_AHCI_RECEIVED_FIS) * Port;
- Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_FB;
+ Data64.Uint64 = (UINTN)(AhciRegisters->AhciRFisPciAddr) + sizeof (EFI_AHCI_RECEIVED_FIS) * Port;
+ Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_FB;
AhciWriteReg (PciIo, Offset, Data64.Uint32.Lower32);
Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_FBU;
AhciWriteReg (PciIo, Offset, Data64.Uint32.Upper32);
- Data64.Uint64 = (UINTN) (AhciRegisters->AhciCmdListPciAddr);
- Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CLB;
+ Data64.Uint64 = (UINTN)(AhciRegisters->AhciCmdListPciAddr);
+ Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CLB;
AhciWriteReg (PciIo, Offset, Data64.Uint32.Lower32);
Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CLBU;
AhciWriteReg (PciIo, Offset, Data64.Uint32.Upper32);
Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
- Data = AhciReadReg (PciIo, Offset);
+ Data = AhciReadReg (PciIo, Offset);
if ((Data & EFI_AHCI_PORT_CMD_CPD) != 0) {
AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_CMD_POD);
}
@@ -2875,7 +2949,7 @@ AhciModeInitialization ( // Wait for the Phy to detect the presence of a device.
//
PhyDetectDelay = EFI_AHCI_BUS_PHY_DETECT_TIMEOUT;
- Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SSTS;
+ Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SSTS;
do {
Data = AhciReadReg (PciIo, Offset) & EFI_AHCI_PORT_SSTS_DET_MASK;
if ((Data == EFI_AHCI_PORT_SSTS_DET_PCE) || (Data == EFI_AHCI_PORT_SSTS_DET)) {
@@ -2910,7 +2984,7 @@ AhciModeInitialization ( Offset,
0x0000FFFF,
0x00000101,
- EFI_TIMER_PERIOD_SECONDS(16)
+ EFI_TIMER_PERIOD_SECONDS (16)
);
if (EFI_ERROR (Status)) {
continue;
@@ -2934,9 +3008,12 @@ AhciModeInitialization ( }
DEBUG ((
- DEBUG_INFO, "IDENTIFY DEVICE: [0] = %016x, [2] = %016x, [83] = %016x, [86] = %016x\n",
- Buffer.AtaData.config, Buffer.AtaData.specific_config,
- Buffer.AtaData.command_set_supported_83, Buffer.AtaData.command_set_feature_enb_86
+ DEBUG_INFO,
+ "IDENTIFY DEVICE: [0] = %016x, [2] = %016x, [83] = %016x, [86] = %016x\n",
+ Buffer.AtaData.config,
+ Buffer.AtaData.specific_config,
+ Buffer.AtaData.command_set_supported_83,
+ Buffer.AtaData.command_set_feature_enb_86
));
if ((Buffer.AtaData.config & BIT2) != 0) {
//
@@ -2959,8 +3036,14 @@ AhciModeInitialization ( } else {
continue;
}
- DEBUG ((DEBUG_INFO, "port [%d] port multitplier [%d] has a [%a]\n",
- Port, 0, DeviceType == EfiIdeCdrom ? "cdrom" : "harddisk"));
+
+ DEBUG ((
+ DEBUG_INFO,
+ "port [%d] port multitplier [%d] has a [%a]\n",
+ Port,
+ 0,
+ DeviceType == EfiIdeCdrom ? "cdrom" : "harddisk"
+ ));
//
// If the device is a hard disk, then try to enable S.M.A.R.T feature
@@ -3004,7 +3087,7 @@ AhciModeInitialization ( TransferMode.ModeCategory = EFI_ATA_MODE_FLOW_PIO;
}
- TransferMode.ModeNumber = (UINT8) (SupportedModes->PioMode.Mode);
+ TransferMode.ModeNumber = (UINT8)(SupportedModes->PioMode.Mode);
//
// Set supported DMA mode on this IDE device. Note that UDMA & MDMA can't
@@ -3014,10 +3097,10 @@ AhciModeInitialization ( //
if (SupportedModes->UdmaMode.Valid) {
TransferMode.ModeCategory = EFI_ATA_MODE_UDMA;
- TransferMode.ModeNumber = (UINT8) (SupportedModes->UdmaMode.Mode);
+ TransferMode.ModeNumber = (UINT8)(SupportedModes->UdmaMode.Mode);
} else if (SupportedModes->MultiWordDmaMode.Valid) {
TransferMode.ModeCategory = EFI_ATA_MODE_MDMA;
- TransferMode.ModeNumber = (UINT8) SupportedModes->MultiWordDmaMode.Mode;
+ TransferMode.ModeNumber = (UINT8)SupportedModes->MultiWordDmaMode.Mode;
}
Status = AhciDeviceSetFeature (PciIo, AhciRegisters, Port, 0, 0x03, (UINT32)(*(UINT8 *)&TransferMode), ATA_ATAPI_TIMEOUT);
|